1 /* SPDX-License-Identifier: (GPL-2.0-only OR B !! 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* 2 /*
3 * This file is provided under a dual BSD/GPLv 3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so und 4 * redistributing this file, you may do so under either license.
5 * 5 *
6 * Copyright(c) 2018 Intel Corporation !! 6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 */ 7 */
8 8
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
11 11
12 #include <sound/sof/header.h> 12 #include <sound/sof/header.h>
13 13
14 /* 14 /*
15 * Component 15 * Component
16 */ 16 */
17 17
18 /* types of component */ 18 /* types of component */
19 enum sof_comp_type { 19 enum sof_comp_type {
20 SOF_COMP_NONE = 0, 20 SOF_COMP_NONE = 0,
21 SOF_COMP_HOST, 21 SOF_COMP_HOST,
22 SOF_COMP_DAI, 22 SOF_COMP_DAI,
23 SOF_COMP_SG_HOST, /**< scatter g 23 SOF_COMP_SG_HOST, /**< scatter gather variant */
24 SOF_COMP_SG_DAI, /**< scatter g 24 SOF_COMP_SG_DAI, /**< scatter gather variant */
25 SOF_COMP_VOLUME, 25 SOF_COMP_VOLUME,
26 SOF_COMP_MIXER, 26 SOF_COMP_MIXER,
27 SOF_COMP_MUX, 27 SOF_COMP_MUX,
28 SOF_COMP_SRC, 28 SOF_COMP_SRC,
29 SOF_COMP_DEPRECATED0, /* Formerly SOF_ !! 29 SOF_COMP_SPLITTER,
30 SOF_COMP_TONE, 30 SOF_COMP_TONE,
31 SOF_COMP_DEPRECATED1, /* Formerly SOF_ !! 31 SOF_COMP_SWITCH,
32 SOF_COMP_BUFFER, 32 SOF_COMP_BUFFER,
33 SOF_COMP_EQ_IIR, 33 SOF_COMP_EQ_IIR,
34 SOF_COMP_EQ_FIR, 34 SOF_COMP_EQ_FIR,
35 SOF_COMP_KEYWORD_DETECT, 35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A k 36 SOF_COMP_KPB, /* A key phrase buffer component */
37 SOF_COMP_SELECTOR, /**< c 37 SOF_COMP_SELECTOR, /**< channel selector component */
38 SOF_COMP_DEMUX, <<
39 SOF_COMP_ASRC, /**< Asynchron <<
40 SOF_COMP_DCBLOCK, <<
41 SOF_COMP_SMART_AMP, /**< s <<
42 SOF_COMP_MODULE_ADAPTER, <<
43 /* keep FILEREAD/FILEWRITE as the last 38 /* keep FILEREAD/FILEWRITE as the last ones */
44 SOF_COMP_FILEREAD = 10000, /**< h 39 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
45 SOF_COMP_FILEWRITE = 10001, /**< h 40 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
46 }; 41 };
47 42
48 /* XRUN action for component */ 43 /* XRUN action for component */
49 #define SOF_XRUN_STOP 1 /**< s 44 #define SOF_XRUN_STOP 1 /**< stop stream */
50 #define SOF_XRUN_UNDER_ZERO 2 /**< s 45 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
51 #define SOF_XRUN_OVER_NULL 4 /**< s 46 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
52 47
53 /* create new generic component - SOF_IPC_TPLG 48 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
54 struct sof_ipc_comp { 49 struct sof_ipc_comp {
55 struct sof_ipc_cmd_hdr hdr; 50 struct sof_ipc_cmd_hdr hdr;
56 uint32_t id; 51 uint32_t id;
57 enum sof_comp_type type; 52 enum sof_comp_type type;
58 uint32_t pipeline_id; 53 uint32_t pipeline_id;
59 uint32_t core; <<
60 54
61 /* extended data length, 0 if no exten !! 55 /* reserved for future use */
62 uint32_t ext_data_length; !! 56 uint32_t reserved[2];
63 } __packed __aligned(4); !! 57 } __packed;
64 58
65 /* 59 /*
66 * Component Buffers 60 * Component Buffers
67 */ 61 */
68 62
69 /* 63 /*
70 * SOF memory capabilities, add new ones at th 64 * SOF memory capabilities, add new ones at the end
71 */ 65 */
72 #define SOF_MEM_CAPS_RAM BIT(0) !! 66 #define SOF_MEM_CAPS_RAM (1 << 0)
73 #define SOF_MEM_CAPS_ROM BIT(1) !! 67 #define SOF_MEM_CAPS_ROM (1 << 1)
74 #define SOF_MEM_CAPS_EXT BIT(2) !! 68 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */
75 #define SOF_MEM_CAPS_LP BIT(3) !! 69 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */
76 #define SOF_MEM_CAPS_HP BIT(4) !! 70 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */
77 #define SOF_MEM_CAPS_DMA BIT(5) !! 71 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */
78 #define SOF_MEM_CAPS_CACHE BIT(6) !! 72 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */
79 #define SOF_MEM_CAPS_EXEC BIT(7) !! 73 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */
80 #define SOF_MEM_CAPS_L3 BIT(8) <<
81 <<
82 /* <<
83 * overrun will cause ring buffer overwrite, i <<
84 */ <<
85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) <<
86 <<
87 /* <<
88 * underrun will cause readback of 0s, instead <<
89 */ <<
90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) <<
91 <<
92 /* the UUID size in bytes, shared between FW a <<
93 #define SOF_UUID_SIZE 16 <<
94 74
95 /* create new component buffer - SOF_IPC_TPLG_ 75 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
96 struct sof_ipc_buffer { 76 struct sof_ipc_buffer {
97 struct sof_ipc_comp comp; 77 struct sof_ipc_comp comp;
98 uint32_t size; /**< buffer si 78 uint32_t size; /**< buffer size in bytes */
99 uint32_t caps; /**< SOF_MEM_C 79 uint32_t caps; /**< SOF_MEM_CAPS_ */
100 uint32_t flags; /**< SOF_BUF_ !! 80 } __packed;
101 uint32_t reserved; /**< reserved <<
102 } __packed __aligned(4); <<
103 81
104 /* generic component config data - must always 82 /* generic component config data - must always be after struct sof_ipc_comp */
105 struct sof_ipc_comp_config { 83 struct sof_ipc_comp_config {
106 struct sof_ipc_cmd_hdr hdr; 84 struct sof_ipc_cmd_hdr hdr;
107 uint32_t periods_sink; /**< 0 means v 85 uint32_t periods_sink; /**< 0 means variable */
108 uint32_t periods_source;/**< 0 means v !! 86 uint32_t periods_source; /**< 0 means variable */
109 uint32_t reserved1; /**< reserved 87 uint32_t reserved1; /**< reserved */
110 uint32_t frame_fmt; /**< SOF_IPC_F !! 88 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
111 uint32_t xrun_action; 89 uint32_t xrun_action;
112 90
113 /* reserved for future use */ 91 /* reserved for future use */
114 uint32_t reserved[2]; 92 uint32_t reserved[2];
115 } __packed __aligned(4); !! 93 } __packed;
116 94
117 /* generic host component */ 95 /* generic host component */
118 struct sof_ipc_comp_host { 96 struct sof_ipc_comp_host {
119 struct sof_ipc_comp comp; 97 struct sof_ipc_comp comp;
120 struct sof_ipc_comp_config config; 98 struct sof_ipc_comp_config config;
121 uint32_t direction; /**< SOF_IPC_S 99 uint32_t direction; /**< SOF_IPC_STREAM_ */
122 uint32_t no_irq; /**< don't sen 100 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
123 uint32_t dmac_config; /**< DMA engine 101 uint32_t dmac_config; /**< DMA engine specific */
124 } __packed __aligned(4); !! 102 } __packed;
125 103
126 /* generic DAI component */ 104 /* generic DAI component */
127 struct sof_ipc_comp_dai { 105 struct sof_ipc_comp_dai {
128 struct sof_ipc_comp comp; 106 struct sof_ipc_comp comp;
129 struct sof_ipc_comp_config config; 107 struct sof_ipc_comp_config config;
130 uint32_t direction; /**< SOF_IPC_S 108 uint32_t direction; /**< SOF_IPC_STREAM_ */
131 uint32_t dai_index; /**< index of 109 uint32_t dai_index; /**< index of this type dai */
132 uint32_t type; /**< DAI type 110 uint32_t type; /**< DAI type - SOF_DAI_ */
133 uint32_t reserved; /**< reserved 111 uint32_t reserved; /**< reserved */
134 } __packed __aligned(4); !! 112 } __packed;
135 113
136 /* generic mixer component */ 114 /* generic mixer component */
137 struct sof_ipc_comp_mixer { 115 struct sof_ipc_comp_mixer {
138 struct sof_ipc_comp comp; 116 struct sof_ipc_comp comp;
139 struct sof_ipc_comp_config config; 117 struct sof_ipc_comp_config config;
140 } __packed __aligned(4); !! 118 } __packed;
141 119
142 /* volume ramping types */ 120 /* volume ramping types */
143 enum sof_volume_ramp { 121 enum sof_volume_ramp {
144 SOF_VOLUME_LINEAR = 0, 122 SOF_VOLUME_LINEAR = 0,
145 SOF_VOLUME_LOG, 123 SOF_VOLUME_LOG,
146 SOF_VOLUME_LINEAR_ZC, 124 SOF_VOLUME_LINEAR_ZC,
147 SOF_VOLUME_LOG_ZC, 125 SOF_VOLUME_LOG_ZC,
148 SOF_VOLUME_WINDOWS_FADE, <<
149 SOF_VOLUME_WINDOWS_NO_FADE, <<
150 }; 126 };
151 127
152 /* generic volume component */ 128 /* generic volume component */
153 struct sof_ipc_comp_volume { 129 struct sof_ipc_comp_volume {
154 struct sof_ipc_comp comp; 130 struct sof_ipc_comp comp;
155 struct sof_ipc_comp_config config; 131 struct sof_ipc_comp_config config;
156 uint32_t channels; 132 uint32_t channels;
157 uint32_t min_value; 133 uint32_t min_value;
158 uint32_t max_value; 134 uint32_t max_value;
159 uint32_t ramp; /**< SOF_VOLUM 135 uint32_t ramp; /**< SOF_VOLUME_ */
160 uint32_t initial_ramp; /**< ramp spac 136 uint32_t initial_ramp; /**< ramp space in ms */
161 } __packed __aligned(4); !! 137 } __packed;
162 138
163 /* generic SRC component */ 139 /* generic SRC component */
164 struct sof_ipc_comp_src { 140 struct sof_ipc_comp_src {
165 struct sof_ipc_comp comp; 141 struct sof_ipc_comp comp;
166 struct sof_ipc_comp_config config; 142 struct sof_ipc_comp_config config;
167 /* either source or sink rate must be 143 /* either source or sink rate must be non zero */
168 uint32_t source_rate; /**< source ra 144 uint32_t source_rate; /**< source rate or 0 for variable */
169 uint32_t sink_rate; /**< sink rate 145 uint32_t sink_rate; /**< sink rate or 0 for variable */
170 uint32_t rate_mask; /**< SOF_RATE_ 146 uint32_t rate_mask; /**< SOF_RATE_ supported rates */
171 } __packed __aligned(4); !! 147 } __packed;
172 <<
173 /* generic ASRC component */ <<
174 struct sof_ipc_comp_asrc { <<
175 struct sof_ipc_comp comp; <<
176 struct sof_ipc_comp_config config; <<
177 /* either source or sink rate must be <<
178 uint32_t source_rate; /**< D <<
179 /**< u <<
180 /**< t <<
181 uint32_t sink_rate; /**< D <<
182 /**< u <<
183 /**< t <<
184 uint32_t asynchronous_mode; /**< s <<
185 /**< W <<
186 /**< c <<
187 uint32_t operation_mode; /**< p <<
188 /**< A <<
189 /**< o <<
190 /**< n <<
191 /**< I <<
192 /**< a <<
193 /**< n <<
194 <<
195 /* reserved for future use */ <<
196 uint32_t reserved[4]; <<
197 } __packed __aligned(4); <<
198 148
199 /* generic MUX component */ 149 /* generic MUX component */
200 struct sof_ipc_comp_mux { 150 struct sof_ipc_comp_mux {
201 struct sof_ipc_comp comp; 151 struct sof_ipc_comp comp;
202 struct sof_ipc_comp_config config; 152 struct sof_ipc_comp_config config;
203 } __packed __aligned(4); !! 153 } __packed;
204 154
205 /* generic tone generator component */ 155 /* generic tone generator component */
206 struct sof_ipc_comp_tone { 156 struct sof_ipc_comp_tone {
207 struct sof_ipc_comp comp; 157 struct sof_ipc_comp comp;
208 struct sof_ipc_comp_config config; 158 struct sof_ipc_comp_config config;
209 int32_t sample_rate; 159 int32_t sample_rate;
210 int32_t frequency; 160 int32_t frequency;
211 int32_t amplitude; 161 int32_t amplitude;
212 int32_t freq_mult; 162 int32_t freq_mult;
213 int32_t ampl_mult; 163 int32_t ampl_mult;
214 int32_t length; 164 int32_t length;
215 int32_t period; 165 int32_t period;
216 int32_t repeats; 166 int32_t repeats;
217 int32_t ramp_step; 167 int32_t ramp_step;
218 } __packed __aligned(4); !! 168 } __packed;
219 169
220 /** \brief Types of processing components */ 170 /** \brief Types of processing components */
221 enum sof_ipc_process_type { 171 enum sof_ipc_process_type {
222 SOF_PROCESS_NONE = 0, /**< N 172 SOF_PROCESS_NONE = 0, /**< None */
223 SOF_PROCESS_EQFIR, /**< I 173 SOF_PROCESS_EQFIR, /**< Intel FIR */
224 SOF_PROCESS_EQIIR, /**< I 174 SOF_PROCESS_EQIIR, /**< Intel IIR */
225 SOF_PROCESS_KEYWORD_DETECT, /**< K 175 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
226 SOF_PROCESS_KPB, /**< K 176 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
227 SOF_PROCESS_CHAN_SELECTOR, /**< C 177 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
228 SOF_PROCESS_MUX, <<
229 SOF_PROCESS_DEMUX, <<
230 SOF_PROCESS_DCBLOCK, <<
231 SOF_PROCESS_SMART_AMP, /**< Smart Amp <<
232 }; 178 };
233 179
234 /* generic "effect", "codec" or proprietary pr 180 /* generic "effect", "codec" or proprietary processing component */
235 struct sof_ipc_comp_process { 181 struct sof_ipc_comp_process {
236 struct sof_ipc_comp comp; 182 struct sof_ipc_comp comp;
237 struct sof_ipc_comp_config config; 183 struct sof_ipc_comp_config config;
238 uint32_t size; /**< size of bespoke d 184 uint32_t size; /**< size of bespoke data section in bytes */
239 uint32_t type; /**< sof_ipc_process_t 185 uint32_t type; /**< sof_ipc_process_type */
240 186
241 /* reserved for future use */ 187 /* reserved for future use */
242 uint32_t reserved[7]; 188 uint32_t reserved[7];
243 189
244 unsigned char data[]; !! 190 unsigned char data[0];
245 } __packed __aligned(4); !! 191 } __packed;
246 192
247 /* frees components, buffers and pipelines 193 /* frees components, buffers and pipelines
248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_F 194 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
249 */ 195 */
250 struct sof_ipc_free { 196 struct sof_ipc_free {
251 struct sof_ipc_cmd_hdr hdr; 197 struct sof_ipc_cmd_hdr hdr;
252 uint32_t id; 198 uint32_t id;
253 } __packed __aligned(4); !! 199 } __packed;
254 200
255 struct sof_ipc_comp_reply { 201 struct sof_ipc_comp_reply {
256 struct sof_ipc_reply rhdr; 202 struct sof_ipc_reply rhdr;
257 uint32_t id; 203 uint32_t id;
258 uint32_t offset; 204 uint32_t offset;
259 } __packed __aligned(4); !! 205 } __packed;
260 206
261 /* 207 /*
262 * Pipeline 208 * Pipeline
263 */ 209 */
264 210
265 /** \brief Types of pipeline scheduling time d 211 /** \brief Types of pipeline scheduling time domains */
266 enum sof_ipc_pipe_sched_time_domain { 212 enum sof_ipc_pipe_sched_time_domain {
267 SOF_TIME_DOMAIN_DMA = 0, /**< D 213 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
268 SOF_TIME_DOMAIN_TIMER, /**< T 214 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
269 }; 215 };
270 216
271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 217 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
272 struct sof_ipc_pipe_new { 218 struct sof_ipc_pipe_new {
273 struct sof_ipc_cmd_hdr hdr; 219 struct sof_ipc_cmd_hdr hdr;
274 uint32_t comp_id; /**< component 220 uint32_t comp_id; /**< component id for pipeline */
275 uint32_t pipeline_id; /**< pipeline 221 uint32_t pipeline_id; /**< pipeline id */
276 uint32_t sched_id; /**< Schedulin 222 uint32_t sched_id; /**< Scheduling component id */
277 uint32_t core; /**< core we r 223 uint32_t core; /**< core we run on */
278 uint32_t period; /**< execution 224 uint32_t period; /**< execution period in us*/
279 uint32_t priority; /**< priority 225 uint32_t priority; /**< priority level 0 (low) to 10 (max) */
280 uint32_t period_mips; /**< worst cas 226 uint32_t period_mips; /**< worst case instruction count per period */
281 uint32_t frames_per_sched;/**< output 227 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
282 uint32_t xrun_limit_usecs; /**< report 228 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
283 uint32_t time_domain; /**< schedulin 229 uint32_t time_domain; /**< scheduling time domain */
284 } __packed __aligned(4); !! 230 } __packed;
285 231
286 /* pipeline construction complete - SOF_IPC_TP 232 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
287 struct sof_ipc_pipe_ready { 233 struct sof_ipc_pipe_ready {
288 struct sof_ipc_cmd_hdr hdr; 234 struct sof_ipc_cmd_hdr hdr;
289 uint32_t comp_id; 235 uint32_t comp_id;
290 } __packed __aligned(4); !! 236 } __packed;
291 237
292 struct sof_ipc_pipe_free { 238 struct sof_ipc_pipe_free {
293 struct sof_ipc_cmd_hdr hdr; 239 struct sof_ipc_cmd_hdr hdr;
294 uint32_t comp_id; 240 uint32_t comp_id;
295 } __packed __aligned(4); !! 241 } __packed;
296 242
297 /* connect two components in pipeline - SOF_IP 243 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
298 struct sof_ipc_pipe_comp_connect { 244 struct sof_ipc_pipe_comp_connect {
299 struct sof_ipc_cmd_hdr hdr; 245 struct sof_ipc_cmd_hdr hdr;
300 uint32_t source_id; 246 uint32_t source_id;
301 uint32_t sink_id; 247 uint32_t sink_id;
302 } __packed __aligned(4); !! 248 } __packed;
303 249
304 /* external events */ 250 /* external events */
305 enum sof_event_types { 251 enum sof_event_types {
306 SOF_EVENT_NONE = 0, 252 SOF_EVENT_NONE = 0,
307 SOF_KEYWORD_DETECT_DAPM_EVENT, 253 SOF_KEYWORD_DETECT_DAPM_EVENT,
308 }; 254 };
309 255
310 #endif 256 #endif
311 257
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