1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 #ifndef _UAPI_LINUX_FB_H 2 #ifndef _UAPI_LINUX_FB_H
3 #define _UAPI_LINUX_FB_H 3 #define _UAPI_LINUX_FB_H
4 4
5 #include <linux/types.h> 5 #include <linux/types.h>
6 #include <linux/i2c.h> 6 #include <linux/i2c.h>
7 #include <linux/vesa.h> <<
8 7
9 /* Definitions of frame buffers 8 /* Definitions of frame buffers */
10 9
11 #define FB_MAX 32 /* suf 10 #define FB_MAX 32 /* sufficient for now */
12 11
13 /* ioctls 12 /* ioctls
14 0x46 is 'F' 13 0x46 is 'F' */
15 #define FBIOGET_VSCREENINFO 0x4600 14 #define FBIOGET_VSCREENINFO 0x4600
16 #define FBIOPUT_VSCREENINFO 0x4601 15 #define FBIOPUT_VSCREENINFO 0x4601
17 #define FBIOGET_FSCREENINFO 0x4602 16 #define FBIOGET_FSCREENINFO 0x4602
18 #define FBIOGETCMAP 0x4604 17 #define FBIOGETCMAP 0x4604
19 #define FBIOPUTCMAP 0x4605 18 #define FBIOPUTCMAP 0x4605
20 #define FBIOPAN_DISPLAY 0x4606 19 #define FBIOPAN_DISPLAY 0x4606
21 #ifndef __KERNEL__ 20 #ifndef __KERNEL__
22 #define FBIO_CURSOR _IOWR('F', 0x08 21 #define FBIO_CURSOR _IOWR('F', 0x08, struct fb_cursor)
23 #endif 22 #endif
24 /* 0x4607-0x460B are defined below */ 23 /* 0x4607-0x460B are defined below */
25 /* #define FBIOGET_MONITORSPEC 0x460C */ 24 /* #define FBIOGET_MONITORSPEC 0x460C */
26 /* #define FBIOPUT_MONITORSPEC 0x460D */ 25 /* #define FBIOPUT_MONITORSPEC 0x460D */
27 /* #define FBIOSWITCH_MONIBIT 0x460E */ 26 /* #define FBIOSWITCH_MONIBIT 0x460E */
28 #define FBIOGET_CON2FBMAP 0x460F 27 #define FBIOGET_CON2FBMAP 0x460F
29 #define FBIOPUT_CON2FBMAP 0x4610 28 #define FBIOPUT_CON2FBMAP 0x4610
30 #define FBIOBLANK 0x4611 29 #define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
31 #define FBIOGET_VBLANK _IOR('F', 0x12 30 #define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank)
32 #define FBIO_ALLOC 0x4613 31 #define FBIO_ALLOC 0x4613
33 #define FBIO_FREE 0x4614 32 #define FBIO_FREE 0x4614
34 #define FBIOGET_GLYPH 0x4615 33 #define FBIOGET_GLYPH 0x4615
35 #define FBIOGET_HWCINFO 0x4616 34 #define FBIOGET_HWCINFO 0x4616
36 #define FBIOPUT_MODEINFO 0x4617 35 #define FBIOPUT_MODEINFO 0x4617
37 #define FBIOGET_DISPINFO 0x4618 36 #define FBIOGET_DISPINFO 0x4618
38 #define FBIO_WAITFORVSYNC _IOW('F', 0x20 37 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
39 38
40 #define FB_TYPE_PACKED_PIXELS 0 39 #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
41 #define FB_TYPE_PLANES 1 40 #define FB_TYPE_PLANES 1 /* Non interleaved planes */
42 #define FB_TYPE_INTERLEAVED_PLANES 2 41 #define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
43 #define FB_TYPE_TEXT 3 42 #define FB_TYPE_TEXT 3 /* Text/attributes */
44 #define FB_TYPE_VGA_PLANES 4 43 #define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
45 #define FB_TYPE_FOURCC 5 44 #define FB_TYPE_FOURCC 5 /* Type identified by a V4L2 FOURCC */
46 45
47 #define FB_AUX_TEXT_MDA 0 /* Mon 46 #define FB_AUX_TEXT_MDA 0 /* Monochrome text */
48 #define FB_AUX_TEXT_CGA 1 /* CGA 47 #define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
49 #define FB_AUX_TEXT_S3_MMIO 2 /* S3 48 #define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
50 #define FB_AUX_TEXT_MGA_STEP16 3 /* MGA 49 #define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
51 #define FB_AUX_TEXT_MGA_STEP8 4 /* oth 50 #define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
52 #define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-1 51 #define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */
53 #define FB_AUX_TEXT_SVGA_MASK 7 /* low 52 #define FB_AUX_TEXT_SVGA_MASK 7 /* lower three bits says step */
54 #define FB_AUX_TEXT_SVGA_STEP2 8 /* SVG 53 #define FB_AUX_TEXT_SVGA_STEP2 8 /* SVGA text mode: text, attr */
55 #define FB_AUX_TEXT_SVGA_STEP4 9 /* SVG 54 #define FB_AUX_TEXT_SVGA_STEP4 9 /* SVGA text mode: text, attr, 2 reserved bytes */
56 #define FB_AUX_TEXT_SVGA_STEP8 10 /* SVG 55 #define FB_AUX_TEXT_SVGA_STEP8 10 /* SVGA text mode: text, attr, 6 reserved bytes */
57 #define FB_AUX_TEXT_SVGA_STEP16 11 /* SVG 56 #define FB_AUX_TEXT_SVGA_STEP16 11 /* SVGA text mode: text, attr, 14 reserved bytes */
58 #define FB_AUX_TEXT_SVGA_LAST 15 /* res 57 #define FB_AUX_TEXT_SVGA_LAST 15 /* reserved up to 15 */
59 58
60 #define FB_AUX_VGA_PLANES_VGA4 0 59 #define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
61 #define FB_AUX_VGA_PLANES_CFB4 1 60 #define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
62 #define FB_AUX_VGA_PLANES_CFB8 2 61 #define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
63 62
64 #define FB_VISUAL_MONO01 0 63 #define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
65 #define FB_VISUAL_MONO10 1 64 #define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
66 #define FB_VISUAL_TRUECOLOR 2 65 #define FB_VISUAL_TRUECOLOR 2 /* True color */
67 #define FB_VISUAL_PSEUDOCOLOR 3 66 #define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
68 #define FB_VISUAL_DIRECTCOLOR 4 67 #define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
69 #define FB_VISUAL_STATIC_PSEUDOCOLOR 5 68 #define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
70 #define FB_VISUAL_FOURCC 6 69 #define FB_VISUAL_FOURCC 6 /* Visual identified by a V4L2 FOURCC */
71 70
72 #define FB_ACCEL_NONE 0 /* no 71 #define FB_ACCEL_NONE 0 /* no hardware accelerator */
73 #define FB_ACCEL_ATARIBLITT 1 /* Ata 72 #define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
74 #define FB_ACCEL_AMIGABLITT 2 /* Ami 73 #define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
75 #define FB_ACCEL_S3_TRIO64 3 /* Cyb 74 #define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
76 #define FB_ACCEL_NCR_77C32BLT 4 /* Ret 75 #define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
77 #define FB_ACCEL_S3_VIRGE 5 /* Cyb 76 #define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
78 #define FB_ACCEL_ATI_MACH64GX 6 /* ATI 77 #define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
79 #define FB_ACCEL_DEC_TGA 7 /* DEC 78 #define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
80 #define FB_ACCEL_ATI_MACH64CT 8 /* ATI 79 #define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
81 #define FB_ACCEL_ATI_MACH64VT 9 /* ATI 80 #define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
82 #define FB_ACCEL_ATI_MACH64GT 10 /* ATI 81 #define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
83 #define FB_ACCEL_SUN_CREATOR 11 /* Sun 82 #define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
84 #define FB_ACCEL_SUN_CGSIX 12 /* Sun 83 #define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
85 #define FB_ACCEL_SUN_LEO 13 /* Sun 84 #define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
86 #define FB_ACCEL_IMS_TWINTURBO 14 /* IMS 85 #define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
87 #define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dl 86 #define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
88 #define FB_ACCEL_MATROX_MGA2064W 16 /* Mat 87 #define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
89 #define FB_ACCEL_MATROX_MGA1064SG 17 /* Mat 88 #define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
90 #define FB_ACCEL_MATROX_MGA2164W 18 /* Mat 89 #define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
91 #define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Mat 90 #define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
92 #define FB_ACCEL_MATROX_MGAG100 20 /* Mat 91 #define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
93 #define FB_ACCEL_MATROX_MGAG200 21 /* Mat 92 #define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
94 #define FB_ACCEL_SUN_CG14 22 /* Sun 93 #define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
95 #define FB_ACCEL_SUN_BWTWO 23 /* Sun 94 #define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
96 #define FB_ACCEL_SUN_CGTHREE 24 /* Sun 95 #define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
97 #define FB_ACCEL_SUN_TCX 25 /* Sun 96 #define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
98 #define FB_ACCEL_MATROX_MGAG400 26 /* Mat 97 #define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
99 #define FB_ACCEL_NV3 27 /* nVi 98 #define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
100 #define FB_ACCEL_NV4 28 /* nVi 99 #define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
101 #define FB_ACCEL_NV5 29 /* nVi 100 #define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
102 #define FB_ACCEL_CT_6555x 30 /* C&T 101 #define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
103 #define FB_ACCEL_3DFX_BANSHEE 31 /* 3Df 102 #define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
104 #define FB_ACCEL_ATI_RAGE128 32 /* ATI 103 #define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
105 #define FB_ACCEL_IGS_CYBER2000 33 /* Cyb 104 #define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
106 #define FB_ACCEL_IGS_CYBER2010 34 /* Cyb 105 #define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
107 #define FB_ACCEL_IGS_CYBER5000 35 /* Cyb 106 #define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
108 #define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 107 #define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
109 #define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dl 108 #define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
110 #define FB_ACCEL_ATI_RADEON 38 /* ATI 109 #define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
111 #define FB_ACCEL_I810 39 /* Int 110 #define FB_ACCEL_I810 39 /* Intel 810/815 */
112 #define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 111 #define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
113 #define FB_ACCEL_SIS_XABRE 41 /* SiS 112 #define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
114 #define FB_ACCEL_I830 42 /* Int 113 #define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */
115 #define FB_ACCEL_NV_10 43 /* nVi 114 #define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */
116 #define FB_ACCEL_NV_20 44 /* nVi 115 #define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */
117 #define FB_ACCEL_NV_30 45 /* nVi 116 #define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
118 #define FB_ACCEL_NV_40 46 /* nVi 117 #define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */
119 #define FB_ACCEL_XGI_VOLARI_V 47 /* XGI 118 #define FB_ACCEL_XGI_VOLARI_V 47 /* XGI Volari V3XT, V5, V8 */
120 #define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI 119 #define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI Volari Z7 */
121 #define FB_ACCEL_OMAP1610 49 /* TI 120 #define FB_ACCEL_OMAP1610 49 /* TI OMAP16xx */
122 #define FB_ACCEL_TRIDENT_TGUI 50 /* Tri 121 #define FB_ACCEL_TRIDENT_TGUI 50 /* Trident TGUI */
123 #define FB_ACCEL_TRIDENT_3DIMAGE 51 /* Tri 122 #define FB_ACCEL_TRIDENT_3DIMAGE 51 /* Trident 3DImage */
124 #define FB_ACCEL_TRIDENT_BLADE3D 52 /* Tri 123 #define FB_ACCEL_TRIDENT_BLADE3D 52 /* Trident Blade3D */
125 #define FB_ACCEL_TRIDENT_BLADEXP 53 /* Tri 124 #define FB_ACCEL_TRIDENT_BLADEXP 53 /* Trident BladeXP */
126 #define FB_ACCEL_CIRRUS_ALPINE 53 /* Cir 125 #define FB_ACCEL_CIRRUS_ALPINE 53 /* Cirrus Logic 543x/544x/5480 */
127 #define FB_ACCEL_NEOMAGIC_NM2070 90 /* Neo 126 #define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
128 #define FB_ACCEL_NEOMAGIC_NM2090 91 /* Neo 127 #define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
129 #define FB_ACCEL_NEOMAGIC_NM2093 92 /* Neo 128 #define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
130 #define FB_ACCEL_NEOMAGIC_NM2097 93 /* Neo 129 #define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
131 #define FB_ACCEL_NEOMAGIC_NM2160 94 /* Neo 130 #define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
132 #define FB_ACCEL_NEOMAGIC_NM2200 95 /* Neo 131 #define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
133 #define FB_ACCEL_NEOMAGIC_NM2230 96 /* Neo 132 #define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
134 #define FB_ACCEL_NEOMAGIC_NM2360 97 /* Neo 133 #define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
135 #define FB_ACCEL_NEOMAGIC_NM2380 98 /* Neo 134 #define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
136 #define FB_ACCEL_PXA3XX 99 /* PXA 135 #define FB_ACCEL_PXA3XX 99 /* PXA3xx */
137 136
138 #define FB_ACCEL_SAVAGE4 0x80 /* S3 137 #define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
139 #define FB_ACCEL_SAVAGE3D 0x81 /* S3 138 #define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
140 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 139 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
141 #define FB_ACCEL_SAVAGE2000 0x83 /* S3 140 #define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */
142 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 141 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
143 #define FB_ACCEL_SAVAGE_MX 0x85 /* S3 142 #define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */
144 #define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 143 #define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
145 #define FB_ACCEL_SAVAGE_IX 0x87 /* S3 144 #define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */
146 #define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 145 #define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */
147 #define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 146 #define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */
148 #define FB_ACCEL_S3TWISTER_P 0x8a /* S3 147 #define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */
149 #define FB_ACCEL_S3TWISTER_K 0x8b /* S3 148 #define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */
150 #define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 149 #define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */
151 #define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 150 #define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */
152 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 151 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
153 152
154 #define FB_ACCEL_PUV3_UNIGFX 0xa0 /* PKU 153 #define FB_ACCEL_PUV3_UNIGFX 0xa0 /* PKUnity-v3 Unigfx */
155 154
156 #define FB_CAP_FOURCC 1 /* Dev 155 #define FB_CAP_FOURCC 1 /* Device supports FOURCC-based formats */
157 156
158 struct fb_fix_screeninfo { 157 struct fb_fix_screeninfo {
159 char id[16]; /* ide 158 char id[16]; /* identification string eg "TT Builtin" */
160 unsigned long smem_start; /* Sta 159 unsigned long smem_start; /* Start of frame buffer mem */
161 /* (ph 160 /* (physical address) */
162 __u32 smem_len; /* Len 161 __u32 smem_len; /* Length of frame buffer mem */
163 __u32 type; /* see 162 __u32 type; /* see FB_TYPE_* */
164 __u32 type_aux; /* Int 163 __u32 type_aux; /* Interleave for interleaved Planes */
165 __u32 visual; /* see 164 __u32 visual; /* see FB_VISUAL_* */
166 __u16 xpanstep; /* zer 165 __u16 xpanstep; /* zero if no hardware panning */
167 __u16 ypanstep; /* zer 166 __u16 ypanstep; /* zero if no hardware panning */
168 __u16 ywrapstep; /* zer 167 __u16 ywrapstep; /* zero if no hardware ywrap */
169 __u32 line_length; /* len 168 __u32 line_length; /* length of a line in bytes */
170 unsigned long mmio_start; /* Sta 169 unsigned long mmio_start; /* Start of Memory Mapped I/O */
171 /* (ph 170 /* (physical address) */
172 __u32 mmio_len; /* Len 171 __u32 mmio_len; /* Length of Memory Mapped I/O */
173 __u32 accel; /* Ind 172 __u32 accel; /* Indicate to driver which */
174 /* sp 173 /* specific chip/card we have */
175 __u16 capabilities; /* see 174 __u16 capabilities; /* see FB_CAP_* */
176 __u16 reserved[2]; /* Res 175 __u16 reserved[2]; /* Reserved for future compatibility */
177 }; 176 };
178 177
179 /* Interpretation of offset for color fields: 178 /* Interpretation of offset for color fields: All offsets are from the right,
180 * inside a "pixel" value, which is exactly 'b 179 * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
181 * can use the offset as right argument to <<) 180 * can use the offset as right argument to <<). A pixel afterwards is a bit
182 * stream and is written to video memory as th 181 * stream and is written to video memory as that unmodified.
183 * 182 *
184 * For pseudocolor: offset and length should b 183 * For pseudocolor: offset and length should be the same for all color
185 * components. Offset specifies the position o 184 * components. Offset specifies the position of the least significant bit
186 * of the palette index in a pixel value. Leng 185 * of the palette index in a pixel value. Length indicates the number
187 * of available palette entries (i.e. # of ent 186 * of available palette entries (i.e. # of entries = 1 << length).
188 */ 187 */
189 struct fb_bitfield { 188 struct fb_bitfield {
190 __u32 offset; /* beg 189 __u32 offset; /* beginning of bitfield */
191 __u32 length; /* len 190 __u32 length; /* length of bitfield */
192 __u32 msb_right; /* != 191 __u32 msb_right; /* != 0 : Most significant bit is */
193 /* rig 192 /* right */
194 }; 193 };
195 194
196 #define FB_NONSTD_HAM 1 /* Hol 195 #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
197 #define FB_NONSTD_REV_PIX_IN_B 2 /* ord 196 #define FB_NONSTD_REV_PIX_IN_B 2 /* order of pixels in each byte is reversed */
198 197
199 #define FB_ACTIVATE_NOW 0 /* set 198 #define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
200 #define FB_ACTIVATE_NXTOPEN 1 /* act 199 #define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
201 #define FB_ACTIVATE_TEST 2 /* don 200 #define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
202 #define FB_ACTIVATE_MASK 15 201 #define FB_ACTIVATE_MASK 15
203 /* val 202 /* values */
204 #define FB_ACTIVATE_VBL 16 /* act 203 #define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
205 #define FB_CHANGE_CMAP_VBL 32 /* cha 204 #define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
206 #define FB_ACTIVATE_ALL 64 /* cha 205 #define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
207 #define FB_ACTIVATE_FORCE 128 /* for 206 #define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
208 #define FB_ACTIVATE_INV_MODE 256 /* inv 207 #define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
209 #define FB_ACTIVATE_KD_TEXT 512 /* for 208 #define FB_ACTIVATE_KD_TEXT 512 /* for KDSET vt ioctl */
210 209
211 #define FB_ACCELF_TEXT 1 /* (OB 210 #define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */
212 211
213 #define FB_SYNC_HOR_HIGH_ACT 1 /* hor 212 #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
214 #define FB_SYNC_VERT_HIGH_ACT 2 /* ver 213 #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
215 #define FB_SYNC_EXT 4 /* ext 214 #define FB_SYNC_EXT 4 /* external sync */
216 #define FB_SYNC_COMP_HIGH_ACT 8 /* com 215 #define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
217 #define FB_SYNC_BROADCAST 16 /* bro 216 #define FB_SYNC_BROADCAST 16 /* broadcast video timings */
218 /* vto 217 /* vtotal = 144d/288n/576i => PAL */
219 /* vto 218 /* vtotal = 121d/242n/484i => NTSC */
220 #define FB_SYNC_ON_GREEN 32 /* syn 219 #define FB_SYNC_ON_GREEN 32 /* sync on green */
221 220
222 #define FB_VMODE_NONINTERLACED 0 /* non 221 #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
223 #define FB_VMODE_INTERLACED 1 /* int 222 #define FB_VMODE_INTERLACED 1 /* interlaced */
224 #define FB_VMODE_DOUBLE 2 /* dou 223 #define FB_VMODE_DOUBLE 2 /* double scan */
225 #define FB_VMODE_ODD_FLD_FIRST 4 /* int 224 #define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
226 #define FB_VMODE_MASK 255 225 #define FB_VMODE_MASK 255
227 226
228 #define FB_VMODE_YWRAP 256 /* ywr 227 #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
229 #define FB_VMODE_SMOOTH_XPAN 512 /* smo 228 #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
230 #define FB_VMODE_CONUPDATE 512 /* don 229 #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
231 230
232 /* 231 /*
233 * Display rotation support 232 * Display rotation support
234 */ 233 */
235 #define FB_ROTATE_UR 0 234 #define FB_ROTATE_UR 0
236 #define FB_ROTATE_CW 1 235 #define FB_ROTATE_CW 1
237 #define FB_ROTATE_UD 2 236 #define FB_ROTATE_UD 2
238 #define FB_ROTATE_CCW 3 237 #define FB_ROTATE_CCW 3
239 238
240 #define PICOS2KHZ(a) (1000000000UL/(a)) 239 #define PICOS2KHZ(a) (1000000000UL/(a))
241 #define KHZ2PICOS(a) (1000000000UL/(a)) 240 #define KHZ2PICOS(a) (1000000000UL/(a))
242 241
243 struct fb_var_screeninfo { 242 struct fb_var_screeninfo {
244 __u32 xres; /* vis 243 __u32 xres; /* visible resolution */
245 __u32 yres; 244 __u32 yres;
246 __u32 xres_virtual; /* vir 245 __u32 xres_virtual; /* virtual resolution */
247 __u32 yres_virtual; 246 __u32 yres_virtual;
248 __u32 xoffset; /* off 247 __u32 xoffset; /* offset from virtual to visible */
249 __u32 yoffset; /* res 248 __u32 yoffset; /* resolution */
250 249
251 __u32 bits_per_pixel; /* gue 250 __u32 bits_per_pixel; /* guess what */
252 __u32 grayscale; /* 0 = 251 __u32 grayscale; /* 0 = color, 1 = grayscale, */
253 /* >1 252 /* >1 = FOURCC */
254 struct fb_bitfield red; /* bit 253 struct fb_bitfield red; /* bitfield in fb mem if true color, */
255 struct fb_bitfield green; /* els 254 struct fb_bitfield green; /* else only length is significant */
256 struct fb_bitfield blue; 255 struct fb_bitfield blue;
257 struct fb_bitfield transp; /* tra 256 struct fb_bitfield transp; /* transparency */
258 257
259 __u32 nonstd; /* != 258 __u32 nonstd; /* != 0 Non standard pixel format */
260 259
261 __u32 activate; /* see 260 __u32 activate; /* see FB_ACTIVATE_* */
262 261
263 __u32 height; /* hei 262 __u32 height; /* height of picture in mm */
264 __u32 width; /* wid 263 __u32 width; /* width of picture in mm */
265 264
266 __u32 accel_flags; /* (OB 265 __u32 accel_flags; /* (OBSOLETE) see fb_info.flags */
267 266
268 /* Timing: All values in pixclocks, ex 267 /* Timing: All values in pixclocks, except pixclock (of course) */
269 __u32 pixclock; /* pix 268 __u32 pixclock; /* pixel clock in ps (pico seconds) */
270 __u32 left_margin; /* tim 269 __u32 left_margin; /* time from sync to picture */
271 __u32 right_margin; /* tim 270 __u32 right_margin; /* time from picture to sync */
272 __u32 upper_margin; /* tim 271 __u32 upper_margin; /* time from sync to picture */
273 __u32 lower_margin; 272 __u32 lower_margin;
274 __u32 hsync_len; /* len 273 __u32 hsync_len; /* length of horizontal sync */
275 __u32 vsync_len; /* len 274 __u32 vsync_len; /* length of vertical sync */
276 __u32 sync; /* see 275 __u32 sync; /* see FB_SYNC_* */
277 __u32 vmode; /* see 276 __u32 vmode; /* see FB_VMODE_* */
278 __u32 rotate; /* ang 277 __u32 rotate; /* angle we rotate counter clockwise */
279 __u32 colorspace; /* col 278 __u32 colorspace; /* colorspace for FOURCC-based modes */
280 __u32 reserved[4]; /* Res 279 __u32 reserved[4]; /* Reserved for future compatibility */
281 }; 280 };
282 281
283 struct fb_cmap { 282 struct fb_cmap {
284 __u32 start; /* Fir 283 __u32 start; /* First entry */
285 __u32 len; /* Num 284 __u32 len; /* Number of entries */
286 __u16 *red; /* Red 285 __u16 *red; /* Red values */
287 __u16 *green; 286 __u16 *green;
288 __u16 *blue; 287 __u16 *blue;
289 __u16 *transp; /* tra 288 __u16 *transp; /* transparency, can be NULL */
290 }; 289 };
291 290
292 struct fb_con2fbmap { 291 struct fb_con2fbmap {
293 __u32 console; 292 __u32 console;
294 __u32 framebuffer; 293 __u32 framebuffer;
295 }; 294 };
>> 295
>> 296 /* VESA Blanking Levels */
>> 297 #define VESA_NO_BLANKING 0
>> 298 #define VESA_VSYNC_SUSPEND 1
>> 299 #define VESA_HSYNC_SUSPEND 2
>> 300 #define VESA_POWERDOWN 3
>> 301
296 302
297 enum { 303 enum {
298 /* screen: unblanked, hsync: on, vsyn 304 /* screen: unblanked, hsync: on, vsync: on */
299 FB_BLANK_UNBLANK = VESA_NO_BLANK 305 FB_BLANK_UNBLANK = VESA_NO_BLANKING,
300 306
301 /* screen: blanked, hsync: on, vsyn 307 /* screen: blanked, hsync: on, vsync: on */
302 FB_BLANK_NORMAL = VESA_NO_BLANK 308 FB_BLANK_NORMAL = VESA_NO_BLANKING + 1,
303 309
304 /* screen: blanked, hsync: on, vsyn 310 /* screen: blanked, hsync: on, vsync: off */
305 FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SU 311 FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
306 312
307 /* screen: blanked, hsync: off, vsyn 313 /* screen: blanked, hsync: off, vsync: on */
308 FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SU 314 FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
309 315
310 /* screen: blanked, hsync: off, vsyn 316 /* screen: blanked, hsync: off, vsync: off */
311 FB_BLANK_POWERDOWN = VESA_POWERDOW 317 FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
312 }; 318 };
313 319
314 #define FB_VBLANK_VBLANKING 0x001 /* cur 320 #define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */
315 #define FB_VBLANK_HBLANKING 0x002 /* cur 321 #define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */
316 #define FB_VBLANK_HAVE_VBLANK 0x004 /* ver 322 #define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */
317 #define FB_VBLANK_HAVE_HBLANK 0x008 /* hor 323 #define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */
318 #define FB_VBLANK_HAVE_COUNT 0x010 /* glo 324 #define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */
319 #define FB_VBLANK_HAVE_VCOUNT 0x020 /* the 325 #define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */
320 #define FB_VBLANK_HAVE_HCOUNT 0x040 /* the 326 #define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */
321 #define FB_VBLANK_VSYNCING 0x080 /* cur 327 #define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
322 #define FB_VBLANK_HAVE_VSYNC 0x100 /* ver 328 #define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
323 329
324 struct fb_vblank { 330 struct fb_vblank {
325 __u32 flags; /* FB_ 331 __u32 flags; /* FB_VBLANK flags */
326 __u32 count; /* cou 332 __u32 count; /* counter of retraces since boot */
327 __u32 vcount; /* cur 333 __u32 vcount; /* current scanline position */
328 __u32 hcount; /* cur 334 __u32 hcount; /* current scandot position */
329 __u32 reserved[4]; /* res 335 __u32 reserved[4]; /* reserved for future compatibility */
330 }; 336 };
331 337
332 /* Internal HW accel */ 338 /* Internal HW accel */
333 #define ROP_COPY 0 339 #define ROP_COPY 0
334 #define ROP_XOR 1 340 #define ROP_XOR 1
335 341
336 struct fb_copyarea { 342 struct fb_copyarea {
337 __u32 dx; 343 __u32 dx;
338 __u32 dy; 344 __u32 dy;
339 __u32 width; 345 __u32 width;
340 __u32 height; 346 __u32 height;
341 __u32 sx; 347 __u32 sx;
342 __u32 sy; 348 __u32 sy;
343 }; 349 };
344 350
345 struct fb_fillrect { 351 struct fb_fillrect {
346 __u32 dx; /* screen-relative */ 352 __u32 dx; /* screen-relative */
347 __u32 dy; 353 __u32 dy;
348 __u32 width; 354 __u32 width;
349 __u32 height; 355 __u32 height;
350 __u32 color; 356 __u32 color;
351 __u32 rop; 357 __u32 rop;
352 }; 358 };
353 359
354 struct fb_image { 360 struct fb_image {
355 __u32 dx; /* Where to pl 361 __u32 dx; /* Where to place image */
356 __u32 dy; 362 __u32 dy;
357 __u32 width; /* Size of ima 363 __u32 width; /* Size of image */
358 __u32 height; 364 __u32 height;
359 __u32 fg_color; /* Only used w 365 __u32 fg_color; /* Only used when a mono bitmap */
360 __u32 bg_color; 366 __u32 bg_color;
361 __u8 depth; /* Depth of th 367 __u8 depth; /* Depth of the image */
362 const char *data; /* Pointer to 368 const char *data; /* Pointer to image data */
363 struct fb_cmap cmap; /* color map i 369 struct fb_cmap cmap; /* color map info */
364 }; 370 };
365 371
366 /* 372 /*
367 * hardware cursor control 373 * hardware cursor control
368 */ 374 */
369 375
370 #define FB_CUR_SETIMAGE 0x01 376 #define FB_CUR_SETIMAGE 0x01
371 #define FB_CUR_SETPOS 0x02 377 #define FB_CUR_SETPOS 0x02
372 #define FB_CUR_SETHOT 0x04 378 #define FB_CUR_SETHOT 0x04
373 #define FB_CUR_SETCMAP 0x08 379 #define FB_CUR_SETCMAP 0x08
374 #define FB_CUR_SETSHAPE 0x10 380 #define FB_CUR_SETSHAPE 0x10
375 #define FB_CUR_SETSIZE 0x20 381 #define FB_CUR_SETSIZE 0x20
376 #define FB_CUR_SETALL 0xFF 382 #define FB_CUR_SETALL 0xFF
377 383
378 struct fbcurpos { 384 struct fbcurpos {
379 __u16 x, y; 385 __u16 x, y;
380 }; 386 };
381 387
382 struct fb_cursor { 388 struct fb_cursor {
383 __u16 set; /* what to set 389 __u16 set; /* what to set */
384 __u16 enable; /* cursor on/o 390 __u16 enable; /* cursor on/off */
385 __u16 rop; /* bitop opera 391 __u16 rop; /* bitop operation */
386 const char *mask; /* cursor mask 392 const char *mask; /* cursor mask bits */
387 struct fbcurpos hot; /* cursor hot 393 struct fbcurpos hot; /* cursor hot spot */
388 struct fb_image image; /* Cursor imag 394 struct fb_image image; /* Cursor image */
389 }; 395 };
390 396
391 /* Settings for the generic backlight code */ 397 /* Settings for the generic backlight code */
392 #define FB_BACKLIGHT_LEVELS 128 398 #define FB_BACKLIGHT_LEVELS 128
393 #define FB_BACKLIGHT_MAX 0xFF 399 #define FB_BACKLIGHT_MAX 0xFF
394 400
395 401
396 #endif /* _UAPI_LINUX_FB_H */ 402 #endif /* _UAPI_LINUX_FB_H */
397 403
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