1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux <<
2 /* 1 /*
3 * linux/mii.h: definitions for MII-compatible 2 * linux/mii.h: definitions for MII-compatible transceivers
4 * Originally drivers/net/sunhme.h. 3 * Originally drivers/net/sunhme.h.
5 * 4 *
6 * Copyright (C) 1996, 1999, 2001 David S. Mil 5 * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
7 */ 6 */
8 7
9 #ifndef _UAPI__LINUX_MII_H__ 8 #ifndef _UAPI__LINUX_MII_H__
10 #define _UAPI__LINUX_MII_H__ 9 #define _UAPI__LINUX_MII_H__
11 10
12 #include <linux/types.h> 11 #include <linux/types.h>
13 #include <linux/ethtool.h> 12 #include <linux/ethtool.h>
14 13
15 /* Generic MII registers. */ 14 /* Generic MII registers. */
16 #define MII_BMCR 0x00 /* Bas 15 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Bas 16 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHY 17 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHY 18 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Adv 19 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Lin 20 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Exp 21 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 100 22 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 100 23 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD 24 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
26 #define MII_MMD_DATA 0x0e /* MMD 25 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
27 #define MII_ESTATUS 0x0f /* Ext 26 #define MII_ESTATUS 0x0f /* Extended Status */
28 #define MII_DCOUNTER 0x12 /* Dis 27 #define MII_DCOUNTER 0x12 /* Disconnect counter */
29 #define MII_FCSCOUNTER 0x13 /* Fal 28 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
30 #define MII_NWAYTEST 0x14 /* N-w 29 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
31 #define MII_RERRCOUNTER 0x15 /* Rec 30 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
32 #define MII_SREVISION 0x16 /* Sil 31 #define MII_SREVISION 0x16 /* Silicon revision */
33 #define MII_RESV1 0x17 /* Res 32 #define MII_RESV1 0x17 /* Reserved... */
34 #define MII_LBRERROR 0x18 /* Lpb 33 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
35 #define MII_PHYADDR 0x19 /* PHY 34 #define MII_PHYADDR 0x19 /* PHY address */
36 #define MII_RESV2 0x1a /* Res 35 #define MII_RESV2 0x1a /* Reserved... */
37 #define MII_TPISTATUS 0x1b /* TPI 36 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
38 #define MII_NCONFIG 0x1c /* Net 37 #define MII_NCONFIG 0x1c /* Network interface config */
39 38
40 /* Basic mode control register. */ 39 /* Basic mode control register. */
41 #define BMCR_RESV 0x003f /* Unu 40 #define BMCR_RESV 0x003f /* Unused... */
42 #define BMCR_SPEED1000 0x0040 /* MSB 41 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
43 #define BMCR_CTST 0x0080 /* Col 42 #define BMCR_CTST 0x0080 /* Collision test */
44 #define BMCR_FULLDPLX 0x0100 /* Ful 43 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
45 #define BMCR_ANRESTART 0x0200 /* Aut 44 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
46 #define BMCR_ISOLATE 0x0400 /* Iso 45 #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
47 #define BMCR_PDOWN 0x0800 /* Ena 46 #define BMCR_PDOWN 0x0800 /* Enable low power state */
48 #define BMCR_ANENABLE 0x1000 /* Ena 47 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
49 #define BMCR_SPEED100 0x2000 /* Sel 48 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
50 #define BMCR_LOOPBACK 0x4000 /* TXD 49 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
51 #define BMCR_RESET 0x8000 /* Res 50 #define BMCR_RESET 0x8000 /* Reset to default state */
52 #define BMCR_SPEED10 0x0000 /* Sel <<
53 51
54 /* Basic mode status register. */ 52 /* Basic mode status register. */
55 #define BMSR_ERCAP 0x0001 /* Ext 53 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
56 #define BMSR_JCD 0x0002 /* Jab 54 #define BMSR_JCD 0x0002 /* Jabber detected */
57 #define BMSR_LSTATUS 0x0004 /* Lin 55 #define BMSR_LSTATUS 0x0004 /* Link status */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Abl 56 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
59 #define BMSR_RFAULT 0x0010 /* Rem 57 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Aut 58 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
61 #define BMSR_RESV 0x00c0 /* Unu 59 #define BMSR_RESV 0x00c0 /* Unused... */
62 #define BMSR_ESTATEN 0x0100 /* Ext 60 #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
63 #define BMSR_100HALF2 0x0200 /* Can 61 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can 62 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
65 #define BMSR_10HALF 0x0800 /* Can 63 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
66 #define BMSR_10FULL 0x1000 /* Can 64 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
67 #define BMSR_100HALF 0x2000 /* Can 65 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
68 #define BMSR_100FULL 0x4000 /* Can 66 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
69 #define BMSR_100BASE4 0x8000 /* Can 67 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
70 68
71 /* Advertisement control register. */ 69 /* Advertisement control register. */
72 #define ADVERTISE_SLCT 0x001f /* Sel 70 #define ADVERTISE_SLCT 0x001f /* Selector bits */
73 #define ADVERTISE_CSMA 0x0001 /* Onl 71 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
74 #define ADVERTISE_10HALF 0x0020 /* Try 72 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
75 #define ADVERTISE_1000XFULL 0x0020 /* Try 73 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
76 #define ADVERTISE_10FULL 0x0040 /* Try 74 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
77 #define ADVERTISE_1000XHALF 0x0040 /* Try 75 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
78 #define ADVERTISE_100HALF 0x0080 /* Try 76 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
79 #define ADVERTISE_1000XPAUSE 0x0080 /* Try 77 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
80 #define ADVERTISE_100FULL 0x0100 /* Try 78 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
81 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try 79 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
82 #define ADVERTISE_100BASE4 0x0200 /* Try 80 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
83 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try 81 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
84 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try 82 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
85 #define ADVERTISE_RESV 0x1000 /* Unu 83 #define ADVERTISE_RESV 0x1000 /* Unused... */
86 #define ADVERTISE_RFAULT 0x2000 /* Say 84 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
87 #define ADVERTISE_LPACK 0x4000 /* Ack 85 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
88 #define ADVERTISE_NPAGE 0x8000 /* Nex 86 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
89 87
90 #define ADVERTISE_FULL (ADVERTISE_100 88 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
91 ADVERTISE_CS 89 ADVERTISE_CSMA)
92 #define ADVERTISE_ALL (ADVERTISE_10H 90 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
93 ADVERTISE_10 91 ADVERTISE_100HALF | ADVERTISE_100FULL)
94 92
95 /* Link partner ability register. */ 93 /* Link partner ability register. */
96 #define LPA_SLCT 0x001f /* Sam 94 #define LPA_SLCT 0x001f /* Same as advertise selector */
97 #define LPA_10HALF 0x0020 /* Can 95 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
98 #define LPA_1000XFULL 0x0020 /* Can 96 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
99 #define LPA_10FULL 0x0040 /* Can 97 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
100 #define LPA_1000XHALF 0x0040 /* Can 98 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
101 #define LPA_100HALF 0x0080 /* Can 99 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
102 #define LPA_1000XPAUSE 0x0080 /* Can 100 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
103 #define LPA_100FULL 0x0100 /* Can 101 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
104 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can 102 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
105 #define LPA_100BASE4 0x0200 /* Can 103 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
106 #define LPA_PAUSE_CAP 0x0400 /* Can 104 #define LPA_PAUSE_CAP 0x0400 /* Can pause */
107 #define LPA_PAUSE_ASYM 0x0800 /* Can 105 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
108 #define LPA_RESV 0x1000 /* Unu 106 #define LPA_RESV 0x1000 /* Unused... */
109 #define LPA_RFAULT 0x2000 /* Lin 107 #define LPA_RFAULT 0x2000 /* Link partner faulted */
110 #define LPA_LPACK 0x4000 /* Lin 108 #define LPA_LPACK 0x4000 /* Link partner acked us */
111 #define LPA_NPAGE 0x8000 /* Nex 109 #define LPA_NPAGE 0x8000 /* Next page bit */
112 110
113 #define LPA_DUPLEX (LPA_10FULL | 111 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
114 #define LPA_100 (LPA_100FULL | 112 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
115 113
116 /* Expansion register for auto-negotiation. */ 114 /* Expansion register for auto-negotiation. */
117 #define EXPANSION_NWAY 0x0001 /* Can 115 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
118 #define EXPANSION_LCWP 0x0002 /* Got 116 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
119 #define EXPANSION_ENABLENPAGE 0x0004 /* Thi 117 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
120 #define EXPANSION_NPCAPABLE 0x0008 /* Lin 118 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
121 #define EXPANSION_MFAULTS 0x0010 /* Mul 119 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
122 #define EXPANSION_RESV 0xffe0 /* Unu 120 #define EXPANSION_RESV 0xffe0 /* Unused... */
123 121
124 #define ESTATUS_1000_XFULL 0x8000 /* Can <<
125 #define ESTATUS_1000_XHALF 0x4000 /* Can <<
126 #define ESTATUS_1000_TFULL 0x2000 /* Can 122 #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
127 #define ESTATUS_1000_THALF 0x1000 /* Can 123 #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
128 124
129 /* N-way test register. */ 125 /* N-way test register. */
130 #define NWAYTEST_RESV1 0x00ff /* Unu 126 #define NWAYTEST_RESV1 0x00ff /* Unused... */
131 #define NWAYTEST_LOOPBACK 0x0100 /* Ena 127 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
132 #define NWAYTEST_RESV2 0xfe00 /* Unu 128 #define NWAYTEST_RESV2 0xfe00 /* Unused... */
133 129
134 /* MAC and PHY tx_config_Reg[15:0] for SGMII i <<
135 #define ADVERTISE_SGMII 0x0001 /* MAC <<
136 #define LPA_SGMII 0x0001 /* PHY <<
137 #define LPA_SGMII_SPD_MASK 0x0c00 /* SGM <<
138 #define LPA_SGMII_FULL_DUPLEX 0x1000 /* SGM <<
139 #define LPA_SGMII_DPX_SPD_MASK 0x1C00 /* SGM <<
140 #define LPA_SGMII_10 0x0000 /* 10M <<
141 #define LPA_SGMII_10HALF 0x0000 /* Can <<
142 #define LPA_SGMII_10FULL 0x1000 /* Can <<
143 #define LPA_SGMII_100 0x0400 /* 100 <<
144 #define LPA_SGMII_100HALF 0x0400 /* Can <<
145 #define LPA_SGMII_100FULL 0x1400 /* Can <<
146 #define LPA_SGMII_1000 0x0800 /* 100 <<
147 #define LPA_SGMII_1000HALF 0x0800 /* Can <<
148 #define LPA_SGMII_1000FULL 0x1800 /* Can <<
149 #define LPA_SGMII_LINK 0x8000 /* PHY <<
150 <<
151 /* 1000BASE-T Control register */ 130 /* 1000BASE-T Control register */
152 #define ADVERTISE_1000FULL 0x0200 /* Adv 131 #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
153 #define ADVERTISE_1000HALF 0x0100 /* Adv 132 #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
154 #define CTL1000_PREFER_MASTER 0x0400 /* pre <<
155 #define CTL1000_AS_MASTER 0x0800 133 #define CTL1000_AS_MASTER 0x0800
156 #define CTL1000_ENABLE_MASTER 0x1000 134 #define CTL1000_ENABLE_MASTER 0x1000
157 135
158 /* 1000BASE-T Status register */ 136 /* 1000BASE-T Status register */
159 #define LPA_1000MSFAIL 0x8000 /* Mas <<
160 #define LPA_1000MSRES 0x4000 /* Mas <<
161 #define LPA_1000LOCALRXOK 0x2000 /* Lin 137 #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
162 #define LPA_1000REMRXOK 0x1000 /* Lin 138 #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
163 #define LPA_1000FULL 0x0800 /* Lin 139 #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
164 #define LPA_1000HALF 0x0400 /* Lin 140 #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
165 141
166 /* Flow control flags */ 142 /* Flow control flags */
167 #define FLOW_CTRL_TX 0x01 143 #define FLOW_CTRL_TX 0x01
168 #define FLOW_CTRL_RX 0x02 144 #define FLOW_CTRL_RX 0x02
169 145
170 /* MMD Access Control register fields */ 146 /* MMD Access Control register fields */
171 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mas 147 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
172 #define MII_MMD_CTRL_ADDR 0x0000 /* Add 148 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */
173 #define MII_MMD_CTRL_NOINCR 0x4000 /* no 149 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
174 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* pos 150 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
175 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* pos 151 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
176 152
177 /* This structure is used in all SIOCxMIIxxx i 153 /* This structure is used in all SIOCxMIIxxx ioctl calls */
178 struct mii_ioctl_data { 154 struct mii_ioctl_data {
179 __u16 phy_id; 155 __u16 phy_id;
180 __u16 reg_num; 156 __u16 reg_num;
181 __u16 val_in; 157 __u16 val_in;
182 __u16 val_out; 158 __u16 val_out;
183 }; 159 };
184 160
185 #endif /* _UAPI__LINUX_MII_H__ */ 161 #endif /* _UAPI__LINUX_MII_H__ */
186 162
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