1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux 1
2 /*
3 * linux/mii.h: definitions for MII-compatible
4 * Originally drivers/net/sunhme.h.
5 *
6 * Copyright (C) 1996, 1999, 2001 David S. Mil
7 */
8
9 #ifndef _UAPI__LINUX_MII_H__
10 #define _UAPI__LINUX_MII_H__
11
12 #include <linux/types.h>
13 #include <linux/ethtool.h>
14
15 /* Generic MII registers. */
16 #define MII_BMCR 0x00 /* Bas
17 #define MII_BMSR 0x01 /* Bas
18 #define MII_PHYSID1 0x02 /* PHY
19 #define MII_PHYSID2 0x03 /* PHY
20 #define MII_ADVERTISE 0x04 /* Adv
21 #define MII_LPA 0x05 /* Lin
22 #define MII_EXPANSION 0x06 /* Exp
23 #define MII_CTRL1000 0x09 /* 100
24 #define MII_STAT1000 0x0a /* 100
25 #define MII_MMD_CTRL 0x0d /* MMD
26 #define MII_MMD_DATA 0x0e /* MMD
27 #define MII_ESTATUS 0x0f /* Ext
28 #define MII_DCOUNTER 0x12 /* Dis
29 #define MII_FCSCOUNTER 0x13 /* Fal
30 #define MII_NWAYTEST 0x14 /* N-w
31 #define MII_RERRCOUNTER 0x15 /* Rec
32 #define MII_SREVISION 0x16 /* Sil
33 #define MII_RESV1 0x17 /* Res
34 #define MII_LBRERROR 0x18 /* Lpb
35 #define MII_PHYADDR 0x19 /* PHY
36 #define MII_RESV2 0x1a /* Res
37 #define MII_TPISTATUS 0x1b /* TPI
38 #define MII_NCONFIG 0x1c /* Net
39
40 /* Basic mode control register. */
41 #define BMCR_RESV 0x003f /* Unu
42 #define BMCR_SPEED1000 0x0040 /* MSB
43 #define BMCR_CTST 0x0080 /* Col
44 #define BMCR_FULLDPLX 0x0100 /* Ful
45 #define BMCR_ANRESTART 0x0200 /* Aut
46 #define BMCR_ISOLATE 0x0400 /* Iso
47 #define BMCR_PDOWN 0x0800 /* Ena
48 #define BMCR_ANENABLE 0x1000 /* Ena
49 #define BMCR_SPEED100 0x2000 /* Sel
50 #define BMCR_LOOPBACK 0x4000 /* TXD
51 #define BMCR_RESET 0x8000 /* Res
52 #define BMCR_SPEED10 0x0000 /* Sel
53
54 /* Basic mode status register. */
55 #define BMSR_ERCAP 0x0001 /* Ext
56 #define BMSR_JCD 0x0002 /* Jab
57 #define BMSR_LSTATUS 0x0004 /* Lin
58 #define BMSR_ANEGCAPABLE 0x0008 /* Abl
59 #define BMSR_RFAULT 0x0010 /* Rem
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Aut
61 #define BMSR_RESV 0x00c0 /* Unu
62 #define BMSR_ESTATEN 0x0100 /* Ext
63 #define BMSR_100HALF2 0x0200 /* Can
64 #define BMSR_100FULL2 0x0400 /* Can
65 #define BMSR_10HALF 0x0800 /* Can
66 #define BMSR_10FULL 0x1000 /* Can
67 #define BMSR_100HALF 0x2000 /* Can
68 #define BMSR_100FULL 0x4000 /* Can
69 #define BMSR_100BASE4 0x8000 /* Can
70
71 /* Advertisement control register. */
72 #define ADVERTISE_SLCT 0x001f /* Sel
73 #define ADVERTISE_CSMA 0x0001 /* Onl
74 #define ADVERTISE_10HALF 0x0020 /* Try
75 #define ADVERTISE_1000XFULL 0x0020 /* Try
76 #define ADVERTISE_10FULL 0x0040 /* Try
77 #define ADVERTISE_1000XHALF 0x0040 /* Try
78 #define ADVERTISE_100HALF 0x0080 /* Try
79 #define ADVERTISE_1000XPAUSE 0x0080 /* Try
80 #define ADVERTISE_100FULL 0x0100 /* Try
81 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try
82 #define ADVERTISE_100BASE4 0x0200 /* Try
83 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try
84 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try
85 #define ADVERTISE_RESV 0x1000 /* Unu
86 #define ADVERTISE_RFAULT 0x2000 /* Say
87 #define ADVERTISE_LPACK 0x4000 /* Ack
88 #define ADVERTISE_NPAGE 0x8000 /* Nex
89
90 #define ADVERTISE_FULL (ADVERTISE_100
91 ADVERTISE_CS
92 #define ADVERTISE_ALL (ADVERTISE_10H
93 ADVERTISE_10
94
95 /* Link partner ability register. */
96 #define LPA_SLCT 0x001f /* Sam
97 #define LPA_10HALF 0x0020 /* Can
98 #define LPA_1000XFULL 0x0020 /* Can
99 #define LPA_10FULL 0x0040 /* Can
100 #define LPA_1000XHALF 0x0040 /* Can
101 #define LPA_100HALF 0x0080 /* Can
102 #define LPA_1000XPAUSE 0x0080 /* Can
103 #define LPA_100FULL 0x0100 /* Can
104 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can
105 #define LPA_100BASE4 0x0200 /* Can
106 #define LPA_PAUSE_CAP 0x0400 /* Can
107 #define LPA_PAUSE_ASYM 0x0800 /* Can
108 #define LPA_RESV 0x1000 /* Unu
109 #define LPA_RFAULT 0x2000 /* Lin
110 #define LPA_LPACK 0x4000 /* Lin
111 #define LPA_NPAGE 0x8000 /* Nex
112
113 #define LPA_DUPLEX (LPA_10FULL |
114 #define LPA_100 (LPA_100FULL |
115
116 /* Expansion register for auto-negotiation. */
117 #define EXPANSION_NWAY 0x0001 /* Can
118 #define EXPANSION_LCWP 0x0002 /* Got
119 #define EXPANSION_ENABLENPAGE 0x0004 /* Thi
120 #define EXPANSION_NPCAPABLE 0x0008 /* Lin
121 #define EXPANSION_MFAULTS 0x0010 /* Mul
122 #define EXPANSION_RESV 0xffe0 /* Unu
123
124 #define ESTATUS_1000_XFULL 0x8000 /* Can
125 #define ESTATUS_1000_XHALF 0x4000 /* Can
126 #define ESTATUS_1000_TFULL 0x2000 /* Can
127 #define ESTATUS_1000_THALF 0x1000 /* Can
128
129 /* N-way test register. */
130 #define NWAYTEST_RESV1 0x00ff /* Unu
131 #define NWAYTEST_LOOPBACK 0x0100 /* Ena
132 #define NWAYTEST_RESV2 0xfe00 /* Unu
133
134 /* MAC and PHY tx_config_Reg[15:0] for SGMII i
135 #define ADVERTISE_SGMII 0x0001 /* MAC
136 #define LPA_SGMII 0x0001 /* PHY
137 #define LPA_SGMII_SPD_MASK 0x0c00 /* SGM
138 #define LPA_SGMII_FULL_DUPLEX 0x1000 /* SGM
139 #define LPA_SGMII_DPX_SPD_MASK 0x1C00 /* SGM
140 #define LPA_SGMII_10 0x0000 /* 10M
141 #define LPA_SGMII_10HALF 0x0000 /* Can
142 #define LPA_SGMII_10FULL 0x1000 /* Can
143 #define LPA_SGMII_100 0x0400 /* 100
144 #define LPA_SGMII_100HALF 0x0400 /* Can
145 #define LPA_SGMII_100FULL 0x1400 /* Can
146 #define LPA_SGMII_1000 0x0800 /* 100
147 #define LPA_SGMII_1000HALF 0x0800 /* Can
148 #define LPA_SGMII_1000FULL 0x1800 /* Can
149 #define LPA_SGMII_LINK 0x8000 /* PHY
150
151 /* 1000BASE-T Control register */
152 #define ADVERTISE_1000FULL 0x0200 /* Adv
153 #define ADVERTISE_1000HALF 0x0100 /* Adv
154 #define CTL1000_PREFER_MASTER 0x0400 /* pre
155 #define CTL1000_AS_MASTER 0x0800
156 #define CTL1000_ENABLE_MASTER 0x1000
157
158 /* 1000BASE-T Status register */
159 #define LPA_1000MSFAIL 0x8000 /* Mas
160 #define LPA_1000MSRES 0x4000 /* Mas
161 #define LPA_1000LOCALRXOK 0x2000 /* Lin
162 #define LPA_1000REMRXOK 0x1000 /* Lin
163 #define LPA_1000FULL 0x0800 /* Lin
164 #define LPA_1000HALF 0x0400 /* Lin
165
166 /* Flow control flags */
167 #define FLOW_CTRL_TX 0x01
168 #define FLOW_CTRL_RX 0x02
169
170 /* MMD Access Control register fields */
171 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mas
172 #define MII_MMD_CTRL_ADDR 0x0000 /* Add
173 #define MII_MMD_CTRL_NOINCR 0x4000 /* no
174 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* pos
175 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* pos
176
177 /* This structure is used in all SIOCxMIIxxx i
178 struct mii_ioctl_data {
179 __u16 phy_id;
180 __u16 reg_num;
181 __u16 val_in;
182 __u16 val_out;
183 };
184
185 #endif /* _UAPI__LINUX_MII_H__ */
186
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