1 /* 1 /*
2 * Virtio platform device driver 2 * Virtio platform device driver
3 * 3 *
4 * Copyright 2011, ARM Ltd. 4 * Copyright 2011, ARM Ltd.
5 * 5 *
6 * Based on Virtio PCI driver by Anthony Liguo 6 * Based on Virtio PCI driver by Anthony Liguori, copyright IBM Corp. 2007
7 * 7 *
8 * This header is BSD licensed so anyone can u 8 * This header is BSD licensed so anyone can use the definitions to implement
9 * compatible drivers/servers. 9 * compatible drivers/servers.
10 * 10 *
11 * Redistribution and use in source and binary 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that t 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must reta 14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the 15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must repr 16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the 17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials pro 18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of IBM nor the names of 19 * 3. Neither the name of IBM nor the names of its contributors
20 * may be used to endorse or promote produc 20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permissio 21 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDIN 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND F 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR C 25 * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECI 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILI 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF AD 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE. 32 * SUCH DAMAGE.
33 */ 33 */
34 34
35 #ifndef _LINUX_VIRTIO_MMIO_H 35 #ifndef _LINUX_VIRTIO_MMIO_H
36 #define _LINUX_VIRTIO_MMIO_H 36 #define _LINUX_VIRTIO_MMIO_H
37 37
38 /* 38 /*
39 * Control registers 39 * Control registers
40 */ 40 */
41 41
42 /* Magic value ("virt" string) - Read Only */ 42 /* Magic value ("virt" string) - Read Only */
43 #define VIRTIO_MMIO_MAGIC_VALUE 0x000 43 #define VIRTIO_MMIO_MAGIC_VALUE 0x000
44 44
45 /* Virtio device version - Read Only */ 45 /* Virtio device version - Read Only */
46 #define VIRTIO_MMIO_VERSION 0x004 46 #define VIRTIO_MMIO_VERSION 0x004
47 47
48 /* Virtio device ID - Read Only */ 48 /* Virtio device ID - Read Only */
49 #define VIRTIO_MMIO_DEVICE_ID 0x008 49 #define VIRTIO_MMIO_DEVICE_ID 0x008
50 50
51 /* Virtio vendor ID - Read Only */ 51 /* Virtio vendor ID - Read Only */
52 #define VIRTIO_MMIO_VENDOR_ID 0x00c 52 #define VIRTIO_MMIO_VENDOR_ID 0x00c
53 53
54 /* Bitmask of the features supported by the de 54 /* Bitmask of the features supported by the device (host)
55 * (32 bits per set) - Read Only */ 55 * (32 bits per set) - Read Only */
56 #define VIRTIO_MMIO_DEVICE_FEATURES 0x010 56 #define VIRTIO_MMIO_DEVICE_FEATURES 0x010
57 57
58 /* Device (host) features set selector - Write 58 /* Device (host) features set selector - Write Only */
59 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014 59 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
60 60
61 /* Bitmask of features activated by the driver 61 /* Bitmask of features activated by the driver (guest)
62 * (32 bits per set) - Write Only */ 62 * (32 bits per set) - Write Only */
63 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020 63 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020
64 64
65 /* Activated features set selector - Write Onl 65 /* Activated features set selector - Write Only */
66 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024 66 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
67 67
68 68
69 #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICE 69 #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
70 70
71 /* Guest's memory page size in bytes - Write O 71 /* Guest's memory page size in bytes - Write Only */
72 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 72 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028
73 73
74 #endif 74 #endif
75 75
76 76
77 /* Queue selector - Write Only */ 77 /* Queue selector - Write Only */
78 #define VIRTIO_MMIO_QUEUE_SEL 0x030 78 #define VIRTIO_MMIO_QUEUE_SEL 0x030
79 79
80 /* Maximum size of the currently selected queu 80 /* Maximum size of the currently selected queue - Read Only */
81 #define VIRTIO_MMIO_QUEUE_NUM_MAX 0x034 81 #define VIRTIO_MMIO_QUEUE_NUM_MAX 0x034
82 82
83 /* Queue size for the currently selected queue 83 /* Queue size for the currently selected queue - Write Only */
84 #define VIRTIO_MMIO_QUEUE_NUM 0x038 84 #define VIRTIO_MMIO_QUEUE_NUM 0x038
85 85
86 86
87 #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICE 87 #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
88 88
89 /* Used Ring alignment for the currently selec 89 /* Used Ring alignment for the currently selected queue - Write Only */
90 #define VIRTIO_MMIO_QUEUE_ALIGN 0x03c 90 #define VIRTIO_MMIO_QUEUE_ALIGN 0x03c
91 91
92 /* Guest's PFN for the currently selected queu 92 /* Guest's PFN for the currently selected queue - Read Write */
93 #define VIRTIO_MMIO_QUEUE_PFN 0x040 93 #define VIRTIO_MMIO_QUEUE_PFN 0x040
94 94
95 #endif 95 #endif
96 96
97 97
98 /* Ready bit for the currently selected queue 98 /* Ready bit for the currently selected queue - Read Write */
99 #define VIRTIO_MMIO_QUEUE_READY 0x044 99 #define VIRTIO_MMIO_QUEUE_READY 0x044
100 100
101 /* Queue notifier - Write Only */ 101 /* Queue notifier - Write Only */
102 #define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 102 #define VIRTIO_MMIO_QUEUE_NOTIFY 0x050
103 103
104 /* Interrupt status - Read Only */ 104 /* Interrupt status - Read Only */
105 #define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 105 #define VIRTIO_MMIO_INTERRUPT_STATUS 0x060
106 106
107 /* Interrupt acknowledge - Write Only */ 107 /* Interrupt acknowledge - Write Only */
108 #define VIRTIO_MMIO_INTERRUPT_ACK 0x064 108 #define VIRTIO_MMIO_INTERRUPT_ACK 0x064
109 109
110 /* Device status register - Read Write */ 110 /* Device status register - Read Write */
111 #define VIRTIO_MMIO_STATUS 0x070 111 #define VIRTIO_MMIO_STATUS 0x070
112 112
113 /* Selected queue's Descriptor Table address, 113 /* Selected queue's Descriptor Table address, 64 bits in two halves */
114 #define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 114 #define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080
115 #define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084 115 #define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084
116 116
117 /* Selected queue's Available Ring address, 64 117 /* Selected queue's Available Ring address, 64 bits in two halves */
118 #define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090 118 #define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090
119 #define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094 119 #define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094
120 120
121 /* Selected queue's Used Ring address, 64 bits 121 /* Selected queue's Used Ring address, 64 bits in two halves */
122 #define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0 122 #define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0
123 #define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4 123 #define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4
124 124
125 /* Shared memory region id */ 125 /* Shared memory region id */
126 #define VIRTIO_MMIO_SHM_SEL 0x0ac 126 #define VIRTIO_MMIO_SHM_SEL 0x0ac
127 127
128 /* Shared memory region length, 64 bits in two 128 /* Shared memory region length, 64 bits in two halves */
129 #define VIRTIO_MMIO_SHM_LEN_LOW 0x0b0 129 #define VIRTIO_MMIO_SHM_LEN_LOW 0x0b0
130 #define VIRTIO_MMIO_SHM_LEN_HIGH 0x0b4 130 #define VIRTIO_MMIO_SHM_LEN_HIGH 0x0b4
131 131
132 /* Shared memory region base address, 64 bits 132 /* Shared memory region base address, 64 bits in two halves */
133 #define VIRTIO_MMIO_SHM_BASE_LOW 0x0b8 133 #define VIRTIO_MMIO_SHM_BASE_LOW 0x0b8
134 #define VIRTIO_MMIO_SHM_BASE_HIGH 0x0bc 134 #define VIRTIO_MMIO_SHM_BASE_HIGH 0x0bc
135 135
136 /* Configuration atomicity value */ 136 /* Configuration atomicity value */
137 #define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc 137 #define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc
138 138
139 /* The config space is defined by each driver 139 /* The config space is defined by each driver as
140 * the per-driver configuration space - Read W 140 * the per-driver configuration space - Read Write */
141 #define VIRTIO_MMIO_CONFIG 0x100 141 #define VIRTIO_MMIO_CONFIG 0x100
142 142
143 143
144 144
145 /* 145 /*
146 * Interrupt flags (re: interrupt status & ack 146 * Interrupt flags (re: interrupt status & acknowledge registers)
147 */ 147 */
148 148
149 #define VIRTIO_MMIO_INT_VRING (1 << 149 #define VIRTIO_MMIO_INT_VRING (1 << 0)
150 #define VIRTIO_MMIO_INT_CONFIG (1 << 150 #define VIRTIO_MMIO_INT_CONFIG (1 << 1)
151 151
152 #endif 152 #endif
153 153
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