1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Lin 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* 2 /*
3 * 3 *
4 * This file is provided under a dual BSD/GPLv 4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so und 5 * redistributing this file, you may do so under either license.
6 * 6 *
7 * GPL LICENSE SUMMARY 7 * GPL LICENSE SUMMARY
8 * 8 *
9 * Copyright(c) 2015 - 2020 Intel Corporation. !! 9 * Copyright(c) 2015 - 2018 Intel Corporation.
10 * 10 *
11 * This program is free software; you can redi 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU 12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 * 14 *
15 * This program is distributed in the hope tha 15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the impl 16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details. 18 * General Public License for more details.
19 * 19 *
20 * BSD LICENSE 20 * BSD LICENSE
21 * 21 *
22 * Copyright(c) 2015 Intel Corporation. 22 * Copyright(c) 2015 Intel Corporation.
23 * 23 *
24 * Redistribution and use in source and binary 24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that t 25 * modification, are permitted provided that the following conditions
26 * are met: 26 * are met:
27 * 27 *
28 * - Redistributions of source code must reta 28 * - Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the 29 * notice, this list of conditions and the following disclaimer.
30 * - Redistributions in binary form must repr 30 * - Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the 31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials 32 * the documentation and/or other materials provided with the
33 * distribution. 33 * distribution.
34 * - Neither the name of Intel Corporation no 34 * - Neither the name of Intel Corporation nor the names of its
35 * contributors may be used to endorse or p 35 * contributors may be used to endorse or promote products derived
36 * from this software without specific prio 36 * from this software without specific prior written permission.
37 * 37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTI 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCH 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIR 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGE 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, S 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE PO 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 * 49 *
50 */ 50 */
51 51
52 /* 52 /*
53 * This file contains defines, structures, etc 53 * This file contains defines, structures, etc. that are used
54 * to communicate between kernel and user code 54 * to communicate between kernel and user code.
55 */ 55 */
56 56
57 #ifndef _LINUX__HFI1_USER_H 57 #ifndef _LINUX__HFI1_USER_H
58 #define _LINUX__HFI1_USER_H 58 #define _LINUX__HFI1_USER_H
59 59
60 #include <linux/types.h> 60 #include <linux/types.h>
61 #include <rdma/rdma_user_ioctl.h> 61 #include <rdma/rdma_user_ioctl.h>
62 62
63 /* 63 /*
64 * This version number is given to the driver 64 * This version number is given to the driver by the user code during
65 * initialization in the spu_userversion field 65 * initialization in the spu_userversion field of hfi1_user_info, so
66 * the driver can check for compatibility with 66 * the driver can check for compatibility with user code.
67 * 67 *
68 * The major version changes when data structu 68 * The major version changes when data structures change in an incompatible
69 * way. The driver must be the same for initia 69 * way. The driver must be the same for initialization to succeed.
70 */ 70 */
71 #define HFI1_USER_SWMAJOR 6 71 #define HFI1_USER_SWMAJOR 6
72 72
73 /* 73 /*
74 * Minor version differences are always compat 74 * Minor version differences are always compatible
75 * a within a major version, however if user s 75 * a within a major version, however if user software is larger
76 * than driver software, some new features and 76 * than driver software, some new features and/or structure fields
77 * may not be implemented; the user code must 77 * may not be implemented; the user code must deal with this if it
78 * cares, or it must abort after initializatio 78 * cares, or it must abort after initialization reports the difference.
79 */ 79 */
80 #define HFI1_USER_SWMINOR 3 80 #define HFI1_USER_SWMINOR 3
81 81
82 /* 82 /*
83 * We will encode the major/minor inside a sin 83 * We will encode the major/minor inside a single 32bit version number.
84 */ 84 */
85 #define HFI1_SWMAJOR_SHIFT 16 85 #define HFI1_SWMAJOR_SHIFT 16
86 86
87 /* 87 /*
88 * Set of HW and driver capability/feature bit 88 * Set of HW and driver capability/feature bits.
89 * These bit values are used to configure enab 89 * These bit values are used to configure enabled/disabled HW and
90 * driver features. The same set of bits are c 90 * driver features. The same set of bits are communicated to user
91 * space. 91 * space.
92 */ 92 */
93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) 93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
94 #define HFI1_CAP_SDMA (1UL << 1) 94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
95 #define HFI1_CAP_SDMA_AHG (1UL << 2) 95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) 96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
97 #define HFI1_CAP_HDRSUPP (1UL << 4) 97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
98 #define HFI1_CAP_TID_RDMA (1UL << 5) 98 #define HFI1_CAP_TID_RDMA (1UL << 5) /* Enable TID RDMA operations */
99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) 99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) 100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) 101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
102 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) 102 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */
103 #define HFI1_CAP_TID_UNMAP (1UL << 10) 103 #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */
104 #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) 104 #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */
105 #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) 105 #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */
106 #define HFI1_CAP_NO_INTEGRITY (1UL << 13) 106 #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */
107 #define HFI1_CAP_PKEY_CHECK (1UL << 14) 107 #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */
108 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) 108 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
109 #define HFI1_CAP_OPFN (1UL << 16) 109 #define HFI1_CAP_OPFN (1UL << 16) /* Enable the OPFN protocol */
110 #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) 110 #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */
111 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 1 111 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
112 #define HFI1_CAP_AIP (1UL << 19) <<
113 112
114 #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 113 #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0)
115 #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 114 #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1)
116 #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 115 #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2)
117 116
118 #define _HFI1_EVENT_FROZEN_BIT 0 117 #define _HFI1_EVENT_FROZEN_BIT 0
119 #define _HFI1_EVENT_LINKDOWN_BIT 1 118 #define _HFI1_EVENT_LINKDOWN_BIT 1
120 #define _HFI1_EVENT_LID_CHANGE_BIT 2 119 #define _HFI1_EVENT_LID_CHANGE_BIT 2
121 #define _HFI1_EVENT_LMC_CHANGE_BIT 3 120 #define _HFI1_EVENT_LMC_CHANGE_BIT 3
122 #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 121 #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4
123 #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5 122 #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5
124 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MM 123 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT
125 124
126 #define HFI1_EVENT_FROZEN (1UL << _ 125 #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
127 #define HFI1_EVENT_LINKDOWN (1UL << _ 126 #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT)
128 #define HFI1_EVENT_LID_CHANGE (1UL << _ 127 #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
129 #define HFI1_EVENT_LMC_CHANGE (1UL << _ 128 #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
130 #define HFI1_EVENT_SL2VL_CHANGE (1UL << _ 129 #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
131 #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _ 130 #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT)
132 131
133 /* 132 /*
134 * These are the status bits readable (in ASCI 133 * These are the status bits readable (in ASCII form, 64bit value)
135 * from the "status" sysfs file. For binary c 134 * from the "status" sysfs file. For binary compatibility, values
136 * must remain as is; removed states can be re 135 * must remain as is; removed states can be reused for different
137 * purposes. 136 * purposes.
138 */ 137 */
139 #define HFI1_STATUS_INITTED 0x1 /* ba 138 #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */
140 /* Chip has been found and initialized */ 139 /* Chip has been found and initialized */
141 #define HFI1_STATUS_CHIP_PRESENT 0x20 140 #define HFI1_STATUS_CHIP_PRESENT 0x20
142 /* IB link is at ACTIVE, usable for data traff 141 /* IB link is at ACTIVE, usable for data traffic */
143 #define HFI1_STATUS_IB_READY 0x40 142 #define HFI1_STATUS_IB_READY 0x40
144 /* link is configured, LID, MTU, etc. have bee 143 /* link is configured, LID, MTU, etc. have been set */
145 #define HFI1_STATUS_IB_CONF 0x80 144 #define HFI1_STATUS_IB_CONF 0x80
146 /* A Fatal hardware error has occurred. */ 145 /* A Fatal hardware error has occurred. */
147 #define HFI1_STATUS_HWERROR 0x200 146 #define HFI1_STATUS_HWERROR 0x200
148 147
149 /* 148 /*
150 * Number of supported shared contexts. 149 * Number of supported shared contexts.
151 * This is the maximum number of software cont 150 * This is the maximum number of software contexts that can share
152 * a hardware send/receive context. 151 * a hardware send/receive context.
153 */ 152 */
154 #define HFI1_MAX_SHARED_CTXTS 8 153 #define HFI1_MAX_SHARED_CTXTS 8
155 154
156 /* 155 /*
157 * Poll types 156 * Poll types
158 */ 157 */
159 #define HFI1_POLL_TYPE_ANYRCV 0x0 158 #define HFI1_POLL_TYPE_ANYRCV 0x0
160 #define HFI1_POLL_TYPE_URGENT 0x1 159 #define HFI1_POLL_TYPE_URGENT 0x1
161 160
162 enum hfi1_sdma_comp_state { 161 enum hfi1_sdma_comp_state {
163 FREE = 0, 162 FREE = 0,
164 QUEUED, 163 QUEUED,
165 COMPLETE, 164 COMPLETE,
166 ERROR 165 ERROR
167 }; 166 };
168 167
169 /* 168 /*
170 * SDMA completion ring entry 169 * SDMA completion ring entry
171 */ 170 */
172 struct hfi1_sdma_comp_entry { 171 struct hfi1_sdma_comp_entry {
173 __u32 status; 172 __u32 status;
174 __u32 errcode; 173 __u32 errcode;
175 }; 174 };
176 175
177 /* 176 /*
178 * Device status and notifications from driver 177 * Device status and notifications from driver to user-space.
179 */ 178 */
180 struct hfi1_status { 179 struct hfi1_status {
181 __aligned_u64 dev; /* device/hw s 180 __aligned_u64 dev; /* device/hw status bits */
182 __aligned_u64 port; /* port state 181 __aligned_u64 port; /* port state and status bits */
183 char freezemsg[]; !! 182 char freezemsg[0];
184 }; 183 };
185 184
186 enum sdma_req_opcode { 185 enum sdma_req_opcode {
187 EXPECTED = 0, 186 EXPECTED = 0,
188 EAGER 187 EAGER
189 }; 188 };
190 189
191 #define HFI1_SDMA_REQ_VERSION_MASK 0xF 190 #define HFI1_SDMA_REQ_VERSION_MASK 0xF
192 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 191 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
193 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF 192 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF
194 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 193 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
195 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 194 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
196 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 195 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
197 196
198 struct sdma_req_info { 197 struct sdma_req_info {
199 /* 198 /*
200 * bits 0-3 - version (currently unuse 199 * bits 0-3 - version (currently unused)
201 * bits 4-7 - opcode (enum sdma_req_op 200 * bits 4-7 - opcode (enum sdma_req_opcode)
202 * bits 8-15 - io vector count 201 * bits 8-15 - io vector count
203 */ 202 */
204 __u16 ctrl; 203 __u16 ctrl;
205 /* 204 /*
206 * Number of fragments contained in th 205 * Number of fragments contained in this request.
207 * User-space has already computed how 206 * User-space has already computed how many
208 * fragment-sized packet the user buff 207 * fragment-sized packet the user buffer will be
209 * split into. 208 * split into.
210 */ 209 */
211 __u16 npkts; 210 __u16 npkts;
212 /* 211 /*
213 * Size of each fragment the user buff 212 * Size of each fragment the user buffer will be
214 * split into. 213 * split into.
215 */ 214 */
216 __u16 fragsize; 215 __u16 fragsize;
217 /* 216 /*
218 * Index of the slot in the SDMA compl 217 * Index of the slot in the SDMA completion ring
219 * this request should be using. User- 218 * this request should be using. User-space is
220 * in charge of managing its own ring. 219 * in charge of managing its own ring.
221 */ 220 */
222 __u16 comp_idx; 221 __u16 comp_idx;
223 } __attribute__((__packed__)); 222 } __attribute__((__packed__));
224 223
225 /* 224 /*
226 * SW KDETH header. 225 * SW KDETH header.
227 * swdata is SW defined portion. 226 * swdata is SW defined portion.
228 */ 227 */
229 struct hfi1_kdeth_header { 228 struct hfi1_kdeth_header {
230 __le32 ver_tid_offset; 229 __le32 ver_tid_offset;
231 __le16 jkey; 230 __le16 jkey;
232 __le16 hcrc; 231 __le16 hcrc;
233 __le32 swdata[7]; 232 __le32 swdata[7];
234 } __attribute__((__packed__)); 233 } __attribute__((__packed__));
235 234
236 /* 235 /*
237 * Structure describing the headers that User 236 * Structure describing the headers that User space uses. The
238 * structure above is a subset of this one. 237 * structure above is a subset of this one.
239 */ 238 */
240 struct hfi1_pkt_header { 239 struct hfi1_pkt_header {
241 __le16 pbc[4]; 240 __le16 pbc[4];
242 __be16 lrh[4]; 241 __be16 lrh[4];
243 __be32 bth[3]; 242 __be32 bth[3];
244 struct hfi1_kdeth_header kdeth; 243 struct hfi1_kdeth_header kdeth;
245 } __attribute__((__packed__)); 244 } __attribute__((__packed__));
246 245
247 246
248 /* 247 /*
249 * The list of usermode accessible registers. 248 * The list of usermode accessible registers.
250 */ 249 */
251 enum hfi1_ureg { 250 enum hfi1_ureg {
252 /* (RO) DMA RcvHdr to be used next. * 251 /* (RO) DMA RcvHdr to be used next. */
253 ur_rcvhdrtail = 0, 252 ur_rcvhdrtail = 0,
254 /* (RW) RcvHdr entry to be processed 253 /* (RW) RcvHdr entry to be processed next by host. */
255 ur_rcvhdrhead = 1, 254 ur_rcvhdrhead = 1,
256 /* (RO) Index of next Eager index to 255 /* (RO) Index of next Eager index to use. */
257 ur_rcvegrindextail = 2, 256 ur_rcvegrindextail = 2,
258 /* (RW) Eager TID to be processed nex 257 /* (RW) Eager TID to be processed next */
259 ur_rcvegrindexhead = 3, 258 ur_rcvegrindexhead = 3,
260 /* (RO) Receive Eager Offset Tail */ 259 /* (RO) Receive Eager Offset Tail */
261 ur_rcvegroffsettail = 4, 260 ur_rcvegroffsettail = 4,
262 /* For internal use only; max register 261 /* For internal use only; max register number. */
263 ur_maxreg, 262 ur_maxreg,
264 /* (RW) Receive TID flow table */ 263 /* (RW) Receive TID flow table */
265 ur_rcvtidflowtable = 256 264 ur_rcvtidflowtable = 256
266 }; 265 };
267 266
268 #endif /* _LINIUX__HFI1_USER_H */ 267 #endif /* _LINIUX__HFI1_USER_H */
269 268
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