1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Lin <<
2 /* 1 /*
3 * Copyright (c) 2013-2015, Mellanox Technolog 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * 3 *
5 * This software is available to you under a c 4 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed un 5 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, ava 6 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this sourc 7 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
10 * 9 *
11 * Redistribution and use in source and bi 10 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted pro 11 * without modification, are permitted provided that the following
13 * conditions are met: 12 * conditions are met:
14 * 13 *
15 * - Redistributions of source code must 14 * - Redistributions of source code must retain the above
16 * copyright notice, this list of condi 15 * copyright notice, this list of conditions and the following
17 * disclaimer. 16 * disclaimer.
18 * 17 *
19 * - Redistributions in binary form must 18 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of condi 19 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/ 20 * disclaimer in the documentation and/or other materials
22 * provided with the distribution. 21 * provided with the distribution.
23 * 22 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 30 * SOFTWARE.
32 */ 31 */
33 32
34 #ifndef MLX5_ABI_USER_H 33 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H 34 #define MLX5_ABI_USER_H
36 35
37 #include <linux/types.h> 36 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALE <<
39 #include <rdma/ib_user_ioctl_verbs.h> <<
40 #include <rdma/mlx5_user_ioctl_verbs.h> <<
41 37
42 enum { 38 enum {
43 MLX5_QP_FLAG_SIGNATURE = 1 << 39 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
44 MLX5_QP_FLAG_SCATTER_CQE = 1 << 40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
45 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << <<
46 MLX5_QP_FLAG_BFREG_INDEX = 1 << <<
47 MLX5_QP_FLAG_TYPE_DCT = 1 << <<
48 MLX5_QP_FLAG_TYPE_DCI = 1 << <<
49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 <<
50 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 <<
51 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << <<
52 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE <<
53 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, <<
54 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, <<
55 }; 41 };
56 42
57 enum { 43 enum {
58 MLX5_SRQ_FLAG_SIGNATURE = 1 << 44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
59 }; 45 };
60 46
61 enum { 47 enum {
62 MLX5_WQ_FLAG_SIGNATURE = 1 << 48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
63 }; 49 };
64 50
65 /* Increment this value if any changes that br 51 /* Increment this value if any changes that break userspace ABI
66 * compatibility are made. 52 * compatibility are made.
67 */ 53 */
68 #define MLX5_IB_UVERBS_ABI_VERSION 1 54 #define MLX5_IB_UVERBS_ABI_VERSION 1
69 55
70 /* Make sure that all structs defined in this 56 /* Make sure that all structs defined in this file remain laid out so
71 * that they pack the same way on 32-bit and 6 57 * that they pack the same way on 32-bit and 64-bit architectures (to
72 * avoid incompatibility between 32-bit usersp 58 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
73 * In particular do not use pointer types -- p 59 * In particular do not use pointer types -- pass pointers in __u64
74 * instead. 60 * instead.
75 */ 61 */
76 62
77 struct mlx5_ib_alloc_ucontext_req { 63 struct mlx5_ib_alloc_ucontext_req {
78 __u32 total_num_bfregs; !! 64 __u32 total_num_uuars;
79 __u32 num_low_latency_bfregs; !! 65 __u32 num_low_latency_uuars;
80 }; 66 };
81 67
82 enum mlx5_lib_caps { <<
83 MLX5_LIB_CAP_4K_UAR = (__u64)1 << <<
84 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << <<
85 }; <<
86 <<
87 enum mlx5_ib_alloc_uctx_v2_flags { <<
88 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, <<
89 }; <<
90 struct mlx5_ib_alloc_ucontext_req_v2 { 68 struct mlx5_ib_alloc_ucontext_req_v2 {
91 __u32 total_num_bfregs; !! 69 __u32 total_num_uuars;
92 __u32 num_low_latency_bfregs; !! 70 __u32 num_low_latency_uuars;
93 __u32 flags; 71 __u32 flags;
94 __u32 comp_mask; 72 __u32 comp_mask;
95 __u8 max_cqe_version; 73 __u8 max_cqe_version;
96 __u8 reserved0; 74 __u8 reserved0;
97 __u16 reserved1; 75 __u16 reserved1;
98 __u32 reserved2; 76 __u32 reserved2;
99 __aligned_u64 lib_caps; <<
100 }; 77 };
101 78
102 enum mlx5_ib_alloc_ucontext_resp_mask { 79 enum mlx5_ib_alloc_ucontext_resp_mask {
103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_ 80 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_ <<
105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE <<
106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2R <<
107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_ <<
108 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_ <<
109 }; 81 };
110 82
111 enum mlx5_user_cmds_supp_uhw { 83 enum mlx5_user_cmds_supp_uhw {
112 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 84 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
113 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 85 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
114 }; 86 };
115 87
116 /* The eth_min_inline response value is set to <<
117 * returned value to allow user-space to deal <<
118 */ <<
119 enum mlx5_user_inline_mode { <<
120 MLX5_USER_INLINE_MODE_NA, <<
121 MLX5_USER_INLINE_MODE_NONE, <<
122 MLX5_USER_INLINE_MODE_L2, <<
123 MLX5_USER_INLINE_MODE_IP, <<
124 MLX5_USER_INLINE_MODE_TCP_UDP, <<
125 }; <<
126 <<
127 enum { <<
128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F <<
129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F <<
130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F <<
131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F <<
132 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F <<
133 }; <<
134 <<
135 struct mlx5_ib_alloc_ucontext_resp { 88 struct mlx5_ib_alloc_ucontext_resp {
136 __u32 qp_tab_size; 89 __u32 qp_tab_size;
137 __u32 bf_reg_size; 90 __u32 bf_reg_size;
138 __u32 tot_bfregs; !! 91 __u32 tot_uuars;
139 __u32 cache_line_size; 92 __u32 cache_line_size;
140 __u16 max_sq_desc_sz; 93 __u16 max_sq_desc_sz;
141 __u16 max_rq_desc_sz; 94 __u16 max_rq_desc_sz;
142 __u32 max_send_wqebb; 95 __u32 max_send_wqebb;
143 __u32 max_recv_wr; 96 __u32 max_recv_wr;
144 __u32 max_srq_recv_wr; 97 __u32 max_srq_recv_wr;
145 __u16 num_ports; 98 __u16 num_ports;
146 __u16 flow_action_flags; !! 99 __u16 reserved1;
147 __u32 comp_mask; 100 __u32 comp_mask;
148 __u32 response_length; 101 __u32 response_length;
149 __u8 cqe_version; 102 __u8 cqe_version;
150 __u8 cmds_supp_uhw; 103 __u8 cmds_supp_uhw;
151 __u8 eth_min_inline; !! 104 __u16 reserved2;
152 __u8 clock_info_versions; !! 105 __u64 hca_core_clock_offset;
153 __aligned_u64 hca_core_clock_offset; <<
154 __u32 log_uar_size; <<
155 __u32 num_uars_per_page; <<
156 __u32 num_dyn_bfregs; <<
157 __u32 dump_fill_mkey; <<
158 }; 106 };
159 107
160 struct mlx5_ib_alloc_pd_resp { 108 struct mlx5_ib_alloc_pd_resp {
161 __u32 pdn; 109 __u32 pdn;
162 }; 110 };
163 111
164 struct mlx5_ib_tso_caps { 112 struct mlx5_ib_tso_caps {
165 __u32 max_tso; /* Maximum tso payload 113 __u32 max_tso; /* Maximum tso payload size in bytes */
166 114
167 /* Corresponding bit will be set if qp 115 /* Corresponding bit will be set if qp type from
168 * 'enum ib_qp_type' is supported, e.g 116 * 'enum ib_qp_type' is supported, e.g.
169 * supported_qpts |= 1 << IB_QPT_UD 117 * supported_qpts |= 1 << IB_QPT_UD
170 */ 118 */
171 __u32 supported_qpts; 119 __u32 supported_qpts;
172 }; 120 };
173 121
174 struct mlx5_ib_rss_caps { 122 struct mlx5_ib_rss_caps {
175 __aligned_u64 rx_hash_fields_mask; /* !! 123 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
176 __u8 rx_hash_function; /* enum mlx5_rx 124 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
177 __u8 reserved[7]; 125 __u8 reserved[7];
178 }; 126 };
179 127
180 enum mlx5_ib_cqe_comp_res_format { 128 enum mlx5_ib_cqe_comp_res_format {
181 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 129 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
182 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 130 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
183 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 !! 131 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
184 }; 132 };
185 133
186 struct mlx5_ib_cqe_comp_caps { 134 struct mlx5_ib_cqe_comp_caps {
187 __u32 max_num; 135 __u32 max_num;
188 __u32 supported_format; /* enum mlx5_i 136 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
189 }; 137 };
190 138
191 enum mlx5_ib_packet_pacing_cap_flags { <<
192 MLX5_IB_PP_SUPPORT_BURST = 1 << <<
193 }; <<
194 <<
195 struct mlx5_packet_pacing_caps { 139 struct mlx5_packet_pacing_caps {
196 __u32 qp_rate_limit_min; 140 __u32 qp_rate_limit_min;
197 __u32 qp_rate_limit_max; /* In kpbs */ 141 __u32 qp_rate_limit_max; /* In kpbs */
198 142
199 /* Corresponding bit will be set if qp 143 /* Corresponding bit will be set if qp type from
200 * 'enum ib_qp_type' is supported, e.g 144 * 'enum ib_qp_type' is supported, e.g.
201 * supported_qpts |= 1 << IB_QPT_RAW_P 145 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
202 */ 146 */
203 __u32 supported_qpts; 147 __u32 supported_qpts;
204 __u8 cap_flags; /* enum mlx5_ib_packe <<
205 __u8 reserved[3]; <<
206 }; <<
207 <<
208 enum mlx5_ib_mpw_caps { <<
209 MPW_RESERVED = 1 << 0, <<
210 MLX5_IB_ALLOW_MPW = 1 << 1, <<
211 MLX5_IB_SUPPORT_EMPW = 1 << 2, <<
212 }; <<
213 <<
214 enum mlx5_ib_sw_parsing_offloads { <<
215 MLX5_IB_SW_PARSING = 1 << 0, <<
216 MLX5_IB_SW_PARSING_CSUM = 1 << 1, <<
217 MLX5_IB_SW_PARSING_LSO = 1 << 2, <<
218 }; <<
219 <<
220 struct mlx5_ib_sw_parsing_caps { <<
221 __u32 sw_parsing_offloads; /* enum mlx <<
222 <<
223 /* Corresponding bit will be set if qp <<
224 * 'enum ib_qp_type' is supported, e.g <<
225 * supported_qpts |= 1 << IB_QPT_RAW_P <<
226 */ <<
227 __u32 supported_qpts; <<
228 }; <<
229 <<
230 struct mlx5_ib_striding_rq_caps { <<
231 __u32 min_single_stride_log_num_of_byt <<
232 __u32 max_single_stride_log_num_of_byt <<
233 __u32 min_single_wqe_log_num_of_stride <<
234 __u32 max_single_wqe_log_num_of_stride <<
235 <<
236 /* Corresponding bit will be set if qp <<
237 * 'enum ib_qp_type' is supported, e.g <<
238 * supported_qpts |= 1 << IB_QPT_RAW_P <<
239 */ <<
240 __u32 supported_qpts; <<
241 __u32 reserved; 148 __u32 reserved;
242 }; 149 };
243 150
244 struct mlx5_ib_dci_streams_caps { <<
245 __u8 max_log_num_concurent; <<
246 __u8 max_log_num_errored; <<
247 }; <<
248 <<
249 enum mlx5_ib_query_dev_resp_flags { <<
250 /* Support 128B CQE compression */ <<
251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ <<
252 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ <<
253 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CR <<
254 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_ <<
255 }; <<
256 <<
257 enum mlx5_ib_tunnel_offloads { <<
258 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 < <<
259 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 < <<
260 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 < <<
261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 <<
262 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 <<
263 }; <<
264 <<
265 struct mlx5_ib_query_device_resp { 151 struct mlx5_ib_query_device_resp {
266 __u32 comp_mask; 152 __u32 comp_mask;
267 __u32 response_length; 153 __u32 response_length;
268 struct mlx5_ib_tso_caps tso_caps; 154 struct mlx5_ib_tso_caps tso_caps;
269 struct mlx5_ib_rss_caps rss_caps; 155 struct mlx5_ib_rss_caps rss_caps;
270 struct mlx5_ib_cqe_comp_caps cqe_comp 156 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
271 struct mlx5_packet_pacing_caps packet 157 struct mlx5_packet_pacing_caps packet_pacing_caps;
272 __u32 mlx5_ib_support_multi_pkt_send 158 __u32 mlx5_ib_support_multi_pkt_send_wqes;
273 __u32 flags; /* Use enum mlx5_ib_que !! 159 __u32 reserved;
274 struct mlx5_ib_sw_parsing_caps sw_pars <<
275 struct mlx5_ib_striding_rq_caps stridi <<
276 __u32 tunnel_offloads_caps; /* enum <<
277 struct mlx5_ib_dci_streams_caps dci_s <<
278 __u16 reserved; <<
279 struct mlx5_ib_uapi_reg reg_c0; <<
280 }; <<
281 <<
282 enum mlx5_ib_create_cq_flags { <<
283 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD <<
284 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX <<
285 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS <<
286 }; 160 };
287 161
288 struct mlx5_ib_create_cq { 162 struct mlx5_ib_create_cq {
289 __aligned_u64 buf_addr; !! 163 __u64 buf_addr;
290 __aligned_u64 db_addr; !! 164 __u64 db_addr;
291 __u32 cqe_size; 165 __u32 cqe_size;
292 __u8 cqe_comp_en; 166 __u8 cqe_comp_en;
293 __u8 cqe_comp_res_format; 167 __u8 cqe_comp_res_format;
294 __u16 flags; !! 168 __u16 reserved; /* explicit padding (optional on i386) */
295 __u16 uar_page_index; <<
296 __u16 reserved0; <<
297 __u32 reserved1; <<
298 }; 169 };
299 170
300 struct mlx5_ib_create_cq_resp { 171 struct mlx5_ib_create_cq_resp {
301 __u32 cqn; 172 __u32 cqn;
302 __u32 reserved; 173 __u32 reserved;
303 }; 174 };
304 175
305 struct mlx5_ib_resize_cq { 176 struct mlx5_ib_resize_cq {
306 __aligned_u64 buf_addr; !! 177 __u64 buf_addr;
307 __u16 cqe_size; 178 __u16 cqe_size;
308 __u16 reserved0; 179 __u16 reserved0;
309 __u32 reserved1; 180 __u32 reserved1;
310 }; 181 };
311 182
312 struct mlx5_ib_create_srq { 183 struct mlx5_ib_create_srq {
313 __aligned_u64 buf_addr; !! 184 __u64 buf_addr;
314 __aligned_u64 db_addr; !! 185 __u64 db_addr;
315 __u32 flags; 186 __u32 flags;
316 __u32 reserved0; /* explicit padding 187 __u32 reserved0; /* explicit padding (optional on i386) */
317 __u32 uidx; 188 __u32 uidx;
318 __u32 reserved1; 189 __u32 reserved1;
319 }; 190 };
320 191
321 struct mlx5_ib_create_srq_resp { 192 struct mlx5_ib_create_srq_resp {
322 __u32 srqn; 193 __u32 srqn;
323 __u32 reserved; 194 __u32 reserved;
324 }; 195 };
325 196
326 struct mlx5_ib_create_qp_dci_streams { <<
327 __u8 log_num_concurent; <<
328 __u8 log_num_errored; <<
329 }; <<
330 <<
331 struct mlx5_ib_create_qp { 197 struct mlx5_ib_create_qp {
332 __aligned_u64 buf_addr; !! 198 __u64 buf_addr;
333 __aligned_u64 db_addr; !! 199 __u64 db_addr;
334 __u32 sq_wqe_count; 200 __u32 sq_wqe_count;
335 __u32 rq_wqe_count; 201 __u32 rq_wqe_count;
336 __u32 rq_wqe_shift; 202 __u32 rq_wqe_shift;
337 __u32 flags; 203 __u32 flags;
338 __u32 uidx; 204 __u32 uidx;
339 __u32 bfreg_index; !! 205 __u32 reserved0;
340 union { !! 206 __u64 sq_buf_addr;
341 __aligned_u64 sq_buf_addr; <<
342 __aligned_u64 access_key; <<
343 }; <<
344 __u32 ece_options; <<
345 struct mlx5_ib_create_qp_dci_streams <<
346 __u16 reserved; <<
347 }; 207 };
348 208
349 /* RX Hash function flags */ 209 /* RX Hash function flags */
350 enum mlx5_rx_hash_function_flags { 210 enum mlx5_rx_hash_function_flags {
351 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 211 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
352 }; 212 };
353 213
354 /* 214 /*
355 * RX Hash flags, these flags allows to set wh 215 * RX Hash flags, these flags allows to set which incoming packet's field should
356 * participates in RX Hash. Each flag represen 216 * participates in RX Hash. Each flag represent certain packet's field,
357 * when the flag is set the field that is repr 217 * when the flag is set the field that is represented by the flag will
358 * participate in RX Hash calculation. 218 * participate in RX Hash calculation.
359 * Note: *IPV4 and *IPV6 flags can't be enable 219 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
360 * and *TCP and *UDP flags can't be enabled to 220 * and *TCP and *UDP flags can't be enabled together on the same QP.
361 */ 221 */
362 enum mlx5_rx_hash_fields { 222 enum mlx5_rx_hash_fields {
363 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 223 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
364 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 224 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
365 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 225 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
366 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 226 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
367 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 227 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
368 MLX5_RX_HASH_DST_PORT_TCP = 1 << 228 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
369 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 229 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
370 MLX5_RX_HASH_DST_PORT_UDP = 1 << !! 230 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
371 MLX5_RX_HASH_IPSEC_SPI = 1 << <<
372 /* Save bits for future fields */ <<
373 MLX5_RX_HASH_INNER = (1UL <<
374 }; 231 };
375 232
376 struct mlx5_ib_create_qp_rss { 233 struct mlx5_ib_create_qp_rss {
377 __aligned_u64 rx_hash_fields_mask; /* !! 234 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
378 __u8 rx_hash_function; /* enum mlx5_rx 235 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
379 __u8 rx_key_len; /* valid only for Toe 236 __u8 rx_key_len; /* valid only for Toeplitz */
380 __u8 reserved[6]; 237 __u8 reserved[6];
381 __u8 rx_hash_key[128]; /* valid only f 238 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
382 __u32 comp_mask; 239 __u32 comp_mask;
383 __u32 flags; !! 240 __u32 reserved1;
384 }; <<
385 <<
386 enum mlx5_ib_create_qp_resp_mask { <<
387 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL <<
388 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL <<
389 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL <<
390 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL <<
391 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_AD <<
392 }; 241 };
393 242
394 struct mlx5_ib_create_qp_resp { 243 struct mlx5_ib_create_qp_resp {
395 __u32 bfreg_index; !! 244 __u32 uuar_index;
396 __u32 ece_options; <<
397 __u32 comp_mask; <<
398 __u32 tirn; <<
399 __u32 tisn; <<
400 __u32 rqn; <<
401 __u32 sqn; <<
402 __u32 reserved1; <<
403 __u64 tir_icm_addr; <<
404 }; 245 };
405 246
406 struct mlx5_ib_alloc_mw { 247 struct mlx5_ib_alloc_mw {
407 __u32 comp_mask; 248 __u32 comp_mask;
408 __u8 num_klms; 249 __u8 num_klms;
409 __u8 reserved1; 250 __u8 reserved1;
410 __u16 reserved2; 251 __u16 reserved2;
411 }; 252 };
412 253
413 enum mlx5_ib_create_wq_mask { <<
414 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 < <<
415 }; <<
416 <<
417 struct mlx5_ib_create_wq { 254 struct mlx5_ib_create_wq {
418 __aligned_u64 buf_addr; !! 255 __u64 buf_addr;
419 __aligned_u64 db_addr; !! 256 __u64 db_addr;
420 __u32 rq_wqe_count; 257 __u32 rq_wqe_count;
421 __u32 rq_wqe_shift; 258 __u32 rq_wqe_shift;
422 __u32 user_index; 259 __u32 user_index;
423 __u32 flags; 260 __u32 flags;
424 __u32 comp_mask; 261 __u32 comp_mask;
425 __u32 single_stride_log_num_of_bytes !! 262 __u32 reserved;
426 __u32 single_wqe_log_num_of_strides; <<
427 __u32 two_byte_shift_en; <<
428 }; 263 };
429 264
430 struct mlx5_ib_create_ah_resp { 265 struct mlx5_ib_create_ah_resp {
431 __u32 response_length; 266 __u32 response_length;
432 __u8 dmac[ETH_ALEN]; 267 __u8 dmac[ETH_ALEN];
433 __u8 reserved[6]; 268 __u8 reserved[6];
434 }; 269 };
435 270
436 struct mlx5_ib_burst_info { <<
437 __u32 max_burst_sz; <<
438 __u16 typical_pkt_sz; <<
439 __u16 reserved; <<
440 }; <<
441 <<
442 struct mlx5_ib_modify_qp { <<
443 __u32 comp_mask; <<
444 struct mlx5_ib_burst_info burst_info; <<
445 __u32 ece_options <<
446 }; <<
447 <<
448 struct mlx5_ib_modify_qp_resp { <<
449 __u32 response_length; <<
450 __u32 dctn; <<
451 __u32 ece_options; <<
452 __u32 reserved; <<
453 }; <<
454 <<
455 struct mlx5_ib_create_wq_resp { 271 struct mlx5_ib_create_wq_resp {
456 __u32 response_length; 272 __u32 response_length;
457 __u32 reserved; 273 __u32 reserved;
458 }; 274 };
459 275
460 struct mlx5_ib_create_rwq_ind_tbl_resp { 276 struct mlx5_ib_create_rwq_ind_tbl_resp {
461 __u32 response_length; 277 __u32 response_length;
462 __u32 reserved; 278 __u32 reserved;
463 }; 279 };
464 280
465 struct mlx5_ib_modify_wq { 281 struct mlx5_ib_modify_wq {
466 __u32 comp_mask; 282 __u32 comp_mask;
467 __u32 reserved; 283 __u32 reserved;
468 }; 284 };
469 <<
470 struct mlx5_ib_clock_info { <<
471 __u32 sign; <<
472 __u32 resv; <<
473 __aligned_u64 nsec; <<
474 __aligned_u64 cycles; <<
475 __aligned_u64 frac; <<
476 __u32 mult; <<
477 __u32 shift; <<
478 __aligned_u64 mask; <<
479 __aligned_u64 overflow_period; <<
480 }; <<
481 <<
482 enum mlx5_ib_mmap_cmd { <<
483 MLX5_IB_MMAP_REGULAR_PAGE <<
484 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES <<
485 MLX5_IB_MMAP_WC_PAGE <<
486 MLX5_IB_MMAP_NC_PAGE <<
487 /* 5 is chosen in order to be compatib <<
488 MLX5_IB_MMAP_CORE_CLOCK <<
489 MLX5_IB_MMAP_ALLOC_WC <<
490 MLX5_IB_MMAP_CLOCK_INFO <<
491 MLX5_IB_MMAP_DEVICE_MEM <<
492 }; <<
493 <<
494 enum { <<
495 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1 <<
496 }; <<
497 <<
498 /* Bit indexes for the mlx5_alloc_ucontext_res <<
499 enum { <<
500 MLX5_IB_CLOCK_INFO_V1 = 0 <<
501 }; <<
502 <<
503 struct mlx5_ib_flow_counters_desc { <<
504 __u32 description; <<
505 __u32 index; <<
506 }; <<
507 <<
508 struct mlx5_ib_flow_counters_data { <<
509 RDMA_UAPI_PTR(struct mlx5_ib_flow_coun <<
510 __u32 ncounters; <<
511 __u32 reserved; <<
512 }; <<
513 <<
514 struct mlx5_ib_create_flow { <<
515 __u32 ncounters_data; <<
516 __u32 reserved; <<
517 /* <<
518 * Following are counters data based o <<
519 * entry in the data[] should match a <<
520 * that was pointed by a counters spec <<
521 */ <<
522 struct mlx5_ib_flow_counters_data data <<
523 }; <<
524 <<
525 #endif /* MLX5_ABI_USER_H */ 285 #endif /* MLX5_ABI_USER_H */
526 286
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