1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Lin 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2 /* 2 /*
3 * Copyright (c) 2013-2015, Mellanox Technolog 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * 4 *
5 * This software is available to you under a c 5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed un 6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, ava 7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this sourc 8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below: 9 * OpenIB.org BSD license below:
10 * 10 *
11 * Redistribution and use in source and bi 11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted pro 12 * without modification, are permitted provided that the following
13 * conditions are met: 13 * conditions are met:
14 * 14 *
15 * - Redistributions of source code must 15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of condi 16 * copyright notice, this list of conditions and the following
17 * disclaimer. 17 * disclaimer.
18 * 18 *
19 * - Redistributions in binary form must 19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of condi 20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/ 21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution. 22 * provided with the distribution.
23 * 23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 31 * SOFTWARE.
32 */ 32 */
33 33
34 #ifndef MLX5_ABI_USER_H 34 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H
36 36
37 #include <linux/types.h> 37 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALE 38 #include <linux/if_ether.h> /* For ETH_ALEN. */
39 #include <rdma/ib_user_ioctl_verbs.h> <<
40 #include <rdma/mlx5_user_ioctl_verbs.h> <<
41 39
42 enum { 40 enum {
43 MLX5_QP_FLAG_SIGNATURE = 1 << 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
44 MLX5_QP_FLAG_SCATTER_CQE = 1 << 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
45 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
46 MLX5_QP_FLAG_BFREG_INDEX = 1 << 44 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
47 MLX5_QP_FLAG_TYPE_DCT = 1 << 45 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
48 MLX5_QP_FLAG_TYPE_DCI = 1 << 46 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 <<
50 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 <<
51 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << <<
52 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE <<
53 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, <<
54 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, <<
55 }; 47 };
56 48
57 enum { 49 enum {
58 MLX5_SRQ_FLAG_SIGNATURE = 1 << 50 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
59 }; 51 };
60 52
61 enum { 53 enum {
62 MLX5_WQ_FLAG_SIGNATURE = 1 << 54 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
63 }; 55 };
64 56
65 /* Increment this value if any changes that br 57 /* Increment this value if any changes that break userspace ABI
66 * compatibility are made. 58 * compatibility are made.
67 */ 59 */
68 #define MLX5_IB_UVERBS_ABI_VERSION 1 60 #define MLX5_IB_UVERBS_ABI_VERSION 1
69 61
70 /* Make sure that all structs defined in this 62 /* Make sure that all structs defined in this file remain laid out so
71 * that they pack the same way on 32-bit and 6 63 * that they pack the same way on 32-bit and 64-bit architectures (to
72 * avoid incompatibility between 32-bit usersp 64 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
73 * In particular do not use pointer types -- p 65 * In particular do not use pointer types -- pass pointers in __u64
74 * instead. 66 * instead.
75 */ 67 */
76 68
77 struct mlx5_ib_alloc_ucontext_req { 69 struct mlx5_ib_alloc_ucontext_req {
78 __u32 total_num_bfregs; 70 __u32 total_num_bfregs;
79 __u32 num_low_latency_bfregs; 71 __u32 num_low_latency_bfregs;
80 }; 72 };
81 73
82 enum mlx5_lib_caps { 74 enum mlx5_lib_caps {
83 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 75 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
84 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << <<
85 }; 76 };
86 77
87 enum mlx5_ib_alloc_uctx_v2_flags { <<
88 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, <<
89 }; <<
90 struct mlx5_ib_alloc_ucontext_req_v2 { 78 struct mlx5_ib_alloc_ucontext_req_v2 {
91 __u32 total_num_bfregs; 79 __u32 total_num_bfregs;
92 __u32 num_low_latency_bfregs; 80 __u32 num_low_latency_bfregs;
93 __u32 flags; 81 __u32 flags;
94 __u32 comp_mask; 82 __u32 comp_mask;
95 __u8 max_cqe_version; 83 __u8 max_cqe_version;
96 __u8 reserved0; 84 __u8 reserved0;
97 __u16 reserved1; 85 __u16 reserved1;
98 __u32 reserved2; 86 __u32 reserved2;
99 __aligned_u64 lib_caps; 87 __aligned_u64 lib_caps;
100 }; 88 };
101 89
102 enum mlx5_ib_alloc_ucontext_resp_mask { 90 enum mlx5_ib_alloc_ucontext_resp_mask {
103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_ 91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_ <<
105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE <<
106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2R <<
107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_ <<
108 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_ <<
109 }; 92 };
110 93
111 enum mlx5_user_cmds_supp_uhw { 94 enum mlx5_user_cmds_supp_uhw {
112 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
113 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 96 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
114 }; 97 };
115 98
116 /* The eth_min_inline response value is set to 99 /* The eth_min_inline response value is set to off-by-one vs the FW
117 * returned value to allow user-space to deal 100 * returned value to allow user-space to deal with older kernels.
118 */ 101 */
119 enum mlx5_user_inline_mode { 102 enum mlx5_user_inline_mode {
120 MLX5_USER_INLINE_MODE_NA, 103 MLX5_USER_INLINE_MODE_NA,
121 MLX5_USER_INLINE_MODE_NONE, 104 MLX5_USER_INLINE_MODE_NONE,
122 MLX5_USER_INLINE_MODE_L2, 105 MLX5_USER_INLINE_MODE_L2,
123 MLX5_USER_INLINE_MODE_IP, 106 MLX5_USER_INLINE_MODE_IP,
124 MLX5_USER_INLINE_MODE_TCP_UDP, 107 MLX5_USER_INLINE_MODE_TCP_UDP,
125 }; 108 };
126 109
127 enum { 110 enum {
128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 111 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 112 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 113 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 114 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
132 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 115 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
133 }; 116 };
134 117
135 struct mlx5_ib_alloc_ucontext_resp { 118 struct mlx5_ib_alloc_ucontext_resp {
136 __u32 qp_tab_size; 119 __u32 qp_tab_size;
137 __u32 bf_reg_size; 120 __u32 bf_reg_size;
138 __u32 tot_bfregs; 121 __u32 tot_bfregs;
139 __u32 cache_line_size; 122 __u32 cache_line_size;
140 __u16 max_sq_desc_sz; 123 __u16 max_sq_desc_sz;
141 __u16 max_rq_desc_sz; 124 __u16 max_rq_desc_sz;
142 __u32 max_send_wqebb; 125 __u32 max_send_wqebb;
143 __u32 max_recv_wr; 126 __u32 max_recv_wr;
144 __u32 max_srq_recv_wr; 127 __u32 max_srq_recv_wr;
145 __u16 num_ports; 128 __u16 num_ports;
146 __u16 flow_action_flags; 129 __u16 flow_action_flags;
147 __u32 comp_mask; 130 __u32 comp_mask;
148 __u32 response_length; 131 __u32 response_length;
149 __u8 cqe_version; 132 __u8 cqe_version;
150 __u8 cmds_supp_uhw; 133 __u8 cmds_supp_uhw;
151 __u8 eth_min_inline; 134 __u8 eth_min_inline;
152 __u8 clock_info_versions; 135 __u8 clock_info_versions;
153 __aligned_u64 hca_core_clock_offset; 136 __aligned_u64 hca_core_clock_offset;
154 __u32 log_uar_size; 137 __u32 log_uar_size;
155 __u32 num_uars_per_page; 138 __u32 num_uars_per_page;
156 __u32 num_dyn_bfregs; 139 __u32 num_dyn_bfregs;
157 __u32 dump_fill_mkey; !! 140 __u32 reserved3;
158 }; 141 };
159 142
160 struct mlx5_ib_alloc_pd_resp { 143 struct mlx5_ib_alloc_pd_resp {
161 __u32 pdn; 144 __u32 pdn;
162 }; 145 };
163 146
164 struct mlx5_ib_tso_caps { 147 struct mlx5_ib_tso_caps {
165 __u32 max_tso; /* Maximum tso payload 148 __u32 max_tso; /* Maximum tso payload size in bytes */
166 149
167 /* Corresponding bit will be set if qp 150 /* Corresponding bit will be set if qp type from
168 * 'enum ib_qp_type' is supported, e.g 151 * 'enum ib_qp_type' is supported, e.g.
169 * supported_qpts |= 1 << IB_QPT_UD 152 * supported_qpts |= 1 << IB_QPT_UD
170 */ 153 */
171 __u32 supported_qpts; 154 __u32 supported_qpts;
172 }; 155 };
173 156
174 struct mlx5_ib_rss_caps { 157 struct mlx5_ib_rss_caps {
175 __aligned_u64 rx_hash_fields_mask; /* 158 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
176 __u8 rx_hash_function; /* enum mlx5_rx 159 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
177 __u8 reserved[7]; 160 __u8 reserved[7];
178 }; 161 };
179 162
180 enum mlx5_ib_cqe_comp_res_format { 163 enum mlx5_ib_cqe_comp_res_format {
181 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 164 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
182 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 165 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
183 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 !! 166 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
184 }; 167 };
185 168
186 struct mlx5_ib_cqe_comp_caps { 169 struct mlx5_ib_cqe_comp_caps {
187 __u32 max_num; 170 __u32 max_num;
188 __u32 supported_format; /* enum mlx5_i 171 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
189 }; 172 };
190 173
191 enum mlx5_ib_packet_pacing_cap_flags { 174 enum mlx5_ib_packet_pacing_cap_flags {
192 MLX5_IB_PP_SUPPORT_BURST = 1 << 175 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
193 }; 176 };
194 177
195 struct mlx5_packet_pacing_caps { 178 struct mlx5_packet_pacing_caps {
196 __u32 qp_rate_limit_min; 179 __u32 qp_rate_limit_min;
197 __u32 qp_rate_limit_max; /* In kpbs */ 180 __u32 qp_rate_limit_max; /* In kpbs */
198 181
199 /* Corresponding bit will be set if qp 182 /* Corresponding bit will be set if qp type from
200 * 'enum ib_qp_type' is supported, e.g 183 * 'enum ib_qp_type' is supported, e.g.
201 * supported_qpts |= 1 << IB_QPT_RAW_P 184 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
202 */ 185 */
203 __u32 supported_qpts; 186 __u32 supported_qpts;
204 __u8 cap_flags; /* enum mlx5_ib_packe 187 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
205 __u8 reserved[3]; 188 __u8 reserved[3];
206 }; 189 };
207 190
208 enum mlx5_ib_mpw_caps { 191 enum mlx5_ib_mpw_caps {
209 MPW_RESERVED = 1 << 0, 192 MPW_RESERVED = 1 << 0,
210 MLX5_IB_ALLOW_MPW = 1 << 1, 193 MLX5_IB_ALLOW_MPW = 1 << 1,
211 MLX5_IB_SUPPORT_EMPW = 1 << 2, 194 MLX5_IB_SUPPORT_EMPW = 1 << 2,
212 }; 195 };
213 196
214 enum mlx5_ib_sw_parsing_offloads { 197 enum mlx5_ib_sw_parsing_offloads {
215 MLX5_IB_SW_PARSING = 1 << 0, 198 MLX5_IB_SW_PARSING = 1 << 0,
216 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 199 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
217 MLX5_IB_SW_PARSING_LSO = 1 << 2, 200 MLX5_IB_SW_PARSING_LSO = 1 << 2,
218 }; 201 };
219 202
220 struct mlx5_ib_sw_parsing_caps { 203 struct mlx5_ib_sw_parsing_caps {
221 __u32 sw_parsing_offloads; /* enum mlx 204 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
222 205
223 /* Corresponding bit will be set if qp 206 /* Corresponding bit will be set if qp type from
224 * 'enum ib_qp_type' is supported, e.g 207 * 'enum ib_qp_type' is supported, e.g.
225 * supported_qpts |= 1 << IB_QPT_RAW_P 208 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
226 */ 209 */
227 __u32 supported_qpts; 210 __u32 supported_qpts;
228 }; 211 };
229 212
230 struct mlx5_ib_striding_rq_caps { 213 struct mlx5_ib_striding_rq_caps {
231 __u32 min_single_stride_log_num_of_byt 214 __u32 min_single_stride_log_num_of_bytes;
232 __u32 max_single_stride_log_num_of_byt 215 __u32 max_single_stride_log_num_of_bytes;
233 __u32 min_single_wqe_log_num_of_stride 216 __u32 min_single_wqe_log_num_of_strides;
234 __u32 max_single_wqe_log_num_of_stride 217 __u32 max_single_wqe_log_num_of_strides;
235 218
236 /* Corresponding bit will be set if qp 219 /* Corresponding bit will be set if qp type from
237 * 'enum ib_qp_type' is supported, e.g 220 * 'enum ib_qp_type' is supported, e.g.
238 * supported_qpts |= 1 << IB_QPT_RAW_P 221 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
239 */ 222 */
240 __u32 supported_qpts; 223 __u32 supported_qpts;
241 __u32 reserved; 224 __u32 reserved;
242 }; 225 };
243 226
244 struct mlx5_ib_dci_streams_caps { <<
245 __u8 max_log_num_concurent; <<
246 __u8 max_log_num_errored; <<
247 }; <<
248 <<
249 enum mlx5_ib_query_dev_resp_flags { 227 enum mlx5_ib_query_dev_resp_flags {
250 /* Support 128B CQE compression */ 228 /* Support 128B CQE compression */
251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ 229 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
252 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ 230 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
253 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CR <<
254 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_ <<
255 }; 231 };
256 232
257 enum mlx5_ib_tunnel_offloads { 233 enum mlx5_ib_tunnel_offloads {
258 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 < 234 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
259 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 < 235 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
260 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 < !! 236 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 <<
262 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 <<
263 }; 237 };
264 238
265 struct mlx5_ib_query_device_resp { 239 struct mlx5_ib_query_device_resp {
266 __u32 comp_mask; 240 __u32 comp_mask;
267 __u32 response_length; 241 __u32 response_length;
268 struct mlx5_ib_tso_caps tso_caps; 242 struct mlx5_ib_tso_caps tso_caps;
269 struct mlx5_ib_rss_caps rss_caps; 243 struct mlx5_ib_rss_caps rss_caps;
270 struct mlx5_ib_cqe_comp_caps cqe_comp 244 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
271 struct mlx5_packet_pacing_caps packet 245 struct mlx5_packet_pacing_caps packet_pacing_caps;
272 __u32 mlx5_ib_support_multi_pkt_send 246 __u32 mlx5_ib_support_multi_pkt_send_wqes;
273 __u32 flags; /* Use enum mlx5_ib_que 247 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
274 struct mlx5_ib_sw_parsing_caps sw_pars 248 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
275 struct mlx5_ib_striding_rq_caps stridi 249 struct mlx5_ib_striding_rq_caps striding_rq_caps;
276 __u32 tunnel_offloads_caps; /* enum 250 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
277 struct mlx5_ib_dci_streams_caps dci_s !! 251 __u32 reserved;
278 __u16 reserved; <<
279 struct mlx5_ib_uapi_reg reg_c0; <<
280 }; 252 };
281 253
282 enum mlx5_ib_create_cq_flags { 254 enum mlx5_ib_create_cq_flags {
283 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD 255 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
284 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX <<
285 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS <<
286 }; 256 };
287 257
288 struct mlx5_ib_create_cq { 258 struct mlx5_ib_create_cq {
289 __aligned_u64 buf_addr; 259 __aligned_u64 buf_addr;
290 __aligned_u64 db_addr; 260 __aligned_u64 db_addr;
291 __u32 cqe_size; 261 __u32 cqe_size;
292 __u8 cqe_comp_en; 262 __u8 cqe_comp_en;
293 __u8 cqe_comp_res_format; 263 __u8 cqe_comp_res_format;
294 __u16 flags; 264 __u16 flags;
295 __u16 uar_page_index; <<
296 __u16 reserved0; <<
297 __u32 reserved1; <<
298 }; 265 };
299 266
300 struct mlx5_ib_create_cq_resp { 267 struct mlx5_ib_create_cq_resp {
301 __u32 cqn; 268 __u32 cqn;
302 __u32 reserved; 269 __u32 reserved;
303 }; 270 };
304 271
305 struct mlx5_ib_resize_cq { 272 struct mlx5_ib_resize_cq {
306 __aligned_u64 buf_addr; 273 __aligned_u64 buf_addr;
307 __u16 cqe_size; 274 __u16 cqe_size;
308 __u16 reserved0; 275 __u16 reserved0;
309 __u32 reserved1; 276 __u32 reserved1;
310 }; 277 };
311 278
312 struct mlx5_ib_create_srq { 279 struct mlx5_ib_create_srq {
313 __aligned_u64 buf_addr; 280 __aligned_u64 buf_addr;
314 __aligned_u64 db_addr; 281 __aligned_u64 db_addr;
315 __u32 flags; 282 __u32 flags;
316 __u32 reserved0; /* explicit padding 283 __u32 reserved0; /* explicit padding (optional on i386) */
317 __u32 uidx; 284 __u32 uidx;
318 __u32 reserved1; 285 __u32 reserved1;
319 }; 286 };
320 287
321 struct mlx5_ib_create_srq_resp { 288 struct mlx5_ib_create_srq_resp {
322 __u32 srqn; 289 __u32 srqn;
323 __u32 reserved; 290 __u32 reserved;
324 }; 291 };
325 292
326 struct mlx5_ib_create_qp_dci_streams { <<
327 __u8 log_num_concurent; <<
328 __u8 log_num_errored; <<
329 }; <<
330 <<
331 struct mlx5_ib_create_qp { 293 struct mlx5_ib_create_qp {
332 __aligned_u64 buf_addr; 294 __aligned_u64 buf_addr;
333 __aligned_u64 db_addr; 295 __aligned_u64 db_addr;
334 __u32 sq_wqe_count; 296 __u32 sq_wqe_count;
335 __u32 rq_wqe_count; 297 __u32 rq_wqe_count;
336 __u32 rq_wqe_shift; 298 __u32 rq_wqe_shift;
337 __u32 flags; 299 __u32 flags;
338 __u32 uidx; 300 __u32 uidx;
339 __u32 bfreg_index; 301 __u32 bfreg_index;
340 union { 302 union {
341 __aligned_u64 sq_buf_addr; 303 __aligned_u64 sq_buf_addr;
342 __aligned_u64 access_key; 304 __aligned_u64 access_key;
343 }; 305 };
344 __u32 ece_options; <<
345 struct mlx5_ib_create_qp_dci_streams <<
346 __u16 reserved; <<
347 }; 306 };
348 307
349 /* RX Hash function flags */ 308 /* RX Hash function flags */
350 enum mlx5_rx_hash_function_flags { 309 enum mlx5_rx_hash_function_flags {
351 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 310 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
352 }; 311 };
353 312
354 /* 313 /*
355 * RX Hash flags, these flags allows to set wh 314 * RX Hash flags, these flags allows to set which incoming packet's field should
356 * participates in RX Hash. Each flag represen 315 * participates in RX Hash. Each flag represent certain packet's field,
357 * when the flag is set the field that is repr 316 * when the flag is set the field that is represented by the flag will
358 * participate in RX Hash calculation. 317 * participate in RX Hash calculation.
359 * Note: *IPV4 and *IPV6 flags can't be enable 318 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
360 * and *TCP and *UDP flags can't be enabled to 319 * and *TCP and *UDP flags can't be enabled together on the same QP.
361 */ 320 */
362 enum mlx5_rx_hash_fields { 321 enum mlx5_rx_hash_fields {
363 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 322 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
364 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 323 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
365 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 324 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
366 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 325 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
367 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 326 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
368 MLX5_RX_HASH_DST_PORT_TCP = 1 << 327 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
369 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 328 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
370 MLX5_RX_HASH_DST_PORT_UDP = 1 << 329 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
371 MLX5_RX_HASH_IPSEC_SPI = 1 << 330 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
372 /* Save bits for future fields */ 331 /* Save bits for future fields */
373 MLX5_RX_HASH_INNER = (1UL 332 MLX5_RX_HASH_INNER = (1UL << 31),
374 }; 333 };
375 334
376 struct mlx5_ib_create_qp_rss { 335 struct mlx5_ib_create_qp_rss {
377 __aligned_u64 rx_hash_fields_mask; /* 336 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
378 __u8 rx_hash_function; /* enum mlx5_rx 337 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
379 __u8 rx_key_len; /* valid only for Toe 338 __u8 rx_key_len; /* valid only for Toeplitz */
380 __u8 reserved[6]; 339 __u8 reserved[6];
381 __u8 rx_hash_key[128]; /* valid only f 340 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
382 __u32 comp_mask; 341 __u32 comp_mask;
383 __u32 flags; 342 __u32 flags;
384 }; 343 };
385 344
386 enum mlx5_ib_create_qp_resp_mask { <<
387 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL <<
388 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL <<
389 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL <<
390 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL <<
391 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_AD <<
392 }; <<
393 <<
394 struct mlx5_ib_create_qp_resp { 345 struct mlx5_ib_create_qp_resp {
395 __u32 bfreg_index; 346 __u32 bfreg_index;
396 __u32 ece_options; !! 347 __u32 reserved;
397 __u32 comp_mask; <<
398 __u32 tirn; <<
399 __u32 tisn; <<
400 __u32 rqn; <<
401 __u32 sqn; <<
402 __u32 reserved1; <<
403 __u64 tir_icm_addr; <<
404 }; 348 };
405 349
406 struct mlx5_ib_alloc_mw { 350 struct mlx5_ib_alloc_mw {
407 __u32 comp_mask; 351 __u32 comp_mask;
408 __u8 num_klms; 352 __u8 num_klms;
409 __u8 reserved1; 353 __u8 reserved1;
410 __u16 reserved2; 354 __u16 reserved2;
411 }; 355 };
412 356
413 enum mlx5_ib_create_wq_mask { 357 enum mlx5_ib_create_wq_mask {
414 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 < 358 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
415 }; 359 };
416 360
417 struct mlx5_ib_create_wq { 361 struct mlx5_ib_create_wq {
418 __aligned_u64 buf_addr; 362 __aligned_u64 buf_addr;
419 __aligned_u64 db_addr; 363 __aligned_u64 db_addr;
420 __u32 rq_wqe_count; 364 __u32 rq_wqe_count;
421 __u32 rq_wqe_shift; 365 __u32 rq_wqe_shift;
422 __u32 user_index; 366 __u32 user_index;
423 __u32 flags; 367 __u32 flags;
424 __u32 comp_mask; 368 __u32 comp_mask;
425 __u32 single_stride_log_num_of_bytes 369 __u32 single_stride_log_num_of_bytes;
426 __u32 single_wqe_log_num_of_strides; 370 __u32 single_wqe_log_num_of_strides;
427 __u32 two_byte_shift_en; 371 __u32 two_byte_shift_en;
428 }; 372 };
429 373
430 struct mlx5_ib_create_ah_resp { 374 struct mlx5_ib_create_ah_resp {
431 __u32 response_length; 375 __u32 response_length;
432 __u8 dmac[ETH_ALEN]; 376 __u8 dmac[ETH_ALEN];
433 __u8 reserved[6]; 377 __u8 reserved[6];
434 }; 378 };
435 379
436 struct mlx5_ib_burst_info { 380 struct mlx5_ib_burst_info {
437 __u32 max_burst_sz; 381 __u32 max_burst_sz;
438 __u16 typical_pkt_sz; 382 __u16 typical_pkt_sz;
439 __u16 reserved; 383 __u16 reserved;
440 }; 384 };
441 385
442 struct mlx5_ib_modify_qp { 386 struct mlx5_ib_modify_qp {
443 __u32 comp_mask; 387 __u32 comp_mask;
444 struct mlx5_ib_burst_info burst_info; 388 struct mlx5_ib_burst_info burst_info;
445 __u32 ece_options !! 389 __u32 reserved;
446 }; 390 };
447 391
448 struct mlx5_ib_modify_qp_resp { 392 struct mlx5_ib_modify_qp_resp {
449 __u32 response_length; 393 __u32 response_length;
450 __u32 dctn; 394 __u32 dctn;
451 __u32 ece_options; <<
452 __u32 reserved; <<
453 }; 395 };
454 396
455 struct mlx5_ib_create_wq_resp { 397 struct mlx5_ib_create_wq_resp {
456 __u32 response_length; 398 __u32 response_length;
457 __u32 reserved; 399 __u32 reserved;
458 }; 400 };
459 401
460 struct mlx5_ib_create_rwq_ind_tbl_resp { 402 struct mlx5_ib_create_rwq_ind_tbl_resp {
461 __u32 response_length; 403 __u32 response_length;
462 __u32 reserved; 404 __u32 reserved;
463 }; 405 };
464 406
465 struct mlx5_ib_modify_wq { 407 struct mlx5_ib_modify_wq {
466 __u32 comp_mask; 408 __u32 comp_mask;
467 __u32 reserved; 409 __u32 reserved;
468 }; 410 };
469 411
470 struct mlx5_ib_clock_info { 412 struct mlx5_ib_clock_info {
471 __u32 sign; 413 __u32 sign;
472 __u32 resv; 414 __u32 resv;
473 __aligned_u64 nsec; 415 __aligned_u64 nsec;
474 __aligned_u64 cycles; 416 __aligned_u64 cycles;
475 __aligned_u64 frac; 417 __aligned_u64 frac;
476 __u32 mult; 418 __u32 mult;
477 __u32 shift; 419 __u32 shift;
478 __aligned_u64 mask; 420 __aligned_u64 mask;
479 __aligned_u64 overflow_period; 421 __aligned_u64 overflow_period;
480 }; 422 };
481 423
482 enum mlx5_ib_mmap_cmd { 424 enum mlx5_ib_mmap_cmd {
483 MLX5_IB_MMAP_REGULAR_PAGE 425 MLX5_IB_MMAP_REGULAR_PAGE = 0,
484 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES 426 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
485 MLX5_IB_MMAP_WC_PAGE 427 MLX5_IB_MMAP_WC_PAGE = 2,
486 MLX5_IB_MMAP_NC_PAGE 428 MLX5_IB_MMAP_NC_PAGE = 3,
487 /* 5 is chosen in order to be compatib 429 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
488 MLX5_IB_MMAP_CORE_CLOCK 430 MLX5_IB_MMAP_CORE_CLOCK = 5,
489 MLX5_IB_MMAP_ALLOC_WC 431 MLX5_IB_MMAP_ALLOC_WC = 6,
490 MLX5_IB_MMAP_CLOCK_INFO 432 MLX5_IB_MMAP_CLOCK_INFO = 7,
491 MLX5_IB_MMAP_DEVICE_MEM 433 MLX5_IB_MMAP_DEVICE_MEM = 8,
492 }; 434 };
493 435
494 enum { 436 enum {
495 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1 437 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
496 }; 438 };
497 439
498 /* Bit indexes for the mlx5_alloc_ucontext_res 440 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
499 enum { 441 enum {
500 MLX5_IB_CLOCK_INFO_V1 = 0 442 MLX5_IB_CLOCK_INFO_V1 = 0,
501 }; 443 };
502 <<
503 struct mlx5_ib_flow_counters_desc { <<
504 __u32 description; <<
505 __u32 index; <<
506 }; <<
507 <<
508 struct mlx5_ib_flow_counters_data { <<
509 RDMA_UAPI_PTR(struct mlx5_ib_flow_coun <<
510 __u32 ncounters; <<
511 __u32 reserved; <<
512 }; <<
513 <<
514 struct mlx5_ib_create_flow { <<
515 __u32 ncounters_data; <<
516 __u32 reserved; <<
517 /* <<
518 * Following are counters data based o <<
519 * entry in the data[] should match a <<
520 * that was pointed by a counters spec <<
521 */ <<
522 struct mlx5_ib_flow_counters_data data <<
523 }; <<
524 <<
525 #endif /* MLX5_ABI_USER_H */ 444 #endif /* MLX5_ABI_USER_H */
526 445
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