1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Lin 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2 /* 2 /*
3 * Copyright (c) 2013-2015, Mellanox Technolog 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * 4 *
5 * This software is available to you under a c 5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed un 6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, ava 7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this sourc 8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below: 9 * OpenIB.org BSD license below:
10 * 10 *
11 * Redistribution and use in source and bi 11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted pro 12 * without modification, are permitted provided that the following
13 * conditions are met: 13 * conditions are met:
14 * 14 *
15 * - Redistributions of source code must 15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of condi 16 * copyright notice, this list of conditions and the following
17 * disclaimer. 17 * disclaimer.
18 * 18 *
19 * - Redistributions in binary form must 19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of condi 20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/ 21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution. 22 * provided with the distribution.
23 * 23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 31 * SOFTWARE.
32 */ 32 */
33 33
34 #ifndef MLX5_ABI_USER_H 34 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H
36 36
37 #include <linux/types.h> 37 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALE 38 #include <linux/if_ether.h> /* For ETH_ALEN. */
39 #include <rdma/ib_user_ioctl_verbs.h> 39 #include <rdma/ib_user_ioctl_verbs.h>
40 #include <rdma/mlx5_user_ioctl_verbs.h> 40 #include <rdma/mlx5_user_ioctl_verbs.h>
41 41
42 enum { 42 enum {
43 MLX5_QP_FLAG_SIGNATURE = 1 << 43 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
44 MLX5_QP_FLAG_SCATTER_CQE = 1 << 44 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
45 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 45 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
46 MLX5_QP_FLAG_BFREG_INDEX = 1 << 46 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
47 MLX5_QP_FLAG_TYPE_DCT = 1 << 47 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
48 MLX5_QP_FLAG_TYPE_DCI = 1 << 48 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
50 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 50 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
51 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 51 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
52 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE 52 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
53 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 53 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
54 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, 54 MLX5_QP_FLAG_DCI_STREAM = 1 << 11,
55 }; 55 };
56 56
57 enum { 57 enum {
58 MLX5_SRQ_FLAG_SIGNATURE = 1 << 58 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
59 }; 59 };
60 60
61 enum { 61 enum {
62 MLX5_WQ_FLAG_SIGNATURE = 1 << 62 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
63 }; 63 };
64 64
65 /* Increment this value if any changes that br 65 /* Increment this value if any changes that break userspace ABI
66 * compatibility are made. 66 * compatibility are made.
67 */ 67 */
68 #define MLX5_IB_UVERBS_ABI_VERSION 1 68 #define MLX5_IB_UVERBS_ABI_VERSION 1
69 69
70 /* Make sure that all structs defined in this 70 /* Make sure that all structs defined in this file remain laid out so
71 * that they pack the same way on 32-bit and 6 71 * that they pack the same way on 32-bit and 64-bit architectures (to
72 * avoid incompatibility between 32-bit usersp 72 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
73 * In particular do not use pointer types -- p 73 * In particular do not use pointer types -- pass pointers in __u64
74 * instead. 74 * instead.
75 */ 75 */
76 76
77 struct mlx5_ib_alloc_ucontext_req { 77 struct mlx5_ib_alloc_ucontext_req {
78 __u32 total_num_bfregs; 78 __u32 total_num_bfregs;
79 __u32 num_low_latency_bfregs; 79 __u32 num_low_latency_bfregs;
80 }; 80 };
81 81
82 enum mlx5_lib_caps { 82 enum mlx5_lib_caps {
83 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 83 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
84 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 84 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
85 }; 85 };
86 86
87 enum mlx5_ib_alloc_uctx_v2_flags { 87 enum mlx5_ib_alloc_uctx_v2_flags {
88 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 88 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
89 }; 89 };
90 struct mlx5_ib_alloc_ucontext_req_v2 { 90 struct mlx5_ib_alloc_ucontext_req_v2 {
91 __u32 total_num_bfregs; 91 __u32 total_num_bfregs;
92 __u32 num_low_latency_bfregs; 92 __u32 num_low_latency_bfregs;
93 __u32 flags; 93 __u32 flags;
94 __u32 comp_mask; 94 __u32 comp_mask;
95 __u8 max_cqe_version; 95 __u8 max_cqe_version;
96 __u8 reserved0; 96 __u8 reserved0;
97 __u16 reserved1; 97 __u16 reserved1;
98 __u32 reserved2; 98 __u32 reserved2;
99 __aligned_u64 lib_caps; 99 __aligned_u64 lib_caps;
100 }; 100 };
101 101
102 enum mlx5_ib_alloc_ucontext_resp_mask { 102 enum mlx5_ib_alloc_ucontext_resp_mask {
103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_ 103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_ 104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE 105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2R 106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_ 107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
108 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_ 108 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5,
109 }; 109 };
110 110
111 enum mlx5_user_cmds_supp_uhw { 111 enum mlx5_user_cmds_supp_uhw {
112 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 112 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
113 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 113 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
114 }; 114 };
115 115
116 /* The eth_min_inline response value is set to 116 /* The eth_min_inline response value is set to off-by-one vs the FW
117 * returned value to allow user-space to deal 117 * returned value to allow user-space to deal with older kernels.
118 */ 118 */
119 enum mlx5_user_inline_mode { 119 enum mlx5_user_inline_mode {
120 MLX5_USER_INLINE_MODE_NA, 120 MLX5_USER_INLINE_MODE_NA,
121 MLX5_USER_INLINE_MODE_NONE, 121 MLX5_USER_INLINE_MODE_NONE,
122 MLX5_USER_INLINE_MODE_L2, 122 MLX5_USER_INLINE_MODE_L2,
123 MLX5_USER_INLINE_MODE_IP, 123 MLX5_USER_INLINE_MODE_IP,
124 MLX5_USER_INLINE_MODE_TCP_UDP, 124 MLX5_USER_INLINE_MODE_TCP_UDP,
125 }; 125 };
126 126
127 enum { 127 enum {
128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
132 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_F 132 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
133 }; 133 };
134 134
135 struct mlx5_ib_alloc_ucontext_resp { 135 struct mlx5_ib_alloc_ucontext_resp {
136 __u32 qp_tab_size; 136 __u32 qp_tab_size;
137 __u32 bf_reg_size; 137 __u32 bf_reg_size;
138 __u32 tot_bfregs; 138 __u32 tot_bfregs;
139 __u32 cache_line_size; 139 __u32 cache_line_size;
140 __u16 max_sq_desc_sz; 140 __u16 max_sq_desc_sz;
141 __u16 max_rq_desc_sz; 141 __u16 max_rq_desc_sz;
142 __u32 max_send_wqebb; 142 __u32 max_send_wqebb;
143 __u32 max_recv_wr; 143 __u32 max_recv_wr;
144 __u32 max_srq_recv_wr; 144 __u32 max_srq_recv_wr;
145 __u16 num_ports; 145 __u16 num_ports;
146 __u16 flow_action_flags; 146 __u16 flow_action_flags;
147 __u32 comp_mask; 147 __u32 comp_mask;
148 __u32 response_length; 148 __u32 response_length;
149 __u8 cqe_version; 149 __u8 cqe_version;
150 __u8 cmds_supp_uhw; 150 __u8 cmds_supp_uhw;
151 __u8 eth_min_inline; 151 __u8 eth_min_inline;
152 __u8 clock_info_versions; 152 __u8 clock_info_versions;
153 __aligned_u64 hca_core_clock_offset; 153 __aligned_u64 hca_core_clock_offset;
154 __u32 log_uar_size; 154 __u32 log_uar_size;
155 __u32 num_uars_per_page; 155 __u32 num_uars_per_page;
156 __u32 num_dyn_bfregs; 156 __u32 num_dyn_bfregs;
157 __u32 dump_fill_mkey; 157 __u32 dump_fill_mkey;
158 }; 158 };
159 159
160 struct mlx5_ib_alloc_pd_resp { 160 struct mlx5_ib_alloc_pd_resp {
161 __u32 pdn; 161 __u32 pdn;
162 }; 162 };
163 163
164 struct mlx5_ib_tso_caps { 164 struct mlx5_ib_tso_caps {
165 __u32 max_tso; /* Maximum tso payload 165 __u32 max_tso; /* Maximum tso payload size in bytes */
166 166
167 /* Corresponding bit will be set if qp 167 /* Corresponding bit will be set if qp type from
168 * 'enum ib_qp_type' is supported, e.g 168 * 'enum ib_qp_type' is supported, e.g.
169 * supported_qpts |= 1 << IB_QPT_UD 169 * supported_qpts |= 1 << IB_QPT_UD
170 */ 170 */
171 __u32 supported_qpts; 171 __u32 supported_qpts;
172 }; 172 };
173 173
174 struct mlx5_ib_rss_caps { 174 struct mlx5_ib_rss_caps {
175 __aligned_u64 rx_hash_fields_mask; /* 175 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
176 __u8 rx_hash_function; /* enum mlx5_rx 176 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
177 __u8 reserved[7]; 177 __u8 reserved[7];
178 }; 178 };
179 179
180 enum mlx5_ib_cqe_comp_res_format { 180 enum mlx5_ib_cqe_comp_res_format {
181 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 181 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
182 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 182 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
183 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 183 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
184 }; 184 };
185 185
186 struct mlx5_ib_cqe_comp_caps { 186 struct mlx5_ib_cqe_comp_caps {
187 __u32 max_num; 187 __u32 max_num;
188 __u32 supported_format; /* enum mlx5_i 188 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
189 }; 189 };
190 190
191 enum mlx5_ib_packet_pacing_cap_flags { 191 enum mlx5_ib_packet_pacing_cap_flags {
192 MLX5_IB_PP_SUPPORT_BURST = 1 << 192 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
193 }; 193 };
194 194
195 struct mlx5_packet_pacing_caps { 195 struct mlx5_packet_pacing_caps {
196 __u32 qp_rate_limit_min; 196 __u32 qp_rate_limit_min;
197 __u32 qp_rate_limit_max; /* In kpbs */ 197 __u32 qp_rate_limit_max; /* In kpbs */
198 198
199 /* Corresponding bit will be set if qp 199 /* Corresponding bit will be set if qp type from
200 * 'enum ib_qp_type' is supported, e.g 200 * 'enum ib_qp_type' is supported, e.g.
201 * supported_qpts |= 1 << IB_QPT_RAW_P 201 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
202 */ 202 */
203 __u32 supported_qpts; 203 __u32 supported_qpts;
204 __u8 cap_flags; /* enum mlx5_ib_packe 204 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
205 __u8 reserved[3]; 205 __u8 reserved[3];
206 }; 206 };
207 207
208 enum mlx5_ib_mpw_caps { 208 enum mlx5_ib_mpw_caps {
209 MPW_RESERVED = 1 << 0, 209 MPW_RESERVED = 1 << 0,
210 MLX5_IB_ALLOW_MPW = 1 << 1, 210 MLX5_IB_ALLOW_MPW = 1 << 1,
211 MLX5_IB_SUPPORT_EMPW = 1 << 2, 211 MLX5_IB_SUPPORT_EMPW = 1 << 2,
212 }; 212 };
213 213
214 enum mlx5_ib_sw_parsing_offloads { 214 enum mlx5_ib_sw_parsing_offloads {
215 MLX5_IB_SW_PARSING = 1 << 0, 215 MLX5_IB_SW_PARSING = 1 << 0,
216 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 216 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
217 MLX5_IB_SW_PARSING_LSO = 1 << 2, 217 MLX5_IB_SW_PARSING_LSO = 1 << 2,
218 }; 218 };
219 219
220 struct mlx5_ib_sw_parsing_caps { 220 struct mlx5_ib_sw_parsing_caps {
221 __u32 sw_parsing_offloads; /* enum mlx 221 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
222 222
223 /* Corresponding bit will be set if qp 223 /* Corresponding bit will be set if qp type from
224 * 'enum ib_qp_type' is supported, e.g 224 * 'enum ib_qp_type' is supported, e.g.
225 * supported_qpts |= 1 << IB_QPT_RAW_P 225 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
226 */ 226 */
227 __u32 supported_qpts; 227 __u32 supported_qpts;
228 }; 228 };
229 229
230 struct mlx5_ib_striding_rq_caps { 230 struct mlx5_ib_striding_rq_caps {
231 __u32 min_single_stride_log_num_of_byt 231 __u32 min_single_stride_log_num_of_bytes;
232 __u32 max_single_stride_log_num_of_byt 232 __u32 max_single_stride_log_num_of_bytes;
233 __u32 min_single_wqe_log_num_of_stride 233 __u32 min_single_wqe_log_num_of_strides;
234 __u32 max_single_wqe_log_num_of_stride 234 __u32 max_single_wqe_log_num_of_strides;
235 235
236 /* Corresponding bit will be set if qp 236 /* Corresponding bit will be set if qp type from
237 * 'enum ib_qp_type' is supported, e.g 237 * 'enum ib_qp_type' is supported, e.g.
238 * supported_qpts |= 1 << IB_QPT_RAW_P 238 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
239 */ 239 */
240 __u32 supported_qpts; 240 __u32 supported_qpts;
241 __u32 reserved; 241 __u32 reserved;
242 }; 242 };
243 243
244 struct mlx5_ib_dci_streams_caps { 244 struct mlx5_ib_dci_streams_caps {
245 __u8 max_log_num_concurent; 245 __u8 max_log_num_concurent;
246 __u8 max_log_num_errored; 246 __u8 max_log_num_errored;
247 }; 247 };
248 248
249 enum mlx5_ib_query_dev_resp_flags { 249 enum mlx5_ib_query_dev_resp_flags {
250 /* Support 128B CQE compression */ 250 /* Support 128B CQE compression */
251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ 251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
252 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_ 252 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
253 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CR 253 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
254 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_ 254 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
255 }; 255 };
256 256
257 enum mlx5_ib_tunnel_offloads { 257 enum mlx5_ib_tunnel_offloads {
258 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 < 258 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
259 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 < 259 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
260 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 < 260 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
262 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 262 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
263 }; 263 };
264 264
265 struct mlx5_ib_query_device_resp { 265 struct mlx5_ib_query_device_resp {
266 __u32 comp_mask; 266 __u32 comp_mask;
267 __u32 response_length; 267 __u32 response_length;
268 struct mlx5_ib_tso_caps tso_caps; 268 struct mlx5_ib_tso_caps tso_caps;
269 struct mlx5_ib_rss_caps rss_caps; 269 struct mlx5_ib_rss_caps rss_caps;
270 struct mlx5_ib_cqe_comp_caps cqe_comp 270 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
271 struct mlx5_packet_pacing_caps packet 271 struct mlx5_packet_pacing_caps packet_pacing_caps;
272 __u32 mlx5_ib_support_multi_pkt_send 272 __u32 mlx5_ib_support_multi_pkt_send_wqes;
273 __u32 flags; /* Use enum mlx5_ib_que 273 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
274 struct mlx5_ib_sw_parsing_caps sw_pars 274 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
275 struct mlx5_ib_striding_rq_caps stridi 275 struct mlx5_ib_striding_rq_caps striding_rq_caps;
276 __u32 tunnel_offloads_caps; /* enum 276 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
277 struct mlx5_ib_dci_streams_caps dci_s 277 struct mlx5_ib_dci_streams_caps dci_streams_caps;
278 __u16 reserved; 278 __u16 reserved;
279 struct mlx5_ib_uapi_reg reg_c0; 279 struct mlx5_ib_uapi_reg reg_c0;
280 }; 280 };
281 281
282 enum mlx5_ib_create_cq_flags { 282 enum mlx5_ib_create_cq_flags {
283 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD 283 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
284 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX 284 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
285 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS 285 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2,
286 }; 286 };
287 287
288 struct mlx5_ib_create_cq { 288 struct mlx5_ib_create_cq {
289 __aligned_u64 buf_addr; 289 __aligned_u64 buf_addr;
290 __aligned_u64 db_addr; 290 __aligned_u64 db_addr;
291 __u32 cqe_size; 291 __u32 cqe_size;
292 __u8 cqe_comp_en; 292 __u8 cqe_comp_en;
293 __u8 cqe_comp_res_format; 293 __u8 cqe_comp_res_format;
294 __u16 flags; 294 __u16 flags;
295 __u16 uar_page_index; 295 __u16 uar_page_index;
296 __u16 reserved0; 296 __u16 reserved0;
297 __u32 reserved1; 297 __u32 reserved1;
298 }; 298 };
299 299
300 struct mlx5_ib_create_cq_resp { 300 struct mlx5_ib_create_cq_resp {
301 __u32 cqn; 301 __u32 cqn;
302 __u32 reserved; 302 __u32 reserved;
303 }; 303 };
304 304
305 struct mlx5_ib_resize_cq { 305 struct mlx5_ib_resize_cq {
306 __aligned_u64 buf_addr; 306 __aligned_u64 buf_addr;
307 __u16 cqe_size; 307 __u16 cqe_size;
308 __u16 reserved0; 308 __u16 reserved0;
309 __u32 reserved1; 309 __u32 reserved1;
310 }; 310 };
311 311
312 struct mlx5_ib_create_srq { 312 struct mlx5_ib_create_srq {
313 __aligned_u64 buf_addr; 313 __aligned_u64 buf_addr;
314 __aligned_u64 db_addr; 314 __aligned_u64 db_addr;
315 __u32 flags; 315 __u32 flags;
316 __u32 reserved0; /* explicit padding 316 __u32 reserved0; /* explicit padding (optional on i386) */
317 __u32 uidx; 317 __u32 uidx;
318 __u32 reserved1; 318 __u32 reserved1;
319 }; 319 };
320 320
321 struct mlx5_ib_create_srq_resp { 321 struct mlx5_ib_create_srq_resp {
322 __u32 srqn; 322 __u32 srqn;
323 __u32 reserved; 323 __u32 reserved;
324 }; 324 };
325 325
326 struct mlx5_ib_create_qp_dci_streams { 326 struct mlx5_ib_create_qp_dci_streams {
327 __u8 log_num_concurent; 327 __u8 log_num_concurent;
328 __u8 log_num_errored; 328 __u8 log_num_errored;
329 }; 329 };
330 330
331 struct mlx5_ib_create_qp { 331 struct mlx5_ib_create_qp {
332 __aligned_u64 buf_addr; 332 __aligned_u64 buf_addr;
333 __aligned_u64 db_addr; 333 __aligned_u64 db_addr;
334 __u32 sq_wqe_count; 334 __u32 sq_wqe_count;
335 __u32 rq_wqe_count; 335 __u32 rq_wqe_count;
336 __u32 rq_wqe_shift; 336 __u32 rq_wqe_shift;
337 __u32 flags; 337 __u32 flags;
338 __u32 uidx; 338 __u32 uidx;
339 __u32 bfreg_index; 339 __u32 bfreg_index;
340 union { 340 union {
341 __aligned_u64 sq_buf_addr; 341 __aligned_u64 sq_buf_addr;
342 __aligned_u64 access_key; 342 __aligned_u64 access_key;
343 }; 343 };
344 __u32 ece_options; 344 __u32 ece_options;
345 struct mlx5_ib_create_qp_dci_streams 345 struct mlx5_ib_create_qp_dci_streams dci_streams;
346 __u16 reserved; 346 __u16 reserved;
347 }; 347 };
348 348
349 /* RX Hash function flags */ 349 /* RX Hash function flags */
350 enum mlx5_rx_hash_function_flags { 350 enum mlx5_rx_hash_function_flags {
351 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 351 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
352 }; 352 };
353 353
354 /* 354 /*
355 * RX Hash flags, these flags allows to set wh 355 * RX Hash flags, these flags allows to set which incoming packet's field should
356 * participates in RX Hash. Each flag represen 356 * participates in RX Hash. Each flag represent certain packet's field,
357 * when the flag is set the field that is repr 357 * when the flag is set the field that is represented by the flag will
358 * participate in RX Hash calculation. 358 * participate in RX Hash calculation.
359 * Note: *IPV4 and *IPV6 flags can't be enable 359 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
360 * and *TCP and *UDP flags can't be enabled to 360 * and *TCP and *UDP flags can't be enabled together on the same QP.
361 */ 361 */
362 enum mlx5_rx_hash_fields { 362 enum mlx5_rx_hash_fields {
363 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 363 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
364 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 364 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
365 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 365 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
366 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 366 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
367 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 367 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
368 MLX5_RX_HASH_DST_PORT_TCP = 1 << 368 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
369 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 369 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
370 MLX5_RX_HASH_DST_PORT_UDP = 1 << 370 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
371 MLX5_RX_HASH_IPSEC_SPI = 1 << 371 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
372 /* Save bits for future fields */ 372 /* Save bits for future fields */
373 MLX5_RX_HASH_INNER = (1UL 373 MLX5_RX_HASH_INNER = (1UL << 31),
374 }; 374 };
375 375
376 struct mlx5_ib_create_qp_rss { 376 struct mlx5_ib_create_qp_rss {
377 __aligned_u64 rx_hash_fields_mask; /* 377 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
378 __u8 rx_hash_function; /* enum mlx5_rx 378 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
379 __u8 rx_key_len; /* valid only for Toe 379 __u8 rx_key_len; /* valid only for Toeplitz */
380 __u8 reserved[6]; 380 __u8 reserved[6];
381 __u8 rx_hash_key[128]; /* valid only f 381 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
382 __u32 comp_mask; 382 __u32 comp_mask;
383 __u32 flags; 383 __u32 flags;
384 }; 384 };
385 385
386 enum mlx5_ib_create_qp_resp_mask { 386 enum mlx5_ib_create_qp_resp_mask {
387 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL 387 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
388 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL 388 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
389 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL 389 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
390 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL 390 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
391 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_AD 391 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
392 }; 392 };
393 393
394 struct mlx5_ib_create_qp_resp { 394 struct mlx5_ib_create_qp_resp {
395 __u32 bfreg_index; 395 __u32 bfreg_index;
396 __u32 ece_options; 396 __u32 ece_options;
397 __u32 comp_mask; 397 __u32 comp_mask;
398 __u32 tirn; 398 __u32 tirn;
399 __u32 tisn; 399 __u32 tisn;
400 __u32 rqn; 400 __u32 rqn;
401 __u32 sqn; 401 __u32 sqn;
402 __u32 reserved1; 402 __u32 reserved1;
403 __u64 tir_icm_addr; 403 __u64 tir_icm_addr;
404 }; 404 };
405 405
406 struct mlx5_ib_alloc_mw { 406 struct mlx5_ib_alloc_mw {
407 __u32 comp_mask; 407 __u32 comp_mask;
408 __u8 num_klms; 408 __u8 num_klms;
409 __u8 reserved1; 409 __u8 reserved1;
410 __u16 reserved2; 410 __u16 reserved2;
411 }; 411 };
412 412
413 enum mlx5_ib_create_wq_mask { 413 enum mlx5_ib_create_wq_mask {
414 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 < 414 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
415 }; 415 };
416 416
417 struct mlx5_ib_create_wq { 417 struct mlx5_ib_create_wq {
418 __aligned_u64 buf_addr; 418 __aligned_u64 buf_addr;
419 __aligned_u64 db_addr; 419 __aligned_u64 db_addr;
420 __u32 rq_wqe_count; 420 __u32 rq_wqe_count;
421 __u32 rq_wqe_shift; 421 __u32 rq_wqe_shift;
422 __u32 user_index; 422 __u32 user_index;
423 __u32 flags; 423 __u32 flags;
424 __u32 comp_mask; 424 __u32 comp_mask;
425 __u32 single_stride_log_num_of_bytes 425 __u32 single_stride_log_num_of_bytes;
426 __u32 single_wqe_log_num_of_strides; 426 __u32 single_wqe_log_num_of_strides;
427 __u32 two_byte_shift_en; 427 __u32 two_byte_shift_en;
428 }; 428 };
429 429
430 struct mlx5_ib_create_ah_resp { 430 struct mlx5_ib_create_ah_resp {
431 __u32 response_length; 431 __u32 response_length;
432 __u8 dmac[ETH_ALEN]; 432 __u8 dmac[ETH_ALEN];
433 __u8 reserved[6]; 433 __u8 reserved[6];
434 }; 434 };
435 435
436 struct mlx5_ib_burst_info { 436 struct mlx5_ib_burst_info {
437 __u32 max_burst_sz; 437 __u32 max_burst_sz;
438 __u16 typical_pkt_sz; 438 __u16 typical_pkt_sz;
439 __u16 reserved; 439 __u16 reserved;
440 }; 440 };
441 441
442 struct mlx5_ib_modify_qp { 442 struct mlx5_ib_modify_qp {
443 __u32 comp_mask; 443 __u32 comp_mask;
444 struct mlx5_ib_burst_info burst_info; 444 struct mlx5_ib_burst_info burst_info;
445 __u32 ece_options 445 __u32 ece_options;
446 }; 446 };
447 447
448 struct mlx5_ib_modify_qp_resp { 448 struct mlx5_ib_modify_qp_resp {
449 __u32 response_length; 449 __u32 response_length;
450 __u32 dctn; 450 __u32 dctn;
451 __u32 ece_options; 451 __u32 ece_options;
452 __u32 reserved; 452 __u32 reserved;
453 }; 453 };
454 454
455 struct mlx5_ib_create_wq_resp { 455 struct mlx5_ib_create_wq_resp {
456 __u32 response_length; 456 __u32 response_length;
457 __u32 reserved; 457 __u32 reserved;
458 }; 458 };
459 459
460 struct mlx5_ib_create_rwq_ind_tbl_resp { 460 struct mlx5_ib_create_rwq_ind_tbl_resp {
461 __u32 response_length; 461 __u32 response_length;
462 __u32 reserved; 462 __u32 reserved;
463 }; 463 };
464 464
465 struct mlx5_ib_modify_wq { 465 struct mlx5_ib_modify_wq {
466 __u32 comp_mask; 466 __u32 comp_mask;
467 __u32 reserved; 467 __u32 reserved;
468 }; 468 };
469 469
470 struct mlx5_ib_clock_info { 470 struct mlx5_ib_clock_info {
471 __u32 sign; 471 __u32 sign;
472 __u32 resv; 472 __u32 resv;
473 __aligned_u64 nsec; 473 __aligned_u64 nsec;
474 __aligned_u64 cycles; 474 __aligned_u64 cycles;
475 __aligned_u64 frac; 475 __aligned_u64 frac;
476 __u32 mult; 476 __u32 mult;
477 __u32 shift; 477 __u32 shift;
478 __aligned_u64 mask; 478 __aligned_u64 mask;
479 __aligned_u64 overflow_period; 479 __aligned_u64 overflow_period;
480 }; 480 };
481 481
482 enum mlx5_ib_mmap_cmd { 482 enum mlx5_ib_mmap_cmd {
483 MLX5_IB_MMAP_REGULAR_PAGE 483 MLX5_IB_MMAP_REGULAR_PAGE = 0,
484 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES 484 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
485 MLX5_IB_MMAP_WC_PAGE 485 MLX5_IB_MMAP_WC_PAGE = 2,
486 MLX5_IB_MMAP_NC_PAGE 486 MLX5_IB_MMAP_NC_PAGE = 3,
487 /* 5 is chosen in order to be compatib 487 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
488 MLX5_IB_MMAP_CORE_CLOCK 488 MLX5_IB_MMAP_CORE_CLOCK = 5,
489 MLX5_IB_MMAP_ALLOC_WC 489 MLX5_IB_MMAP_ALLOC_WC = 6,
490 MLX5_IB_MMAP_CLOCK_INFO 490 MLX5_IB_MMAP_CLOCK_INFO = 7,
491 MLX5_IB_MMAP_DEVICE_MEM 491 MLX5_IB_MMAP_DEVICE_MEM = 8,
492 }; 492 };
493 493
494 enum { 494 enum {
495 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1 495 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
496 }; 496 };
497 497
498 /* Bit indexes for the mlx5_alloc_ucontext_res 498 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
499 enum { 499 enum {
500 MLX5_IB_CLOCK_INFO_V1 = 0 500 MLX5_IB_CLOCK_INFO_V1 = 0,
501 }; 501 };
502 502
503 struct mlx5_ib_flow_counters_desc { 503 struct mlx5_ib_flow_counters_desc {
504 __u32 description; 504 __u32 description;
505 __u32 index; 505 __u32 index;
506 }; 506 };
507 507
508 struct mlx5_ib_flow_counters_data { 508 struct mlx5_ib_flow_counters_data {
509 RDMA_UAPI_PTR(struct mlx5_ib_flow_coun 509 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
510 __u32 ncounters; 510 __u32 ncounters;
511 __u32 reserved; 511 __u32 reserved;
512 }; 512 };
513 513
514 struct mlx5_ib_create_flow { 514 struct mlx5_ib_create_flow {
515 __u32 ncounters_data; 515 __u32 ncounters_data;
516 __u32 reserved; 516 __u32 reserved;
517 /* 517 /*
518 * Following are counters data based o 518 * Following are counters data based on ncounters_data, each
519 * entry in the data[] should match a 519 * entry in the data[] should match a corresponding counter object
520 * that was pointed by a counters spec 520 * that was pointed by a counters spec upon the flow creation
521 */ 521 */
522 struct mlx5_ib_flow_counters_data data 522 struct mlx5_ib_flow_counters_data data[];
523 }; 523 };
524 524
525 #endif /* MLX5_ABI_USER_H */ 525 #endif /* MLX5_ABI_USER_H */
526 526
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