1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Lin 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* QLogic qedr NIC Driver 2 /* QLogic qedr NIC Driver 3 * Copyright (c) 2015-2016 QLogic Corporation 3 * Copyright (c) 2015-2016 QLogic Corporation 4 * 4 * 5 * This software is available to you under a c 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed un 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, ava 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this sourc 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 9 * OpenIB.org BSD license below: 10 * 10 * 11 * Redistribution and use in source and bi 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted pro 12 * without modification, are permitted provided that the following 13 * conditions are met: 13 * conditions are met: 14 * 14 * 15 * - Redistributions of source code must 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of condi 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 17 * disclaimer. 18 * 18 * 19 * - Redistributions in binary form must 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of condi 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and 21 * disclaimer in the documentation and /or other materials 22 * provided with the distribution. 22 * provided with the distribution. 23 * 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 31 * SOFTWARE. 32 */ 32 */ 33 #ifndef __QEDR_USER_H__ 33 #ifndef __QEDR_USER_H__ 34 #define __QEDR_USER_H__ 34 #define __QEDR_USER_H__ 35 35 36 #include <linux/types.h> 36 #include <linux/types.h> 37 37 38 #define QEDR_ABI_VERSION (8) 38 #define QEDR_ABI_VERSION (8) 39 39 40 /* user kernel communication data structures. 40 /* user kernel communication data structures. */ 41 enum qedr_alloc_ucontext_flags { << 42 QEDR_ALLOC_UCTX_EDPM_MODE = 1 << << 43 QEDR_ALLOC_UCTX_DB_REC = 1 << << 44 QEDR_SUPPORT_DPM_SIZES = 1 << << 45 }; << 46 << 47 struct qedr_alloc_ucontext_req { << 48 __u32 context_flags; << 49 __u32 reserved; << 50 }; << 51 << 52 #define QEDR_LDPM_MAX_SIZE (8192) << 53 #define QEDR_EDPM_TRANS_SIZE (64) << 54 #define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_ << 55 << 56 enum qedr_rdma_dpm_type { << 57 QEDR_DPM_TYPE_NONE = 0, << 58 QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << << 59 QEDR_DPM_TYPE_ROCE_LEGACY = 1 << << 60 QEDR_DPM_TYPE_IWARP_LEGACY = 1 << << 61 QEDR_DPM_TYPE_ROCE_EDPM_MODE = 1 << << 62 QEDR_DPM_SIZES_SET = 1 << << 63 }; << 64 41 65 struct qedr_alloc_ucontext_resp { 42 struct qedr_alloc_ucontext_resp { 66 __aligned_u64 db_pa; 43 __aligned_u64 db_pa; 67 __u32 db_size; 44 __u32 db_size; 68 45 69 __u32 max_send_wr; 46 __u32 max_send_wr; 70 __u32 max_recv_wr; 47 __u32 max_recv_wr; 71 __u32 max_srq_wr; 48 __u32 max_srq_wr; 72 __u32 sges_per_send_wr; 49 __u32 sges_per_send_wr; 73 __u32 sges_per_recv_wr; 50 __u32 sges_per_recv_wr; 74 __u32 sges_per_srq_wr; 51 __u32 sges_per_srq_wr; 75 __u32 max_cqes; 52 __u32 max_cqes; 76 __u8 dpm_flags; !! 53 __u8 dpm_enabled; 77 __u8 wids_enabled; 54 __u8 wids_enabled; 78 __u16 wid_count; 55 __u16 wid_count; 79 __u16 ldpm_limit_size; !! 56 __u32 reserved; 80 __u8 edpm_trans_size; << 81 __u8 reserved; << 82 __u16 edpm_limit_size; << 83 __u8 padding[6]; << 84 }; 57 }; 85 58 86 struct qedr_alloc_pd_ureq { 59 struct qedr_alloc_pd_ureq { 87 __aligned_u64 rsvd1; 60 __aligned_u64 rsvd1; 88 }; 61 }; 89 62 90 struct qedr_alloc_pd_uresp { 63 struct qedr_alloc_pd_uresp { 91 __u32 pd_id; 64 __u32 pd_id; 92 __u32 reserved; 65 __u32 reserved; 93 }; 66 }; 94 67 95 struct qedr_create_cq_ureq { 68 struct qedr_create_cq_ureq { 96 __aligned_u64 addr; 69 __aligned_u64 addr; 97 __aligned_u64 len; 70 __aligned_u64 len; 98 }; 71 }; 99 72 100 struct qedr_create_cq_uresp { 73 struct qedr_create_cq_uresp { 101 __u32 db_offset; 74 __u32 db_offset; 102 __u16 icid; 75 __u16 icid; 103 __u16 reserved; 76 __u16 reserved; 104 __aligned_u64 db_rec_addr; << 105 }; 77 }; 106 78 107 struct qedr_create_qp_ureq { 79 struct qedr_create_qp_ureq { 108 __u32 qp_handle_hi; 80 __u32 qp_handle_hi; 109 __u32 qp_handle_lo; 81 __u32 qp_handle_lo; 110 82 111 /* SQ */ 83 /* SQ */ 112 /* user space virtual address of SQ bu 84 /* user space virtual address of SQ buffer */ 113 __aligned_u64 sq_addr; 85 __aligned_u64 sq_addr; 114 86 115 /* length of SQ buffer */ 87 /* length of SQ buffer */ 116 __aligned_u64 sq_len; 88 __aligned_u64 sq_len; 117 89 118 /* RQ */ 90 /* RQ */ 119 /* user space virtual address of RQ bu 91 /* user space virtual address of RQ buffer */ 120 __aligned_u64 rq_addr; 92 __aligned_u64 rq_addr; 121 93 122 /* length of RQ buffer */ 94 /* length of RQ buffer */ 123 __aligned_u64 rq_len; 95 __aligned_u64 rq_len; 124 }; 96 }; 125 97 126 struct qedr_create_qp_uresp { 98 struct qedr_create_qp_uresp { 127 __u32 qp_id; 99 __u32 qp_id; 128 __u32 atomic_supported; 100 __u32 atomic_supported; 129 101 130 /* SQ */ 102 /* SQ */ 131 __u32 sq_db_offset; 103 __u32 sq_db_offset; 132 __u16 sq_icid; 104 __u16 sq_icid; 133 105 134 /* RQ */ 106 /* RQ */ 135 __u32 rq_db_offset; 107 __u32 rq_db_offset; 136 __u16 rq_icid; 108 __u16 rq_icid; 137 109 138 __u32 rq_db2_offset; 110 __u32 rq_db2_offset; 139 __u32 reserved; 111 __u32 reserved; 140 << 141 /* address of SQ doorbell recovery use << 142 __aligned_u64 sq_db_rec_addr; << 143 << 144 /* address of RQ doorbell recovery use << 145 __aligned_u64 rq_db_rec_addr; << 146 << 147 }; 112 }; 148 113 149 struct qedr_create_srq_ureq { 114 struct qedr_create_srq_ureq { 150 /* user space virtual address of produ 115 /* user space virtual address of producer pair */ 151 __aligned_u64 prod_pair_addr; 116 __aligned_u64 prod_pair_addr; 152 117 153 /* user space virtual address of SRQ b 118 /* user space virtual address of SRQ buffer */ 154 __aligned_u64 srq_addr; 119 __aligned_u64 srq_addr; 155 120 156 /* length of SRQ buffer */ 121 /* length of SRQ buffer */ 157 __aligned_u64 srq_len; 122 __aligned_u64 srq_len; 158 }; 123 }; 159 124 160 struct qedr_create_srq_uresp { 125 struct qedr_create_srq_uresp { 161 __u16 srq_id; 126 __u16 srq_id; 162 __u16 reserved0; 127 __u16 reserved0; 163 __u32 reserved1; 128 __u32 reserved1; 164 }; << 165 << 166 /* doorbell recovery entry allocated and popul << 167 * entities and mapped to kernel. Kernel uses << 168 * information with doorbell drop recovery mec << 169 */ << 170 struct qedr_user_db_rec { << 171 __aligned_u64 db_data; /* doorbell dat << 172 }; 129 }; 173 130 174 #endif /* __QEDR_USER_H__ */ 131 #endif /* __QEDR_USER_H__ */ 175 132
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