1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Universal Flash Storage Host controller dri 3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Softw 4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * 5 *
6 * Authors: 6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung 7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.c 8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */ 9 */
10 10
11 #ifndef _UFS_H 11 #ifndef _UFS_H
12 #define _UFS_H 12 #define _UFS_H
13 13
14 #include <linux/bitops.h> !! 14 #include <linux/mutex.h>
15 #include <linux/types.h> 15 #include <linux/types.h>
16 #include <uapi/scsi/scsi_bsg_ufs.h> 16 #include <uapi/scsi/scsi_bsg_ufs.h>
17 #include <linux/time64.h> <<
18 <<
19 /* <<
20 * Using static_assert() is not allowed in UAP <<
21 * in this header file of the size of struct u <<
22 */ <<
23 static_assert(sizeof(struct utp_upiu_header) = <<
24 17
25 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(stru 18 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
26 #define QUERY_DESC_MAX_SIZE 255 19 #define QUERY_DESC_MAX_SIZE 255
27 #define QUERY_DESC_MIN_SIZE 2 20 #define QUERY_DESC_MIN_SIZE 2
28 #define QUERY_DESC_HDR_SIZE 2 21 #define QUERY_DESC_HDR_SIZE 2
29 #define QUERY_OSF_SIZE (GENERAL_UPI 22 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
30 (sizeo 23 (sizeof(struct utp_upiu_header)))
31 #define UFS_SENSE_SIZE 18 24 #define UFS_SENSE_SIZE 18
32 25
>> 26 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
>> 27 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
>> 28 (byte1 << 8) | (byte0))
33 /* 29 /*
34 * UFS device may have standard LUs and LUN id 30 * UFS device may have standard LUs and LUN id could be from 0x00 to
35 * 0x7F. Standard LUs use "Peripheral Device A 31 * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
36 * UFS device may also have the Well Known LUs 32 * UFS device may also have the Well Known LUs (also referred as W-LU)
37 * which again could be from 0x00 to 0x7F. For 33 * which again could be from 0x00 to 0x7F. For W-LUs, device only use
38 * the "Extended Addressing Format" which mean 34 * the "Extended Addressing Format" which means the W-LUNs would be
39 * from 0xc100 (SCSI_W_LUN_BASE) onwards. 35 * from 0xc100 (SCSI_W_LUN_BASE) onwards.
40 * This means max. LUN number reported from UF 36 * This means max. LUN number reported from UFS device could be 0xC17F.
41 */ 37 */
42 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F 38 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
43 #define UFS_MAX_LUNS (SCSI_W_LUN_BA 39 #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
44 #define UFS_UPIU_WLUN_ID (1 << 7) 40 #define UFS_UPIU_WLUN_ID (1 << 7)
>> 41 #define UFS_RPMB_UNIT 0xC4
45 42
46 /* WriteBooster buffer is available only for t 43 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
47 #define UFS_UPIU_MAX_WB_LUN_ID 8 44 #define UFS_UPIU_MAX_WB_LUN_ID 8
48 45
49 /* 46 /*
50 * WriteBooster buffer lifetime has a limit se 47 * WriteBooster buffer lifetime has a limit setted by vendor.
51 * If it is over the limit, WriteBooster featu 48 * If it is over the limit, WriteBooster feature will be disabled.
52 */ 49 */
53 #define UFS_WB_EXCEED_LIFETIME 0x0B 50 #define UFS_WB_EXCEED_LIFETIME 0x0B
54 51
55 /* <<
56 * In UFS Spec, the Extra Header Segment (EHS) <<
57 */ <<
58 #define EHS_OFFSET_IN_RESPONSE 32 <<
59 <<
60 /* Well known logical unit id in LUN field of 52 /* Well known logical unit id in LUN field of UPIU */
61 enum { 53 enum {
62 UFS_UPIU_REPORT_LUNS_WLUN = 0x81 54 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
63 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0 55 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
64 UFS_UPIU_BOOT_WLUN = 0xB0 56 UFS_UPIU_BOOT_WLUN = 0xB0,
65 UFS_UPIU_RPMB_WLUN = 0xC4 57 UFS_UPIU_RPMB_WLUN = 0xC4,
66 }; 58 };
67 59
68 /* 60 /*
69 * UFS Protocol Information Unit related defin 61 * UFS Protocol Information Unit related definitions
70 */ 62 */
71 63
72 /* Task management functions */ 64 /* Task management functions */
73 enum { 65 enum {
74 UFS_ABORT_TASK = 0x01, 66 UFS_ABORT_TASK = 0x01,
75 UFS_ABORT_TASK_SET = 0x02, 67 UFS_ABORT_TASK_SET = 0x02,
76 UFS_CLEAR_TASK_SET = 0x04, 68 UFS_CLEAR_TASK_SET = 0x04,
77 UFS_LOGICAL_RESET = 0x08, 69 UFS_LOGICAL_RESET = 0x08,
78 UFS_QUERY_TASK = 0x80, 70 UFS_QUERY_TASK = 0x80,
79 UFS_QUERY_TASK_SET = 0x81, 71 UFS_QUERY_TASK_SET = 0x81,
80 }; 72 };
81 73
82 /* UTP UPIU Transaction Codes Initiator to Tar 74 /* UTP UPIU Transaction Codes Initiator to Target */
83 enum upiu_request_transaction { !! 75 enum {
84 UPIU_TRANSACTION_NOP_OUT = 0x00 76 UPIU_TRANSACTION_NOP_OUT = 0x00,
85 UPIU_TRANSACTION_COMMAND = 0x01 77 UPIU_TRANSACTION_COMMAND = 0x01,
86 UPIU_TRANSACTION_DATA_OUT = 0x02 78 UPIU_TRANSACTION_DATA_OUT = 0x02,
87 UPIU_TRANSACTION_TASK_REQ = 0x04 79 UPIU_TRANSACTION_TASK_REQ = 0x04,
88 UPIU_TRANSACTION_QUERY_REQ = 0x16 80 UPIU_TRANSACTION_QUERY_REQ = 0x16,
89 }; 81 };
90 82
91 /* UTP UPIU Transaction Codes Target to Initia 83 /* UTP UPIU Transaction Codes Target to Initiator */
92 enum upiu_response_transaction { !! 84 enum {
93 UPIU_TRANSACTION_NOP_IN = 0x20 85 UPIU_TRANSACTION_NOP_IN = 0x20,
94 UPIU_TRANSACTION_RESPONSE = 0x21 86 UPIU_TRANSACTION_RESPONSE = 0x21,
95 UPIU_TRANSACTION_DATA_IN = 0x22 87 UPIU_TRANSACTION_DATA_IN = 0x22,
96 UPIU_TRANSACTION_TASK_RSP = 0x24 88 UPIU_TRANSACTION_TASK_RSP = 0x24,
97 UPIU_TRANSACTION_READY_XFER = 0x31 89 UPIU_TRANSACTION_READY_XFER = 0x31,
98 UPIU_TRANSACTION_QUERY_RSP = 0x36 90 UPIU_TRANSACTION_QUERY_RSP = 0x36,
99 UPIU_TRANSACTION_REJECT_UPIU = 0x3F 91 UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
100 }; 92 };
101 93
102 /* UPIU Read/Write flags. See also table "UPIU !! 94 /* UPIU Read/Write flags */
103 enum { 95 enum {
104 UPIU_CMD_FLAGS_NONE = 0x00, 96 UPIU_CMD_FLAGS_NONE = 0x00,
105 UPIU_CMD_FLAGS_CP = 0x04, <<
106 UPIU_CMD_FLAGS_WRITE = 0x20, 97 UPIU_CMD_FLAGS_WRITE = 0x20,
107 UPIU_CMD_FLAGS_READ = 0x40, 98 UPIU_CMD_FLAGS_READ = 0x40,
108 }; 99 };
109 100
110 /* UPIU response flags */ <<
111 enum { <<
112 UPIU_RSP_FLAG_UNDERFLOW = 0x20, <<
113 UPIU_RSP_FLAG_OVERFLOW = 0x40, <<
114 }; <<
115 <<
116 /* UPIU Task Attributes */ 101 /* UPIU Task Attributes */
117 enum { 102 enum {
118 UPIU_TASK_ATTR_SIMPLE = 0x00, 103 UPIU_TASK_ATTR_SIMPLE = 0x00,
119 UPIU_TASK_ATTR_ORDERED = 0x01, 104 UPIU_TASK_ATTR_ORDERED = 0x01,
120 UPIU_TASK_ATTR_HEADQ = 0x02, 105 UPIU_TASK_ATTR_HEADQ = 0x02,
121 UPIU_TASK_ATTR_ACA = 0x03, 106 UPIU_TASK_ATTR_ACA = 0x03,
122 }; 107 };
123 108
124 /* UPIU Query request function */ 109 /* UPIU Query request function */
125 enum { 110 enum {
126 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST 111 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
127 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST 112 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
128 }; 113 };
129 114
130 /* Flag idn for Query Requests*/ 115 /* Flag idn for Query Requests*/
131 enum flag_idn { 116 enum flag_idn {
132 QUERY_FLAG_IDN_FDEVICEINIT 117 QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
133 QUERY_FLAG_IDN_PERMANENT_WPE 118 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
134 QUERY_FLAG_IDN_PWR_ON_WPE 119 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
135 QUERY_FLAG_IDN_BKOPS_EN 120 QUERY_FLAG_IDN_BKOPS_EN = 0x04,
136 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE 121 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
137 QUERY_FLAG_IDN_PURGE_ENABLE 122 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
138 QUERY_FLAG_IDN_RESERVED2 123 QUERY_FLAG_IDN_RESERVED2 = 0x07,
139 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL 124 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
140 QUERY_FLAG_IDN_BUSY_RTC 125 QUERY_FLAG_IDN_BUSY_RTC = 0x09,
141 QUERY_FLAG_IDN_RESERVED3 126 QUERY_FLAG_IDN_RESERVED3 = 0x0A,
142 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_ 127 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
143 QUERY_FLAG_IDN_WB_EN 128 QUERY_FLAG_IDN_WB_EN = 0x0E,
144 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN 129 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
145 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HI 130 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
146 QUERY_FLAG_IDN_HPB_RESET 131 QUERY_FLAG_IDN_HPB_RESET = 0x11,
147 QUERY_FLAG_IDN_HPB_EN 132 QUERY_FLAG_IDN_HPB_EN = 0x12,
148 }; 133 };
149 134
150 /* Attribute idn for Query requests */ 135 /* Attribute idn for Query requests */
151 enum attr_idn { 136 enum attr_idn {
152 QUERY_ATTR_IDN_BOOT_LU_EN 137 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
153 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD 138 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
154 QUERY_ATTR_IDN_POWER_MODE 139 QUERY_ATTR_IDN_POWER_MODE = 0x02,
155 QUERY_ATTR_IDN_ACTIVE_ICC_LVL 140 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
156 QUERY_ATTR_IDN_OOO_DATA_EN 141 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
157 QUERY_ATTR_IDN_BKOPS_STATUS 142 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
158 QUERY_ATTR_IDN_PURGE_STATUS 143 QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
159 QUERY_ATTR_IDN_MAX_DATA_IN 144 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
160 QUERY_ATTR_IDN_MAX_DATA_OUT 145 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
161 QUERY_ATTR_IDN_DYN_CAP_NEEDED 146 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
162 QUERY_ATTR_IDN_REF_CLK_FREQ 147 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
163 QUERY_ATTR_IDN_CONF_DESC_LOCK 148 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
164 QUERY_ATTR_IDN_MAX_NUM_OF_RTT 149 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
165 QUERY_ATTR_IDN_EE_CONTROL 150 QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
166 QUERY_ATTR_IDN_EE_STATUS 151 QUERY_ATTR_IDN_EE_STATUS = 0x0E,
167 QUERY_ATTR_IDN_SECONDS_PASSED 152 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
168 QUERY_ATTR_IDN_CNTX_CONF 153 QUERY_ATTR_IDN_CNTX_CONF = 0x10,
169 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM 154 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
170 QUERY_ATTR_IDN_RESERVED2 155 QUERY_ATTR_IDN_RESERVED2 = 0x12,
171 QUERY_ATTR_IDN_RESERVED3 156 QUERY_ATTR_IDN_RESERVED3 = 0x13,
172 QUERY_ATTR_IDN_FFU_STATUS 157 QUERY_ATTR_IDN_FFU_STATUS = 0x14,
173 QUERY_ATTR_IDN_PSA_STATE 158 QUERY_ATTR_IDN_PSA_STATE = 0x15,
174 QUERY_ATTR_IDN_PSA_DATA_SIZE 159 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
175 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIM 160 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
176 QUERY_ATTR_IDN_CASE_ROUGH_TEMP 161 QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
177 QUERY_ATTR_IDN_HIGH_TEMP_BOUND 162 QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
178 QUERY_ATTR_IDN_LOW_TEMP_BOUND 163 QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
179 QUERY_ATTR_IDN_WB_FLUSH_STATUS 164 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
180 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE 165 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
181 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST 166 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
182 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE 167 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
183 QUERY_ATTR_IDN_EXT_IID_EN <<
184 QUERY_ATTR_IDN_TIMESTAMP <<
185 }; 168 };
186 169
187 /* Descriptor idn for Query requests */ 170 /* Descriptor idn for Query requests */
188 enum desc_idn { 171 enum desc_idn {
189 QUERY_DESC_IDN_DEVICE = 0x0, 172 QUERY_DESC_IDN_DEVICE = 0x0,
190 QUERY_DESC_IDN_CONFIGURATION = 0x1, 173 QUERY_DESC_IDN_CONFIGURATION = 0x1,
191 QUERY_DESC_IDN_UNIT = 0x2, 174 QUERY_DESC_IDN_UNIT = 0x2,
192 QUERY_DESC_IDN_RFU_0 = 0x3, 175 QUERY_DESC_IDN_RFU_0 = 0x3,
193 QUERY_DESC_IDN_INTERCONNECT = 0x4, 176 QUERY_DESC_IDN_INTERCONNECT = 0x4,
194 QUERY_DESC_IDN_STRING = 0x5, 177 QUERY_DESC_IDN_STRING = 0x5,
195 QUERY_DESC_IDN_RFU_1 = 0x6, 178 QUERY_DESC_IDN_RFU_1 = 0x6,
196 QUERY_DESC_IDN_GEOMETRY = 0x7, 179 QUERY_DESC_IDN_GEOMETRY = 0x7,
197 QUERY_DESC_IDN_POWER = 0x8, 180 QUERY_DESC_IDN_POWER = 0x8,
198 QUERY_DESC_IDN_HEALTH = 0x9, 181 QUERY_DESC_IDN_HEALTH = 0x9,
199 QUERY_DESC_IDN_MAX, 182 QUERY_DESC_IDN_MAX,
200 }; 183 };
201 184
202 enum desc_header_offset { 185 enum desc_header_offset {
203 QUERY_DESC_LENGTH_OFFSET = 0x00 186 QUERY_DESC_LENGTH_OFFSET = 0x00,
204 QUERY_DESC_DESC_TYPE_OFFSET = 0x01 187 QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
205 }; 188 };
206 189
207 /* Unit descriptor parameters offsets in bytes 190 /* Unit descriptor parameters offsets in bytes*/
208 enum unit_desc_param { 191 enum unit_desc_param {
209 UNIT_DESC_PARAM_LEN 192 UNIT_DESC_PARAM_LEN = 0x0,
210 UNIT_DESC_PARAM_TYPE 193 UNIT_DESC_PARAM_TYPE = 0x1,
211 UNIT_DESC_PARAM_UNIT_INDEX 194 UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
212 UNIT_DESC_PARAM_LU_ENABLE 195 UNIT_DESC_PARAM_LU_ENABLE = 0x3,
213 UNIT_DESC_PARAM_BOOT_LUN_ID 196 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
214 UNIT_DESC_PARAM_LU_WR_PROTECT 197 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
215 UNIT_DESC_PARAM_LU_Q_DEPTH 198 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
216 UNIT_DESC_PARAM_PSA_SENSITIVE 199 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
217 UNIT_DESC_PARAM_MEM_TYPE 200 UNIT_DESC_PARAM_MEM_TYPE = 0x8,
218 UNIT_DESC_PARAM_DATA_RELIABILITY 201 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
219 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE 202 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
220 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT 203 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
221 UNIT_DESC_PARAM_ERASE_BLK_SIZE 204 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
222 UNIT_DESC_PARAM_PROVISIONING_TYPE 205 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
223 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT 206 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
224 UNIT_DESC_PARAM_CTX_CAPABILITIES 207 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
225 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 208 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
226 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS 209 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
227 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF 210 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
228 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS 211 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
229 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS 212 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
230 }; 213 };
231 214
232 /* RPMB Unit descriptor parameters offsets in <<
233 enum rpmb_unit_desc_param { <<
234 RPMB_UNIT_DESC_PARAM_LEN <<
235 RPMB_UNIT_DESC_PARAM_TYPE <<
236 RPMB_UNIT_DESC_PARAM_UNIT_INDEX <<
237 RPMB_UNIT_DESC_PARAM_LU_ENABLE <<
238 RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID <<
239 RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT <<
240 RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH <<
241 RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE <<
242 RPMB_UNIT_DESC_PARAM_MEM_TYPE <<
243 RPMB_UNIT_DESC_PARAM_REGION_EN <<
244 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE <<
245 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT <<
246 RPMB_UNIT_DESC_PARAM_REGION0_SIZE <<
247 RPMB_UNIT_DESC_PARAM_REGION1_SIZE <<
248 RPMB_UNIT_DESC_PARAM_REGION2_SIZE <<
249 RPMB_UNIT_DESC_PARAM_REGION3_SIZE <<
250 RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE <<
251 RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT <<
252 }; <<
253 <<
254 /* Device descriptor parameters offsets in byt 215 /* Device descriptor parameters offsets in bytes*/
255 enum device_desc_param { 216 enum device_desc_param {
256 DEVICE_DESC_PARAM_LEN 217 DEVICE_DESC_PARAM_LEN = 0x0,
257 DEVICE_DESC_PARAM_TYPE 218 DEVICE_DESC_PARAM_TYPE = 0x1,
258 DEVICE_DESC_PARAM_DEVICE_TYPE 219 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
259 DEVICE_DESC_PARAM_DEVICE_CLASS 220 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
260 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS 221 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
261 DEVICE_DESC_PARAM_PRTCL 222 DEVICE_DESC_PARAM_PRTCL = 0x5,
262 DEVICE_DESC_PARAM_NUM_LU 223 DEVICE_DESC_PARAM_NUM_LU = 0x6,
263 DEVICE_DESC_PARAM_NUM_WLU 224 DEVICE_DESC_PARAM_NUM_WLU = 0x7,
264 DEVICE_DESC_PARAM_BOOT_ENBL 225 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
265 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL 226 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
266 DEVICE_DESC_PARAM_INIT_PWR_MODE 227 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
267 DEVICE_DESC_PARAM_HIGH_PR_LUN 228 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
268 DEVICE_DESC_PARAM_SEC_RMV_TYPE 229 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
269 DEVICE_DESC_PARAM_SEC_LU 230 DEVICE_DESC_PARAM_SEC_LU = 0xD,
270 DEVICE_DESC_PARAM_BKOP_TERM_LT 231 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
271 DEVICE_DESC_PARAM_ACTVE_ICC_LVL 232 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
272 DEVICE_DESC_PARAM_SPEC_VER 233 DEVICE_DESC_PARAM_SPEC_VER = 0x10,
273 DEVICE_DESC_PARAM_MANF_DATE 234 DEVICE_DESC_PARAM_MANF_DATE = 0x12,
274 DEVICE_DESC_PARAM_MANF_NAME 235 DEVICE_DESC_PARAM_MANF_NAME = 0x14,
275 DEVICE_DESC_PARAM_PRDCT_NAME 236 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
276 DEVICE_DESC_PARAM_SN 237 DEVICE_DESC_PARAM_SN = 0x16,
277 DEVICE_DESC_PARAM_OEM_ID 238 DEVICE_DESC_PARAM_OEM_ID = 0x17,
278 DEVICE_DESC_PARAM_MANF_ID 239 DEVICE_DESC_PARAM_MANF_ID = 0x18,
279 DEVICE_DESC_PARAM_UD_OFFSET 240 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
280 DEVICE_DESC_PARAM_UD_LEN 241 DEVICE_DESC_PARAM_UD_LEN = 0x1B,
281 DEVICE_DESC_PARAM_RTT_CAP 242 DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
282 DEVICE_DESC_PARAM_FRQ_RTC 243 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
283 DEVICE_DESC_PARAM_UFS_FEAT 244 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
284 DEVICE_DESC_PARAM_FFU_TMT 245 DEVICE_DESC_PARAM_FFU_TMT = 0x20,
285 DEVICE_DESC_PARAM_Q_DPTH 246 DEVICE_DESC_PARAM_Q_DPTH = 0x21,
286 DEVICE_DESC_PARAM_DEV_VER 247 DEVICE_DESC_PARAM_DEV_VER = 0x22,
287 DEVICE_DESC_PARAM_NUM_SEC_WPA 248 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
288 DEVICE_DESC_PARAM_PSA_MAX_DATA 249 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
289 DEVICE_DESC_PARAM_PSA_TMT 250 DEVICE_DESC_PARAM_PSA_TMT = 0x29,
290 DEVICE_DESC_PARAM_PRDCT_REV 251 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
291 DEVICE_DESC_PARAM_HPB_VER 252 DEVICE_DESC_PARAM_HPB_VER = 0x40,
292 DEVICE_DESC_PARAM_HPB_CONTROL 253 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
293 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP 254 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
294 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN 255 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
295 DEVICE_DESC_PARAM_WB_TYPE 256 DEVICE_DESC_PARAM_WB_TYPE = 0x54,
296 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNIT 257 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
297 }; 258 };
298 259
299 /* Interconnect descriptor parameters offsets 260 /* Interconnect descriptor parameters offsets in bytes*/
300 enum interconnect_desc_param { 261 enum interconnect_desc_param {
301 INTERCONNECT_DESC_PARAM_LEN 262 INTERCONNECT_DESC_PARAM_LEN = 0x0,
302 INTERCONNECT_DESC_PARAM_TYPE 263 INTERCONNECT_DESC_PARAM_TYPE = 0x1,
303 INTERCONNECT_DESC_PARAM_UNIPRO_VER 264 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
304 INTERCONNECT_DESC_PARAM_MPHY_VER 265 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
305 }; 266 };
306 267
307 /* Geometry descriptor parameters offsets in b 268 /* Geometry descriptor parameters offsets in bytes*/
308 enum geometry_desc_param { 269 enum geometry_desc_param {
309 GEOMETRY_DESC_PARAM_LEN 270 GEOMETRY_DESC_PARAM_LEN = 0x0,
310 GEOMETRY_DESC_PARAM_TYPE 271 GEOMETRY_DESC_PARAM_TYPE = 0x1,
311 GEOMETRY_DESC_PARAM_DEV_CAP 272 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
312 GEOMETRY_DESC_PARAM_MAX_NUM_LUN 273 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
313 GEOMETRY_DESC_PARAM_SEG_SIZE 274 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
314 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE 275 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
315 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE 276 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
316 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE 277 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
317 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE 278 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
318 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE 279 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
319 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE 280 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
320 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE 281 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
321 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC 282 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
322 GEOMETRY_DESC_PARAM_DATA_ORDER 283 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
323 GEOMETRY_DESC_PARAM_MAX_NUM_CTX 284 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
324 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE 285 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
325 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE 286 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
326 GEOMETRY_DESC_PARAM_SEC_RM_TYPES 287 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
327 GEOMETRY_DESC_PARAM_MEM_TYPES 288 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
328 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS 289 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
329 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR 290 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
330 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS 291 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
331 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR 292 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
332 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS 293 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
333 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR 294 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
334 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS 295 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
335 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR 296 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
336 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS 297 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
337 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR 298 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
338 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS 299 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
339 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR 300 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
340 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE 301 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
341 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE 302 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
342 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU 303 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
343 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE 304 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
344 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REG 305 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
345 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS 306 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
346 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS 307 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
347 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ 308 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
348 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE 309 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
349 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE 310 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
350 }; 311 };
351 312
352 /* Health descriptor parameters offsets in byt 313 /* Health descriptor parameters offsets in bytes*/
353 enum health_desc_param { 314 enum health_desc_param {
354 HEALTH_DESC_PARAM_LEN 315 HEALTH_DESC_PARAM_LEN = 0x0,
355 HEALTH_DESC_PARAM_TYPE 316 HEALTH_DESC_PARAM_TYPE = 0x1,
356 HEALTH_DESC_PARAM_EOL_INFO 317 HEALTH_DESC_PARAM_EOL_INFO = 0x2,
357 HEALTH_DESC_PARAM_LIFE_TIME_EST_A 318 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
358 HEALTH_DESC_PARAM_LIFE_TIME_EST_B 319 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
359 }; 320 };
360 321
361 /* WriteBooster buffer mode */ 322 /* WriteBooster buffer mode */
362 enum { 323 enum {
363 WB_BUF_MODE_LU_DEDICATED = 0x0, 324 WB_BUF_MODE_LU_DEDICATED = 0x0,
364 WB_BUF_MODE_SHARED = 0x1, 325 WB_BUF_MODE_SHARED = 0x1,
365 }; 326 };
366 327
367 /* 328 /*
368 * Logical Unit Write Protect 329 * Logical Unit Write Protect
369 * 00h: LU not write protected 330 * 00h: LU not write protected
370 * 01h: LU write protected when fPowerOnWPEn = 331 * 01h: LU write protected when fPowerOnWPEn =1
371 * 02h: LU permanently write protected when fP 332 * 02h: LU permanently write protected when fPermanentWPEn =1
372 */ 333 */
373 enum ufs_lu_wp_type { 334 enum ufs_lu_wp_type {
374 UFS_LU_NO_WP = 0x00, 335 UFS_LU_NO_WP = 0x00,
375 UFS_LU_POWER_ON_WP = 0x01, 336 UFS_LU_POWER_ON_WP = 0x01,
376 UFS_LU_PERM_WP = 0x02, 337 UFS_LU_PERM_WP = 0x02,
377 }; 338 };
378 339
379 /* bActiveICCLevel parameter current units */ 340 /* bActiveICCLevel parameter current units */
380 enum { 341 enum {
381 UFSHCD_NANO_AMP = 0, 342 UFSHCD_NANO_AMP = 0,
382 UFSHCD_MICRO_AMP = 1, 343 UFSHCD_MICRO_AMP = 1,
383 UFSHCD_MILI_AMP = 2, 344 UFSHCD_MILI_AMP = 2,
384 UFSHCD_AMP = 3, 345 UFSHCD_AMP = 3,
385 }; 346 };
386 347
387 /* Possible values for dExtendedUFSFeaturesSup 348 /* Possible values for dExtendedUFSFeaturesSupport */
388 enum { 349 enum {
389 UFS_DEV_LOW_TEMP_NOTIF = BIT( 350 UFS_DEV_LOW_TEMP_NOTIF = BIT(4),
390 UFS_DEV_HIGH_TEMP_NOTIF = BIT( 351 UFS_DEV_HIGH_TEMP_NOTIF = BIT(5),
391 UFS_DEV_EXT_TEMP_NOTIF = BIT( 352 UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
392 UFS_DEV_HPB_SUPPORT = BIT( 353 UFS_DEV_HPB_SUPPORT = BIT(7),
393 UFS_DEV_WRITE_BOOSTER_SUP = BIT( 354 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
394 UFS_DEV_EXT_IID_SUP = BIT( <<
395 }; 355 };
396 #define UFS_DEV_HPB_SUPPORT_VERSION 356 #define UFS_DEV_HPB_SUPPORT_VERSION 0x310
397 357
398 #define POWER_DESC_MAX_ACTV_ICC_LVLS 358 #define POWER_DESC_MAX_ACTV_ICC_LVLS 16
399 359
400 /* Attribute bActiveICCLevel parameter bit ma 360 /* Attribute bActiveICCLevel parameter bit masks definitions */
401 #define ATTR_ICC_LVL_UNIT_OFFSET 14 361 #define ATTR_ICC_LVL_UNIT_OFFSET 14
402 #define ATTR_ICC_LVL_UNIT_MASK (0x3 < 362 #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
403 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF 363 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF
404 364
405 /* Power descriptor parameters offsets in byte 365 /* Power descriptor parameters offsets in bytes */
406 enum power_desc_param_offset { 366 enum power_desc_param_offset {
407 PWR_DESC_LEN = 0x0, 367 PWR_DESC_LEN = 0x0,
408 PWR_DESC_TYPE = 0x1, 368 PWR_DESC_TYPE = 0x1,
409 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2, 369 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
410 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22 370 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
411 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42 371 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
412 }; 372 };
413 373
414 /* Exception event mask values */ 374 /* Exception event mask values */
415 enum { 375 enum {
416 MASK_EE_STATUS = 0xFF 376 MASK_EE_STATUS = 0xFFFF,
417 MASK_EE_DYNCAP_EVENT = BIT( 377 MASK_EE_DYNCAP_EVENT = BIT(0),
418 MASK_EE_SYSPOOL_EVENT = BIT( 378 MASK_EE_SYSPOOL_EVENT = BIT(1),
419 MASK_EE_URGENT_BKOPS = BIT( 379 MASK_EE_URGENT_BKOPS = BIT(2),
420 MASK_EE_TOO_HIGH_TEMP = BIT( 380 MASK_EE_TOO_HIGH_TEMP = BIT(3),
421 MASK_EE_TOO_LOW_TEMP = BIT( 381 MASK_EE_TOO_LOW_TEMP = BIT(4),
422 MASK_EE_WRITEBOOSTER_EVENT = BIT( 382 MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
423 MASK_EE_PERFORMANCE_THROTTLING = BIT( 383 MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
424 }; 384 };
425 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_ 385 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
426 386
427 /* Background operation status */ 387 /* Background operation status */
428 enum bkops_status { 388 enum bkops_status {
429 BKOPS_STATUS_NO_OP = 0x0 389 BKOPS_STATUS_NO_OP = 0x0,
430 BKOPS_STATUS_NON_CRITICAL = 0x1 390 BKOPS_STATUS_NON_CRITICAL = 0x1,
431 BKOPS_STATUS_PERF_IMPACT = 0x2 391 BKOPS_STATUS_PERF_IMPACT = 0x2,
432 BKOPS_STATUS_CRITICAL = 0x3 392 BKOPS_STATUS_CRITICAL = 0x3,
433 BKOPS_STATUS_MAX = BKO 393 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
434 }; 394 };
435 395
436 /* UTP QUERY Transaction Specific Fields OpCod 396 /* UTP QUERY Transaction Specific Fields OpCode */
437 enum query_opcode { 397 enum query_opcode {
438 UPIU_QUERY_OPCODE_NOP = 0x0, 398 UPIU_QUERY_OPCODE_NOP = 0x0,
439 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 399 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
440 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 400 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
441 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 401 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
442 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 402 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
443 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 403 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
444 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 404 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
445 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 405 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
446 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 406 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
447 }; 407 };
448 408
449 /* bRefClkFreq attribute values */ 409 /* bRefClkFreq attribute values */
450 enum ufs_ref_clk_freq { 410 enum ufs_ref_clk_freq {
451 REF_CLK_FREQ_19_2_MHZ = 0, 411 REF_CLK_FREQ_19_2_MHZ = 0,
452 REF_CLK_FREQ_26_MHZ = 1, 412 REF_CLK_FREQ_26_MHZ = 1,
453 REF_CLK_FREQ_38_4_MHZ = 2, 413 REF_CLK_FREQ_38_4_MHZ = 2,
454 REF_CLK_FREQ_52_MHZ = 3, 414 REF_CLK_FREQ_52_MHZ = 3,
455 REF_CLK_FREQ_INVAL = -1, 415 REF_CLK_FREQ_INVAL = -1,
456 }; 416 };
457 417
458 /* Query response result code */ 418 /* Query response result code */
459 enum { 419 enum {
460 QUERY_RESULT_SUCCESS 420 QUERY_RESULT_SUCCESS = 0x00,
461 QUERY_RESULT_NOT_READABLE 421 QUERY_RESULT_NOT_READABLE = 0xF6,
462 QUERY_RESULT_NOT_WRITEABLE 422 QUERY_RESULT_NOT_WRITEABLE = 0xF7,
463 QUERY_RESULT_ALREADY_WRITTEN 423 QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
464 QUERY_RESULT_INVALID_LENGTH 424 QUERY_RESULT_INVALID_LENGTH = 0xF9,
465 QUERY_RESULT_INVALID_VALUE 425 QUERY_RESULT_INVALID_VALUE = 0xFA,
466 QUERY_RESULT_INVALID_SELECTOR 426 QUERY_RESULT_INVALID_SELECTOR = 0xFB,
467 QUERY_RESULT_INVALID_INDEX 427 QUERY_RESULT_INVALID_INDEX = 0xFC,
468 QUERY_RESULT_INVALID_IDN 428 QUERY_RESULT_INVALID_IDN = 0xFD,
469 QUERY_RESULT_INVALID_OPCODE 429 QUERY_RESULT_INVALID_OPCODE = 0xFE,
470 QUERY_RESULT_GENERAL_FAILURE 430 QUERY_RESULT_GENERAL_FAILURE = 0xFF,
471 }; 431 };
472 432
473 /* UTP Transfer Request Command Type (CT) */ 433 /* UTP Transfer Request Command Type (CT) */
474 enum { 434 enum {
475 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 435 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
476 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 436 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
477 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 437 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
478 }; 438 };
479 439
>> 440 /* UTP Transfer Request Command Offset */
>> 441 #define UPIU_COMMAND_TYPE_OFFSET 28
>> 442
480 /* Offset of the response code in the UPIU hea 443 /* Offset of the response code in the UPIU header */
481 #define UPIU_RSP_CODE_OFFSET 8 444 #define UPIU_RSP_CODE_OFFSET 8
482 445
483 enum { 446 enum {
>> 447 MASK_SCSI_STATUS = 0xFF,
>> 448 MASK_TASK_RESPONSE = 0xFF00,
>> 449 MASK_RSP_UPIU_RESULT = 0xFFFF,
>> 450 MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
>> 451 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
>> 452 MASK_RSP_EXCEPTION_EVENT = 0x10000,
484 MASK_TM_SERVICE_RESP = 0xFF 453 MASK_TM_SERVICE_RESP = 0xFF,
>> 454 MASK_TM_FUNC = 0xFF,
485 }; 455 };
486 456
487 /* Task management service response */ 457 /* Task management service response */
488 enum { 458 enum {
489 UPIU_TASK_MANAGEMENT_FUNC_COMPL 459 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
490 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTE 460 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
491 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED 461 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
492 UPIU_TASK_MANAGEMENT_FUNC_FAILED 462 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
493 UPIU_INCORRECT_LOGICAL_UNIT_NO 463 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
494 }; 464 };
495 465
496 /* UFS device power modes */ 466 /* UFS device power modes */
497 enum ufs_dev_pwr_mode { 467 enum ufs_dev_pwr_mode {
498 UFS_ACTIVE_PWR_MODE = 1, 468 UFS_ACTIVE_PWR_MODE = 1,
499 UFS_SLEEP_PWR_MODE = 2, 469 UFS_SLEEP_PWR_MODE = 2,
500 UFS_POWERDOWN_PWR_MODE = 3, 470 UFS_POWERDOWN_PWR_MODE = 3,
501 UFS_DEEPSLEEP_PWR_MODE = 4, 471 UFS_DEEPSLEEP_PWR_MODE = 4,
502 }; 472 };
503 473
504 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) 474 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
505 475
506 /** 476 /**
507 * struct utp_cmd_rsp - Response UPIU structur 477 * struct utp_cmd_rsp - Response UPIU structure
508 * @residual_transfer_count: Residual transfer 478 * @residual_transfer_count: Residual transfer count DW-3
509 * @reserved: Reserved double words DW-4 to DW 479 * @reserved: Reserved double words DW-4 to DW-7
510 * @sense_data_len: Sense data length DW-8 U16 480 * @sense_data_len: Sense data length DW-8 U16
511 * @sense_data: Sense data field DW-8 to DW-12 481 * @sense_data: Sense data field DW-8 to DW-12
512 */ 482 */
513 struct utp_cmd_rsp { 483 struct utp_cmd_rsp {
514 __be32 residual_transfer_count; 484 __be32 residual_transfer_count;
515 __be32 reserved[4]; 485 __be32 reserved[4];
516 __be16 sense_data_len; 486 __be16 sense_data_len;
517 u8 sense_data[UFS_SENSE_SIZE]; 487 u8 sense_data[UFS_SENSE_SIZE];
518 }; 488 };
519 489
>> 490 struct ufshpb_active_field {
>> 491 __be16 active_rgn;
>> 492 __be16 active_srgn;
>> 493 };
>> 494 #define HPB_ACT_FIELD_SIZE 4
>> 495
>> 496 /**
>> 497 * struct utp_hpb_rsp - Response UPIU structure
>> 498 * @residual_transfer_count: Residual transfer count DW-3
>> 499 * @reserved1: Reserved double words DW-4 to DW-7
>> 500 * @sense_data_len: Sense data length DW-8 U16
>> 501 * @desc_type: Descriptor type of sense data
>> 502 * @additional_len: Additional length of sense data
>> 503 * @hpb_op: HPB operation type
>> 504 * @lun: LUN of response UPIU
>> 505 * @active_rgn_cnt: Active region count
>> 506 * @inactive_rgn_cnt: Inactive region count
>> 507 * @hpb_active_field: Recommended to read HPB region and subregion
>> 508 * @hpb_inactive_field: To be inactivated HPB region and subregion
>> 509 */
>> 510 struct utp_hpb_rsp {
>> 511 __be32 residual_transfer_count;
>> 512 __be32 reserved1[4];
>> 513 __be16 sense_data_len;
>> 514 u8 desc_type;
>> 515 u8 additional_len;
>> 516 u8 hpb_op;
>> 517 u8 lun;
>> 518 u8 active_rgn_cnt;
>> 519 u8 inactive_rgn_cnt;
>> 520 struct ufshpb_active_field hpb_active_field[2];
>> 521 __be16 hpb_inactive_field[2];
>> 522 };
>> 523 #define UTP_HPB_RSP_SIZE 40
>> 524
520 /** 525 /**
521 * struct utp_upiu_rsp - general upiu response 526 * struct utp_upiu_rsp - general upiu response structure
522 * @header: UPIU header structure DW-0 to DW-2 527 * @header: UPIU header structure DW-0 to DW-2
523 * @sr: fields structure for scsi command DW-3 528 * @sr: fields structure for scsi command DW-3 to DW-12
524 * @qr: fields structure for query request DW- 529 * @qr: fields structure for query request DW-3 to DW-7
525 */ 530 */
526 struct utp_upiu_rsp { 531 struct utp_upiu_rsp {
527 struct utp_upiu_header header; 532 struct utp_upiu_header header;
528 union { 533 union {
529 struct utp_cmd_rsp sr; 534 struct utp_cmd_rsp sr;
>> 535 struct utp_hpb_rsp hr;
530 struct utp_upiu_query qr; 536 struct utp_upiu_query qr;
531 }; 537 };
532 }; 538 };
533 539
>> 540 /**
>> 541 * struct ufs_query_req - parameters for building a query request
>> 542 * @query_func: UPIU header query function
>> 543 * @upiu_req: the query request data
>> 544 */
>> 545 struct ufs_query_req {
>> 546 u8 query_func;
>> 547 struct utp_upiu_query upiu_req;
>> 548 };
>> 549
>> 550 /**
>> 551 * struct ufs_query_resp - UPIU QUERY
>> 552 * @response: device response code
>> 553 * @upiu_res: query response data
>> 554 */
>> 555 struct ufs_query_res {
>> 556 u8 response;
>> 557 struct utp_upiu_query upiu_res;
>> 558 };
>> 559
534 /* 560 /*
535 * VCCQ & VCCQ2 current requirement when UFS d 561 * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
536 * and link is in Hibern8 state. 562 * and link is in Hibern8 state.
537 */ 563 */
538 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */ 564 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
539 565
540 struct ufs_vreg { 566 struct ufs_vreg {
541 struct regulator *reg; 567 struct regulator *reg;
542 const char *name; 568 const char *name;
543 bool always_on; 569 bool always_on;
544 bool enabled; 570 bool enabled;
545 int max_uA; 571 int max_uA;
546 }; 572 };
547 573
548 struct ufs_vreg_info { 574 struct ufs_vreg_info {
549 struct ufs_vreg *vcc; 575 struct ufs_vreg *vcc;
550 struct ufs_vreg *vccq; 576 struct ufs_vreg *vccq;
551 struct ufs_vreg *vccq2; 577 struct ufs_vreg *vccq2;
552 struct ufs_vreg *vdd_hba; 578 struct ufs_vreg *vdd_hba;
553 }; 579 };
554 580
555 /* UFS device descriptor wPeriodicRTCUpdate bi <<
556 #define UFS_RTC_TIME_BASELINE BIT(9) <<
557 <<
558 enum ufs_rtc_time { <<
559 UFS_RTC_RELATIVE, <<
560 UFS_RTC_ABSOLUTE <<
561 }; <<
562 <<
563 struct ufs_dev_info { 581 struct ufs_dev_info {
564 bool f_power_on_wp_en; 582 bool f_power_on_wp_en;
565 /* Keeps information if any of the LU 583 /* Keeps information if any of the LU is power on write protected */
566 bool is_lu_power_on_wp; 584 bool is_lu_power_on_wp;
567 /* Maximum number of general LU suppor 585 /* Maximum number of general LU supported by the UFS device */
568 u8 max_lu_supported; 586 u8 max_lu_supported;
569 u16 wmanufacturerid; 587 u16 wmanufacturerid;
570 /*UFS device Product Name */ 588 /*UFS device Product Name */
571 u8 *model; 589 u8 *model;
572 u16 wspecversion; 590 u16 wspecversion;
573 u32 clk_gating_wait_us; 591 u32 clk_gating_wait_us;
574 /* Stores the depth of queue in UFS de !! 592
575 u8 bqueuedepth; !! 593 /* UFS HPB related flag */
>> 594 bool hpb_enabled;
576 595
577 /* UFS WB related flags */ 596 /* UFS WB related flags */
578 bool wb_enabled; 597 bool wb_enabled;
579 bool wb_buf_flush_enabled; 598 bool wb_buf_flush_enabled;
580 u8 wb_dedicated_lu; 599 u8 wb_dedicated_lu;
581 u8 wb_buffer_type; 600 u8 wb_buffer_type;
582 601
583 bool b_rpm_dev_flush_capable; 602 bool b_rpm_dev_flush_capable;
584 u8 b_presrv_uspc_en; 603 u8 b_presrv_uspc_en;
585 <<
586 bool b_advanced_rpmb_en; <<
587 <<
588 /* UFS EXT_IID Enable */ <<
589 bool b_ext_iid_en; <<
590 <<
591 /* UFS RTC */ <<
592 enum ufs_rtc_time rtc_type; <<
593 time64_t rtc_time_baseline; <<
594 u32 rtc_update_period; <<
595 <<
596 u8 rtt_cap; /* bDeviceRTTCap */ <<
597 }; 604 };
598 605
599 /* 606 /*
600 * This enum is used in string mapping in incl 607 * This enum is used in string mapping in include/trace/events/ufs.h.
601 */ 608 */
602 enum ufs_trace_str_t { 609 enum ufs_trace_str_t {
603 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_CO 610 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
604 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QU 611 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
605 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR 612 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
606 }; 613 };
607 614
608 /* 615 /*
609 * Transaction Specific Fields (TSF) type in t 616 * Transaction Specific Fields (TSF) type in the UPIU package, this enum is
610 * used in include/trace/events/ufs.h for UFS 617 * used in include/trace/events/ufs.h for UFS command trace.
611 */ 618 */
612 enum ufs_trace_tsf_t { 619 enum ufs_trace_tsf_t {
613 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_I 620 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
614 }; 621 };
615 622
616 #endif /* End of Header */ 623 #endif /* End of Header */
617 624
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