1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Universal Flash Storage Host controller dri 3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Softw 4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * 5 *
6 * Authors: 6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung 7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.c 8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */ 9 */
10 10
11 #ifndef _UFS_H 11 #ifndef _UFS_H
12 #define _UFS_H 12 #define _UFS_H
13 13
14 #include <linux/bitops.h> !! 14 #include <linux/mutex.h>
15 #include <linux/types.h> 15 #include <linux/types.h>
16 #include <uapi/scsi/scsi_bsg_ufs.h> 16 #include <uapi/scsi/scsi_bsg_ufs.h>
17 #include <linux/time64.h> <<
18 <<
19 /* <<
20 * Using static_assert() is not allowed in UAP <<
21 * in this header file of the size of struct u <<
22 */ <<
23 static_assert(sizeof(struct utp_upiu_header) = <<
24 17
25 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(stru 18 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
26 #define QUERY_DESC_MAX_SIZE 255 19 #define QUERY_DESC_MAX_SIZE 255
27 #define QUERY_DESC_MIN_SIZE 2 20 #define QUERY_DESC_MIN_SIZE 2
28 #define QUERY_DESC_HDR_SIZE 2 21 #define QUERY_DESC_HDR_SIZE 2
29 #define QUERY_OSF_SIZE (GENERAL_UPI 22 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
30 (sizeo 23 (sizeof(struct utp_upiu_header)))
31 #define UFS_SENSE_SIZE 18 24 #define UFS_SENSE_SIZE 18
32 25
>> 26 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
>> 27 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
>> 28 (byte1 << 8) | (byte0))
33 /* 29 /*
34 * UFS device may have standard LUs and LUN id 30 * UFS device may have standard LUs and LUN id could be from 0x00 to
35 * 0x7F. Standard LUs use "Peripheral Device A 31 * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
36 * UFS device may also have the Well Known LUs 32 * UFS device may also have the Well Known LUs (also referred as W-LU)
37 * which again could be from 0x00 to 0x7F. For 33 * which again could be from 0x00 to 0x7F. For W-LUs, device only use
38 * the "Extended Addressing Format" which mean 34 * the "Extended Addressing Format" which means the W-LUNs would be
39 * from 0xc100 (SCSI_W_LUN_BASE) onwards. 35 * from 0xc100 (SCSI_W_LUN_BASE) onwards.
40 * This means max. LUN number reported from UF 36 * This means max. LUN number reported from UFS device could be 0xC17F.
41 */ 37 */
42 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F 38 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
43 #define UFS_MAX_LUNS (SCSI_W_LUN_BA 39 #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
44 #define UFS_UPIU_WLUN_ID (1 << 7) 40 #define UFS_UPIU_WLUN_ID (1 << 7)
45 41
46 /* WriteBooster buffer is available only for t 42 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
47 #define UFS_UPIU_MAX_WB_LUN_ID 8 43 #define UFS_UPIU_MAX_WB_LUN_ID 8
48 44
49 /* 45 /*
50 * WriteBooster buffer lifetime has a limit se 46 * WriteBooster buffer lifetime has a limit setted by vendor.
51 * If it is over the limit, WriteBooster featu 47 * If it is over the limit, WriteBooster feature will be disabled.
52 */ 48 */
53 #define UFS_WB_EXCEED_LIFETIME 0x0B 49 #define UFS_WB_EXCEED_LIFETIME 0x0B
54 50
55 /* 51 /*
56 * In UFS Spec, the Extra Header Segment (EHS) 52 * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet
57 */ 53 */
58 #define EHS_OFFSET_IN_RESPONSE 32 54 #define EHS_OFFSET_IN_RESPONSE 32
59 55
60 /* Well known logical unit id in LUN field of 56 /* Well known logical unit id in LUN field of UPIU */
61 enum { 57 enum {
62 UFS_UPIU_REPORT_LUNS_WLUN = 0x81 58 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
63 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0 59 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
64 UFS_UPIU_BOOT_WLUN = 0xB0 60 UFS_UPIU_BOOT_WLUN = 0xB0,
65 UFS_UPIU_RPMB_WLUN = 0xC4 61 UFS_UPIU_RPMB_WLUN = 0xC4,
66 }; 62 };
67 63
68 /* 64 /*
69 * UFS Protocol Information Unit related defin 65 * UFS Protocol Information Unit related definitions
70 */ 66 */
71 67
72 /* Task management functions */ 68 /* Task management functions */
73 enum { 69 enum {
74 UFS_ABORT_TASK = 0x01, 70 UFS_ABORT_TASK = 0x01,
75 UFS_ABORT_TASK_SET = 0x02, 71 UFS_ABORT_TASK_SET = 0x02,
76 UFS_CLEAR_TASK_SET = 0x04, 72 UFS_CLEAR_TASK_SET = 0x04,
77 UFS_LOGICAL_RESET = 0x08, 73 UFS_LOGICAL_RESET = 0x08,
78 UFS_QUERY_TASK = 0x80, 74 UFS_QUERY_TASK = 0x80,
79 UFS_QUERY_TASK_SET = 0x81, 75 UFS_QUERY_TASK_SET = 0x81,
80 }; 76 };
81 77
82 /* UTP UPIU Transaction Codes Initiator to Tar 78 /* UTP UPIU Transaction Codes Initiator to Target */
83 enum upiu_request_transaction { !! 79 enum {
84 UPIU_TRANSACTION_NOP_OUT = 0x00 80 UPIU_TRANSACTION_NOP_OUT = 0x00,
85 UPIU_TRANSACTION_COMMAND = 0x01 81 UPIU_TRANSACTION_COMMAND = 0x01,
86 UPIU_TRANSACTION_DATA_OUT = 0x02 82 UPIU_TRANSACTION_DATA_OUT = 0x02,
87 UPIU_TRANSACTION_TASK_REQ = 0x04 83 UPIU_TRANSACTION_TASK_REQ = 0x04,
88 UPIU_TRANSACTION_QUERY_REQ = 0x16 84 UPIU_TRANSACTION_QUERY_REQ = 0x16,
89 }; 85 };
90 86
91 /* UTP UPIU Transaction Codes Target to Initia 87 /* UTP UPIU Transaction Codes Target to Initiator */
92 enum upiu_response_transaction { !! 88 enum {
93 UPIU_TRANSACTION_NOP_IN = 0x20 89 UPIU_TRANSACTION_NOP_IN = 0x20,
94 UPIU_TRANSACTION_RESPONSE = 0x21 90 UPIU_TRANSACTION_RESPONSE = 0x21,
95 UPIU_TRANSACTION_DATA_IN = 0x22 91 UPIU_TRANSACTION_DATA_IN = 0x22,
96 UPIU_TRANSACTION_TASK_RSP = 0x24 92 UPIU_TRANSACTION_TASK_RSP = 0x24,
97 UPIU_TRANSACTION_READY_XFER = 0x31 93 UPIU_TRANSACTION_READY_XFER = 0x31,
98 UPIU_TRANSACTION_QUERY_RSP = 0x36 94 UPIU_TRANSACTION_QUERY_RSP = 0x36,
99 UPIU_TRANSACTION_REJECT_UPIU = 0x3F 95 UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
100 }; 96 };
101 97
102 /* UPIU Read/Write flags. See also table "UPIU !! 98 /* UPIU Read/Write flags */
103 enum { 99 enum {
104 UPIU_CMD_FLAGS_NONE = 0x00, 100 UPIU_CMD_FLAGS_NONE = 0x00,
105 UPIU_CMD_FLAGS_CP = 0x04, <<
106 UPIU_CMD_FLAGS_WRITE = 0x20, 101 UPIU_CMD_FLAGS_WRITE = 0x20,
107 UPIU_CMD_FLAGS_READ = 0x40, 102 UPIU_CMD_FLAGS_READ = 0x40,
108 }; 103 };
109 104
110 /* UPIU response flags */ 105 /* UPIU response flags */
111 enum { 106 enum {
112 UPIU_RSP_FLAG_UNDERFLOW = 0x20, 107 UPIU_RSP_FLAG_UNDERFLOW = 0x20,
113 UPIU_RSP_FLAG_OVERFLOW = 0x40, 108 UPIU_RSP_FLAG_OVERFLOW = 0x40,
114 }; 109 };
115 110
116 /* UPIU Task Attributes */ 111 /* UPIU Task Attributes */
117 enum { 112 enum {
118 UPIU_TASK_ATTR_SIMPLE = 0x00, 113 UPIU_TASK_ATTR_SIMPLE = 0x00,
119 UPIU_TASK_ATTR_ORDERED = 0x01, 114 UPIU_TASK_ATTR_ORDERED = 0x01,
120 UPIU_TASK_ATTR_HEADQ = 0x02, 115 UPIU_TASK_ATTR_HEADQ = 0x02,
121 UPIU_TASK_ATTR_ACA = 0x03, 116 UPIU_TASK_ATTR_ACA = 0x03,
122 }; 117 };
123 118
124 /* UPIU Query request function */ 119 /* UPIU Query request function */
125 enum { 120 enum {
126 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST 121 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
127 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST 122 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
128 }; 123 };
129 124
130 /* Flag idn for Query Requests*/ 125 /* Flag idn for Query Requests*/
131 enum flag_idn { 126 enum flag_idn {
132 QUERY_FLAG_IDN_FDEVICEINIT 127 QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
133 QUERY_FLAG_IDN_PERMANENT_WPE 128 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
134 QUERY_FLAG_IDN_PWR_ON_WPE 129 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
135 QUERY_FLAG_IDN_BKOPS_EN 130 QUERY_FLAG_IDN_BKOPS_EN = 0x04,
136 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE 131 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
137 QUERY_FLAG_IDN_PURGE_ENABLE 132 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
138 QUERY_FLAG_IDN_RESERVED2 133 QUERY_FLAG_IDN_RESERVED2 = 0x07,
139 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL 134 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
140 QUERY_FLAG_IDN_BUSY_RTC 135 QUERY_FLAG_IDN_BUSY_RTC = 0x09,
141 QUERY_FLAG_IDN_RESERVED3 136 QUERY_FLAG_IDN_RESERVED3 = 0x0A,
142 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_ 137 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
143 QUERY_FLAG_IDN_WB_EN 138 QUERY_FLAG_IDN_WB_EN = 0x0E,
144 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN 139 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
145 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HI 140 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
146 QUERY_FLAG_IDN_HPB_RESET 141 QUERY_FLAG_IDN_HPB_RESET = 0x11,
147 QUERY_FLAG_IDN_HPB_EN 142 QUERY_FLAG_IDN_HPB_EN = 0x12,
148 }; 143 };
149 144
150 /* Attribute idn for Query requests */ 145 /* Attribute idn for Query requests */
151 enum attr_idn { 146 enum attr_idn {
152 QUERY_ATTR_IDN_BOOT_LU_EN 147 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
153 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD 148 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
154 QUERY_ATTR_IDN_POWER_MODE 149 QUERY_ATTR_IDN_POWER_MODE = 0x02,
155 QUERY_ATTR_IDN_ACTIVE_ICC_LVL 150 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
156 QUERY_ATTR_IDN_OOO_DATA_EN 151 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
157 QUERY_ATTR_IDN_BKOPS_STATUS 152 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
158 QUERY_ATTR_IDN_PURGE_STATUS 153 QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
159 QUERY_ATTR_IDN_MAX_DATA_IN 154 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
160 QUERY_ATTR_IDN_MAX_DATA_OUT 155 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
161 QUERY_ATTR_IDN_DYN_CAP_NEEDED 156 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
162 QUERY_ATTR_IDN_REF_CLK_FREQ 157 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
163 QUERY_ATTR_IDN_CONF_DESC_LOCK 158 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
164 QUERY_ATTR_IDN_MAX_NUM_OF_RTT 159 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
165 QUERY_ATTR_IDN_EE_CONTROL 160 QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
166 QUERY_ATTR_IDN_EE_STATUS 161 QUERY_ATTR_IDN_EE_STATUS = 0x0E,
167 QUERY_ATTR_IDN_SECONDS_PASSED 162 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
168 QUERY_ATTR_IDN_CNTX_CONF 163 QUERY_ATTR_IDN_CNTX_CONF = 0x10,
169 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM 164 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
170 QUERY_ATTR_IDN_RESERVED2 165 QUERY_ATTR_IDN_RESERVED2 = 0x12,
171 QUERY_ATTR_IDN_RESERVED3 166 QUERY_ATTR_IDN_RESERVED3 = 0x13,
172 QUERY_ATTR_IDN_FFU_STATUS 167 QUERY_ATTR_IDN_FFU_STATUS = 0x14,
173 QUERY_ATTR_IDN_PSA_STATE 168 QUERY_ATTR_IDN_PSA_STATE = 0x15,
174 QUERY_ATTR_IDN_PSA_DATA_SIZE 169 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
175 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIM 170 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
176 QUERY_ATTR_IDN_CASE_ROUGH_TEMP 171 QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
177 QUERY_ATTR_IDN_HIGH_TEMP_BOUND 172 QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
178 QUERY_ATTR_IDN_LOW_TEMP_BOUND 173 QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
179 QUERY_ATTR_IDN_WB_FLUSH_STATUS 174 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
180 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE 175 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
181 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST 176 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
182 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE 177 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
183 QUERY_ATTR_IDN_EXT_IID_EN 178 QUERY_ATTR_IDN_EXT_IID_EN = 0x2A,
184 QUERY_ATTR_IDN_TIMESTAMP 179 QUERY_ATTR_IDN_TIMESTAMP = 0x30
185 }; 180 };
186 181
187 /* Descriptor idn for Query requests */ 182 /* Descriptor idn for Query requests */
188 enum desc_idn { 183 enum desc_idn {
189 QUERY_DESC_IDN_DEVICE = 0x0, 184 QUERY_DESC_IDN_DEVICE = 0x0,
190 QUERY_DESC_IDN_CONFIGURATION = 0x1, 185 QUERY_DESC_IDN_CONFIGURATION = 0x1,
191 QUERY_DESC_IDN_UNIT = 0x2, 186 QUERY_DESC_IDN_UNIT = 0x2,
192 QUERY_DESC_IDN_RFU_0 = 0x3, 187 QUERY_DESC_IDN_RFU_0 = 0x3,
193 QUERY_DESC_IDN_INTERCONNECT = 0x4, 188 QUERY_DESC_IDN_INTERCONNECT = 0x4,
194 QUERY_DESC_IDN_STRING = 0x5, 189 QUERY_DESC_IDN_STRING = 0x5,
195 QUERY_DESC_IDN_RFU_1 = 0x6, 190 QUERY_DESC_IDN_RFU_1 = 0x6,
196 QUERY_DESC_IDN_GEOMETRY = 0x7, 191 QUERY_DESC_IDN_GEOMETRY = 0x7,
197 QUERY_DESC_IDN_POWER = 0x8, 192 QUERY_DESC_IDN_POWER = 0x8,
198 QUERY_DESC_IDN_HEALTH = 0x9, 193 QUERY_DESC_IDN_HEALTH = 0x9,
199 QUERY_DESC_IDN_MAX, 194 QUERY_DESC_IDN_MAX,
200 }; 195 };
201 196
202 enum desc_header_offset { 197 enum desc_header_offset {
203 QUERY_DESC_LENGTH_OFFSET = 0x00 198 QUERY_DESC_LENGTH_OFFSET = 0x00,
204 QUERY_DESC_DESC_TYPE_OFFSET = 0x01 199 QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
205 }; 200 };
206 201
207 /* Unit descriptor parameters offsets in bytes 202 /* Unit descriptor parameters offsets in bytes*/
208 enum unit_desc_param { 203 enum unit_desc_param {
209 UNIT_DESC_PARAM_LEN 204 UNIT_DESC_PARAM_LEN = 0x0,
210 UNIT_DESC_PARAM_TYPE 205 UNIT_DESC_PARAM_TYPE = 0x1,
211 UNIT_DESC_PARAM_UNIT_INDEX 206 UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
212 UNIT_DESC_PARAM_LU_ENABLE 207 UNIT_DESC_PARAM_LU_ENABLE = 0x3,
213 UNIT_DESC_PARAM_BOOT_LUN_ID 208 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
214 UNIT_DESC_PARAM_LU_WR_PROTECT 209 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
215 UNIT_DESC_PARAM_LU_Q_DEPTH 210 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
216 UNIT_DESC_PARAM_PSA_SENSITIVE 211 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
217 UNIT_DESC_PARAM_MEM_TYPE 212 UNIT_DESC_PARAM_MEM_TYPE = 0x8,
218 UNIT_DESC_PARAM_DATA_RELIABILITY 213 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
219 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE 214 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
220 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT 215 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
221 UNIT_DESC_PARAM_ERASE_BLK_SIZE 216 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
222 UNIT_DESC_PARAM_PROVISIONING_TYPE 217 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
223 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT 218 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
224 UNIT_DESC_PARAM_CTX_CAPABILITIES 219 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
225 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 220 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
226 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS 221 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
227 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF 222 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
228 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS 223 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
229 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS 224 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
230 }; 225 };
231 226
232 /* RPMB Unit descriptor parameters offsets in 227 /* RPMB Unit descriptor parameters offsets in bytes*/
233 enum rpmb_unit_desc_param { 228 enum rpmb_unit_desc_param {
234 RPMB_UNIT_DESC_PARAM_LEN 229 RPMB_UNIT_DESC_PARAM_LEN = 0x0,
235 RPMB_UNIT_DESC_PARAM_TYPE 230 RPMB_UNIT_DESC_PARAM_TYPE = 0x1,
236 RPMB_UNIT_DESC_PARAM_UNIT_INDEX 231 RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
237 RPMB_UNIT_DESC_PARAM_LU_ENABLE 232 RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3,
238 RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID 233 RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
239 RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT 234 RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
240 RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH 235 RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
241 RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE 236 RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
242 RPMB_UNIT_DESC_PARAM_MEM_TYPE 237 RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8,
243 RPMB_UNIT_DESC_PARAM_REGION_EN 238 RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9,
244 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE 239 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
245 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT 240 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
246 RPMB_UNIT_DESC_PARAM_REGION0_SIZE 241 RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13,
247 RPMB_UNIT_DESC_PARAM_REGION1_SIZE 242 RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14,
248 RPMB_UNIT_DESC_PARAM_REGION2_SIZE 243 RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15,
249 RPMB_UNIT_DESC_PARAM_REGION3_SIZE 244 RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16,
250 RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE 245 RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
251 RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT 246 RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
252 }; 247 };
253 248
254 /* Device descriptor parameters offsets in byt 249 /* Device descriptor parameters offsets in bytes*/
255 enum device_desc_param { 250 enum device_desc_param {
256 DEVICE_DESC_PARAM_LEN 251 DEVICE_DESC_PARAM_LEN = 0x0,
257 DEVICE_DESC_PARAM_TYPE 252 DEVICE_DESC_PARAM_TYPE = 0x1,
258 DEVICE_DESC_PARAM_DEVICE_TYPE 253 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
259 DEVICE_DESC_PARAM_DEVICE_CLASS 254 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
260 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS 255 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
261 DEVICE_DESC_PARAM_PRTCL 256 DEVICE_DESC_PARAM_PRTCL = 0x5,
262 DEVICE_DESC_PARAM_NUM_LU 257 DEVICE_DESC_PARAM_NUM_LU = 0x6,
263 DEVICE_DESC_PARAM_NUM_WLU 258 DEVICE_DESC_PARAM_NUM_WLU = 0x7,
264 DEVICE_DESC_PARAM_BOOT_ENBL 259 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
265 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL 260 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
266 DEVICE_DESC_PARAM_INIT_PWR_MODE 261 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
267 DEVICE_DESC_PARAM_HIGH_PR_LUN 262 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
268 DEVICE_DESC_PARAM_SEC_RMV_TYPE 263 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
269 DEVICE_DESC_PARAM_SEC_LU 264 DEVICE_DESC_PARAM_SEC_LU = 0xD,
270 DEVICE_DESC_PARAM_BKOP_TERM_LT 265 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
271 DEVICE_DESC_PARAM_ACTVE_ICC_LVL 266 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
272 DEVICE_DESC_PARAM_SPEC_VER 267 DEVICE_DESC_PARAM_SPEC_VER = 0x10,
273 DEVICE_DESC_PARAM_MANF_DATE 268 DEVICE_DESC_PARAM_MANF_DATE = 0x12,
274 DEVICE_DESC_PARAM_MANF_NAME 269 DEVICE_DESC_PARAM_MANF_NAME = 0x14,
275 DEVICE_DESC_PARAM_PRDCT_NAME 270 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
276 DEVICE_DESC_PARAM_SN 271 DEVICE_DESC_PARAM_SN = 0x16,
277 DEVICE_DESC_PARAM_OEM_ID 272 DEVICE_DESC_PARAM_OEM_ID = 0x17,
278 DEVICE_DESC_PARAM_MANF_ID 273 DEVICE_DESC_PARAM_MANF_ID = 0x18,
279 DEVICE_DESC_PARAM_UD_OFFSET 274 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
280 DEVICE_DESC_PARAM_UD_LEN 275 DEVICE_DESC_PARAM_UD_LEN = 0x1B,
281 DEVICE_DESC_PARAM_RTT_CAP 276 DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
282 DEVICE_DESC_PARAM_FRQ_RTC 277 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
283 DEVICE_DESC_PARAM_UFS_FEAT 278 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
284 DEVICE_DESC_PARAM_FFU_TMT 279 DEVICE_DESC_PARAM_FFU_TMT = 0x20,
285 DEVICE_DESC_PARAM_Q_DPTH 280 DEVICE_DESC_PARAM_Q_DPTH = 0x21,
286 DEVICE_DESC_PARAM_DEV_VER 281 DEVICE_DESC_PARAM_DEV_VER = 0x22,
287 DEVICE_DESC_PARAM_NUM_SEC_WPA 282 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
288 DEVICE_DESC_PARAM_PSA_MAX_DATA 283 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
289 DEVICE_DESC_PARAM_PSA_TMT 284 DEVICE_DESC_PARAM_PSA_TMT = 0x29,
290 DEVICE_DESC_PARAM_PRDCT_REV 285 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
291 DEVICE_DESC_PARAM_HPB_VER 286 DEVICE_DESC_PARAM_HPB_VER = 0x40,
292 DEVICE_DESC_PARAM_HPB_CONTROL 287 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
293 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP 288 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
294 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN 289 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
295 DEVICE_DESC_PARAM_WB_TYPE 290 DEVICE_DESC_PARAM_WB_TYPE = 0x54,
296 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNIT 291 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
297 }; 292 };
298 293
299 /* Interconnect descriptor parameters offsets 294 /* Interconnect descriptor parameters offsets in bytes*/
300 enum interconnect_desc_param { 295 enum interconnect_desc_param {
301 INTERCONNECT_DESC_PARAM_LEN 296 INTERCONNECT_DESC_PARAM_LEN = 0x0,
302 INTERCONNECT_DESC_PARAM_TYPE 297 INTERCONNECT_DESC_PARAM_TYPE = 0x1,
303 INTERCONNECT_DESC_PARAM_UNIPRO_VER 298 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
304 INTERCONNECT_DESC_PARAM_MPHY_VER 299 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
305 }; 300 };
306 301
307 /* Geometry descriptor parameters offsets in b 302 /* Geometry descriptor parameters offsets in bytes*/
308 enum geometry_desc_param { 303 enum geometry_desc_param {
309 GEOMETRY_DESC_PARAM_LEN 304 GEOMETRY_DESC_PARAM_LEN = 0x0,
310 GEOMETRY_DESC_PARAM_TYPE 305 GEOMETRY_DESC_PARAM_TYPE = 0x1,
311 GEOMETRY_DESC_PARAM_DEV_CAP 306 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
312 GEOMETRY_DESC_PARAM_MAX_NUM_LUN 307 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
313 GEOMETRY_DESC_PARAM_SEG_SIZE 308 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
314 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE 309 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
315 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE 310 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
316 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE 311 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
317 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE 312 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
318 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE 313 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
319 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE 314 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
320 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE 315 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
321 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC 316 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
322 GEOMETRY_DESC_PARAM_DATA_ORDER 317 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
323 GEOMETRY_DESC_PARAM_MAX_NUM_CTX 318 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
324 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE 319 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
325 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE 320 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
326 GEOMETRY_DESC_PARAM_SEC_RM_TYPES 321 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
327 GEOMETRY_DESC_PARAM_MEM_TYPES 322 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
328 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS 323 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
329 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR 324 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
330 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS 325 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
331 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR 326 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
332 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS 327 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
333 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR 328 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
334 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS 329 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
335 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR 330 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
336 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS 331 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
337 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR 332 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
338 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS 333 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
339 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR 334 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
340 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE 335 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
341 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE 336 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
342 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU 337 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
343 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE 338 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
344 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REG 339 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
345 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS 340 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
346 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS 341 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
347 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ 342 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
348 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE 343 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
349 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE 344 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
350 }; 345 };
351 346
352 /* Health descriptor parameters offsets in byt 347 /* Health descriptor parameters offsets in bytes*/
353 enum health_desc_param { 348 enum health_desc_param {
354 HEALTH_DESC_PARAM_LEN 349 HEALTH_DESC_PARAM_LEN = 0x0,
355 HEALTH_DESC_PARAM_TYPE 350 HEALTH_DESC_PARAM_TYPE = 0x1,
356 HEALTH_DESC_PARAM_EOL_INFO 351 HEALTH_DESC_PARAM_EOL_INFO = 0x2,
357 HEALTH_DESC_PARAM_LIFE_TIME_EST_A 352 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
358 HEALTH_DESC_PARAM_LIFE_TIME_EST_B 353 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
359 }; 354 };
360 355
361 /* WriteBooster buffer mode */ 356 /* WriteBooster buffer mode */
362 enum { 357 enum {
363 WB_BUF_MODE_LU_DEDICATED = 0x0, 358 WB_BUF_MODE_LU_DEDICATED = 0x0,
364 WB_BUF_MODE_SHARED = 0x1, 359 WB_BUF_MODE_SHARED = 0x1,
365 }; 360 };
366 361
367 /* 362 /*
368 * Logical Unit Write Protect 363 * Logical Unit Write Protect
369 * 00h: LU not write protected 364 * 00h: LU not write protected
370 * 01h: LU write protected when fPowerOnWPEn = 365 * 01h: LU write protected when fPowerOnWPEn =1
371 * 02h: LU permanently write protected when fP 366 * 02h: LU permanently write protected when fPermanentWPEn =1
372 */ 367 */
373 enum ufs_lu_wp_type { 368 enum ufs_lu_wp_type {
374 UFS_LU_NO_WP = 0x00, 369 UFS_LU_NO_WP = 0x00,
375 UFS_LU_POWER_ON_WP = 0x01, 370 UFS_LU_POWER_ON_WP = 0x01,
376 UFS_LU_PERM_WP = 0x02, 371 UFS_LU_PERM_WP = 0x02,
377 }; 372 };
378 373
379 /* bActiveICCLevel parameter current units */ 374 /* bActiveICCLevel parameter current units */
380 enum { 375 enum {
381 UFSHCD_NANO_AMP = 0, 376 UFSHCD_NANO_AMP = 0,
382 UFSHCD_MICRO_AMP = 1, 377 UFSHCD_MICRO_AMP = 1,
383 UFSHCD_MILI_AMP = 2, 378 UFSHCD_MILI_AMP = 2,
384 UFSHCD_AMP = 3, 379 UFSHCD_AMP = 3,
385 }; 380 };
386 381
387 /* Possible values for dExtendedUFSFeaturesSup 382 /* Possible values for dExtendedUFSFeaturesSupport */
388 enum { 383 enum {
389 UFS_DEV_LOW_TEMP_NOTIF = BIT( 384 UFS_DEV_LOW_TEMP_NOTIF = BIT(4),
390 UFS_DEV_HIGH_TEMP_NOTIF = BIT( 385 UFS_DEV_HIGH_TEMP_NOTIF = BIT(5),
391 UFS_DEV_EXT_TEMP_NOTIF = BIT( 386 UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
392 UFS_DEV_HPB_SUPPORT = BIT( 387 UFS_DEV_HPB_SUPPORT = BIT(7),
393 UFS_DEV_WRITE_BOOSTER_SUP = BIT( 388 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
394 UFS_DEV_EXT_IID_SUP = BIT( 389 UFS_DEV_EXT_IID_SUP = BIT(16),
395 }; 390 };
396 #define UFS_DEV_HPB_SUPPORT_VERSION 391 #define UFS_DEV_HPB_SUPPORT_VERSION 0x310
397 392
398 #define POWER_DESC_MAX_ACTV_ICC_LVLS 393 #define POWER_DESC_MAX_ACTV_ICC_LVLS 16
399 394
400 /* Attribute bActiveICCLevel parameter bit ma 395 /* Attribute bActiveICCLevel parameter bit masks definitions */
401 #define ATTR_ICC_LVL_UNIT_OFFSET 14 396 #define ATTR_ICC_LVL_UNIT_OFFSET 14
402 #define ATTR_ICC_LVL_UNIT_MASK (0x3 < 397 #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
403 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF 398 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF
404 399
405 /* Power descriptor parameters offsets in byte 400 /* Power descriptor parameters offsets in bytes */
406 enum power_desc_param_offset { 401 enum power_desc_param_offset {
407 PWR_DESC_LEN = 0x0, 402 PWR_DESC_LEN = 0x0,
408 PWR_DESC_TYPE = 0x1, 403 PWR_DESC_TYPE = 0x1,
409 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2, 404 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
410 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22 405 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
411 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42 406 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
412 }; 407 };
413 408
414 /* Exception event mask values */ 409 /* Exception event mask values */
415 enum { 410 enum {
416 MASK_EE_STATUS = 0xFF 411 MASK_EE_STATUS = 0xFFFF,
417 MASK_EE_DYNCAP_EVENT = BIT( 412 MASK_EE_DYNCAP_EVENT = BIT(0),
418 MASK_EE_SYSPOOL_EVENT = BIT( 413 MASK_EE_SYSPOOL_EVENT = BIT(1),
419 MASK_EE_URGENT_BKOPS = BIT( 414 MASK_EE_URGENT_BKOPS = BIT(2),
420 MASK_EE_TOO_HIGH_TEMP = BIT( 415 MASK_EE_TOO_HIGH_TEMP = BIT(3),
421 MASK_EE_TOO_LOW_TEMP = BIT( 416 MASK_EE_TOO_LOW_TEMP = BIT(4),
422 MASK_EE_WRITEBOOSTER_EVENT = BIT( 417 MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
423 MASK_EE_PERFORMANCE_THROTTLING = BIT( 418 MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
424 }; 419 };
425 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_ 420 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
426 421
427 /* Background operation status */ 422 /* Background operation status */
428 enum bkops_status { 423 enum bkops_status {
429 BKOPS_STATUS_NO_OP = 0x0 424 BKOPS_STATUS_NO_OP = 0x0,
430 BKOPS_STATUS_NON_CRITICAL = 0x1 425 BKOPS_STATUS_NON_CRITICAL = 0x1,
431 BKOPS_STATUS_PERF_IMPACT = 0x2 426 BKOPS_STATUS_PERF_IMPACT = 0x2,
432 BKOPS_STATUS_CRITICAL = 0x3 427 BKOPS_STATUS_CRITICAL = 0x3,
433 BKOPS_STATUS_MAX = BKO 428 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
434 }; 429 };
435 430
436 /* UTP QUERY Transaction Specific Fields OpCod 431 /* UTP QUERY Transaction Specific Fields OpCode */
437 enum query_opcode { 432 enum query_opcode {
438 UPIU_QUERY_OPCODE_NOP = 0x0, 433 UPIU_QUERY_OPCODE_NOP = 0x0,
439 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 434 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
440 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 435 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
441 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 436 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
442 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 437 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
443 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 438 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
444 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 439 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
445 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 440 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
446 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 441 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
447 }; 442 };
448 443
449 /* bRefClkFreq attribute values */ 444 /* bRefClkFreq attribute values */
450 enum ufs_ref_clk_freq { 445 enum ufs_ref_clk_freq {
451 REF_CLK_FREQ_19_2_MHZ = 0, 446 REF_CLK_FREQ_19_2_MHZ = 0,
452 REF_CLK_FREQ_26_MHZ = 1, 447 REF_CLK_FREQ_26_MHZ = 1,
453 REF_CLK_FREQ_38_4_MHZ = 2, 448 REF_CLK_FREQ_38_4_MHZ = 2,
454 REF_CLK_FREQ_52_MHZ = 3, 449 REF_CLK_FREQ_52_MHZ = 3,
455 REF_CLK_FREQ_INVAL = -1, 450 REF_CLK_FREQ_INVAL = -1,
456 }; 451 };
457 452
458 /* Query response result code */ 453 /* Query response result code */
459 enum { 454 enum {
460 QUERY_RESULT_SUCCESS 455 QUERY_RESULT_SUCCESS = 0x00,
461 QUERY_RESULT_NOT_READABLE 456 QUERY_RESULT_NOT_READABLE = 0xF6,
462 QUERY_RESULT_NOT_WRITEABLE 457 QUERY_RESULT_NOT_WRITEABLE = 0xF7,
463 QUERY_RESULT_ALREADY_WRITTEN 458 QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
464 QUERY_RESULT_INVALID_LENGTH 459 QUERY_RESULT_INVALID_LENGTH = 0xF9,
465 QUERY_RESULT_INVALID_VALUE 460 QUERY_RESULT_INVALID_VALUE = 0xFA,
466 QUERY_RESULT_INVALID_SELECTOR 461 QUERY_RESULT_INVALID_SELECTOR = 0xFB,
467 QUERY_RESULT_INVALID_INDEX 462 QUERY_RESULT_INVALID_INDEX = 0xFC,
468 QUERY_RESULT_INVALID_IDN 463 QUERY_RESULT_INVALID_IDN = 0xFD,
469 QUERY_RESULT_INVALID_OPCODE 464 QUERY_RESULT_INVALID_OPCODE = 0xFE,
470 QUERY_RESULT_GENERAL_FAILURE 465 QUERY_RESULT_GENERAL_FAILURE = 0xFF,
471 }; 466 };
472 467
473 /* UTP Transfer Request Command Type (CT) */ 468 /* UTP Transfer Request Command Type (CT) */
474 enum { 469 enum {
475 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 470 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
476 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 471 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
477 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 472 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
478 }; 473 };
479 474
>> 475 /* UTP Transfer Request Command Offset */
>> 476 #define UPIU_COMMAND_TYPE_OFFSET 28
>> 477
480 /* Offset of the response code in the UPIU hea 478 /* Offset of the response code in the UPIU header */
481 #define UPIU_RSP_CODE_OFFSET 8 479 #define UPIU_RSP_CODE_OFFSET 8
482 480
483 enum { 481 enum {
>> 482 MASK_SCSI_STATUS = 0xFF,
>> 483 MASK_TASK_RESPONSE = 0xFF00,
>> 484 MASK_RSP_UPIU_RESULT = 0xFFFF,
>> 485 MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
>> 486 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
>> 487 MASK_RSP_EXCEPTION_EVENT = 0x10000,
484 MASK_TM_SERVICE_RESP = 0xFF 488 MASK_TM_SERVICE_RESP = 0xFF,
>> 489 MASK_TM_FUNC = 0xFF,
485 }; 490 };
486 491
487 /* Task management service response */ 492 /* Task management service response */
488 enum { 493 enum {
489 UPIU_TASK_MANAGEMENT_FUNC_COMPL 494 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
490 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTE 495 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
491 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED 496 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
492 UPIU_TASK_MANAGEMENT_FUNC_FAILED 497 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
493 UPIU_INCORRECT_LOGICAL_UNIT_NO 498 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
494 }; 499 };
495 500
496 /* UFS device power modes */ 501 /* UFS device power modes */
497 enum ufs_dev_pwr_mode { 502 enum ufs_dev_pwr_mode {
498 UFS_ACTIVE_PWR_MODE = 1, 503 UFS_ACTIVE_PWR_MODE = 1,
499 UFS_SLEEP_PWR_MODE = 2, 504 UFS_SLEEP_PWR_MODE = 2,
500 UFS_POWERDOWN_PWR_MODE = 3, 505 UFS_POWERDOWN_PWR_MODE = 3,
501 UFS_DEEPSLEEP_PWR_MODE = 4, 506 UFS_DEEPSLEEP_PWR_MODE = 4,
502 }; 507 };
503 508
504 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) 509 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
505 510
506 /** 511 /**
507 * struct utp_cmd_rsp - Response UPIU structur 512 * struct utp_cmd_rsp - Response UPIU structure
508 * @residual_transfer_count: Residual transfer 513 * @residual_transfer_count: Residual transfer count DW-3
509 * @reserved: Reserved double words DW-4 to DW 514 * @reserved: Reserved double words DW-4 to DW-7
510 * @sense_data_len: Sense data length DW-8 U16 515 * @sense_data_len: Sense data length DW-8 U16
511 * @sense_data: Sense data field DW-8 to DW-12 516 * @sense_data: Sense data field DW-8 to DW-12
512 */ 517 */
513 struct utp_cmd_rsp { 518 struct utp_cmd_rsp {
514 __be32 residual_transfer_count; 519 __be32 residual_transfer_count;
515 __be32 reserved[4]; 520 __be32 reserved[4];
516 __be16 sense_data_len; 521 __be16 sense_data_len;
517 u8 sense_data[UFS_SENSE_SIZE]; 522 u8 sense_data[UFS_SENSE_SIZE];
518 }; 523 };
519 524
>> 525 struct ufshpb_active_field {
>> 526 __be16 active_rgn;
>> 527 __be16 active_srgn;
>> 528 };
>> 529 #define HPB_ACT_FIELD_SIZE 4
>> 530
>> 531 /**
>> 532 * struct utp_hpb_rsp - Response UPIU structure
>> 533 * @residual_transfer_count: Residual transfer count DW-3
>> 534 * @reserved1: Reserved double words DW-4 to DW-7
>> 535 * @sense_data_len: Sense data length DW-8 U16
>> 536 * @desc_type: Descriptor type of sense data
>> 537 * @additional_len: Additional length of sense data
>> 538 * @hpb_op: HPB operation type
>> 539 * @lun: LUN of response UPIU
>> 540 * @active_rgn_cnt: Active region count
>> 541 * @inactive_rgn_cnt: Inactive region count
>> 542 * @hpb_active_field: Recommended to read HPB region and subregion
>> 543 * @hpb_inactive_field: To be inactivated HPB region and subregion
>> 544 */
>> 545 struct utp_hpb_rsp {
>> 546 __be32 residual_transfer_count;
>> 547 __be32 reserved1[4];
>> 548 __be16 sense_data_len;
>> 549 u8 desc_type;
>> 550 u8 additional_len;
>> 551 u8 hpb_op;
>> 552 u8 lun;
>> 553 u8 active_rgn_cnt;
>> 554 u8 inactive_rgn_cnt;
>> 555 struct ufshpb_active_field hpb_active_field[2];
>> 556 __be16 hpb_inactive_field[2];
>> 557 };
>> 558 #define UTP_HPB_RSP_SIZE 40
>> 559
520 /** 560 /**
521 * struct utp_upiu_rsp - general upiu response 561 * struct utp_upiu_rsp - general upiu response structure
522 * @header: UPIU header structure DW-0 to DW-2 562 * @header: UPIU header structure DW-0 to DW-2
523 * @sr: fields structure for scsi command DW-3 563 * @sr: fields structure for scsi command DW-3 to DW-12
524 * @qr: fields structure for query request DW- 564 * @qr: fields structure for query request DW-3 to DW-7
525 */ 565 */
526 struct utp_upiu_rsp { 566 struct utp_upiu_rsp {
527 struct utp_upiu_header header; 567 struct utp_upiu_header header;
528 union { 568 union {
529 struct utp_cmd_rsp sr; 569 struct utp_cmd_rsp sr;
>> 570 struct utp_hpb_rsp hr;
530 struct utp_upiu_query qr; 571 struct utp_upiu_query qr;
531 }; 572 };
532 }; 573 };
533 574
>> 575 /**
>> 576 * struct ufs_query_req - parameters for building a query request
>> 577 * @query_func: UPIU header query function
>> 578 * @upiu_req: the query request data
>> 579 */
>> 580 struct ufs_query_req {
>> 581 u8 query_func;
>> 582 struct utp_upiu_query upiu_req;
>> 583 };
>> 584
>> 585 /**
>> 586 * struct ufs_query_resp - UPIU QUERY
>> 587 * @response: device response code
>> 588 * @upiu_res: query response data
>> 589 */
>> 590 struct ufs_query_res {
>> 591 u8 response;
>> 592 struct utp_upiu_query upiu_res;
>> 593 };
>> 594
534 /* 595 /*
535 * VCCQ & VCCQ2 current requirement when UFS d 596 * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
536 * and link is in Hibern8 state. 597 * and link is in Hibern8 state.
537 */ 598 */
538 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */ 599 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
539 600
540 struct ufs_vreg { 601 struct ufs_vreg {
541 struct regulator *reg; 602 struct regulator *reg;
542 const char *name; 603 const char *name;
543 bool always_on; 604 bool always_on;
544 bool enabled; 605 bool enabled;
545 int max_uA; 606 int max_uA;
546 }; 607 };
547 608
548 struct ufs_vreg_info { 609 struct ufs_vreg_info {
549 struct ufs_vreg *vcc; 610 struct ufs_vreg *vcc;
550 struct ufs_vreg *vccq; 611 struct ufs_vreg *vccq;
551 struct ufs_vreg *vccq2; 612 struct ufs_vreg *vccq2;
552 struct ufs_vreg *vdd_hba; 613 struct ufs_vreg *vdd_hba;
553 }; 614 };
554 615
555 /* UFS device descriptor wPeriodicRTCUpdate bi <<
556 #define UFS_RTC_TIME_BASELINE BIT(9) <<
557 <<
558 enum ufs_rtc_time { <<
559 UFS_RTC_RELATIVE, <<
560 UFS_RTC_ABSOLUTE <<
561 }; <<
562 <<
563 struct ufs_dev_info { 616 struct ufs_dev_info {
564 bool f_power_on_wp_en; 617 bool f_power_on_wp_en;
565 /* Keeps information if any of the LU 618 /* Keeps information if any of the LU is power on write protected */
566 bool is_lu_power_on_wp; 619 bool is_lu_power_on_wp;
567 /* Maximum number of general LU suppor 620 /* Maximum number of general LU supported by the UFS device */
568 u8 max_lu_supported; 621 u8 max_lu_supported;
569 u16 wmanufacturerid; 622 u16 wmanufacturerid;
570 /*UFS device Product Name */ 623 /*UFS device Product Name */
571 u8 *model; 624 u8 *model;
572 u16 wspecversion; 625 u16 wspecversion;
573 u32 clk_gating_wait_us; 626 u32 clk_gating_wait_us;
574 /* Stores the depth of queue in UFS de 627 /* Stores the depth of queue in UFS device */
575 u8 bqueuedepth; 628 u8 bqueuedepth;
576 629
>> 630 /* UFS HPB related flag */
>> 631 bool hpb_enabled;
>> 632
577 /* UFS WB related flags */ 633 /* UFS WB related flags */
578 bool wb_enabled; 634 bool wb_enabled;
579 bool wb_buf_flush_enabled; 635 bool wb_buf_flush_enabled;
580 u8 wb_dedicated_lu; 636 u8 wb_dedicated_lu;
581 u8 wb_buffer_type; 637 u8 wb_buffer_type;
582 638
583 bool b_rpm_dev_flush_capable; 639 bool b_rpm_dev_flush_capable;
584 u8 b_presrv_uspc_en; 640 u8 b_presrv_uspc_en;
585 641
586 bool b_advanced_rpmb_en; 642 bool b_advanced_rpmb_en;
587 643
588 /* UFS EXT_IID Enable */ 644 /* UFS EXT_IID Enable */
589 bool b_ext_iid_en; 645 bool b_ext_iid_en;
590 <<
591 /* UFS RTC */ <<
592 enum ufs_rtc_time rtc_type; <<
593 time64_t rtc_time_baseline; <<
594 u32 rtc_update_period; <<
595 <<
596 u8 rtt_cap; /* bDeviceRTTCap */ <<
597 }; 646 };
598 647
599 /* 648 /*
600 * This enum is used in string mapping in incl 649 * This enum is used in string mapping in include/trace/events/ufs.h.
601 */ 650 */
602 enum ufs_trace_str_t { 651 enum ufs_trace_str_t {
603 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_CO 652 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
604 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QU 653 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
605 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR 654 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
606 }; 655 };
607 656
608 /* 657 /*
609 * Transaction Specific Fields (TSF) type in t 658 * Transaction Specific Fields (TSF) type in the UPIU package, this enum is
610 * used in include/trace/events/ufs.h for UFS 659 * used in include/trace/events/ufs.h for UFS command trace.
611 */ 660 */
612 enum ufs_trace_tsf_t { 661 enum ufs_trace_tsf_t {
613 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_I 662 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
614 }; 663 };
615 664
616 #endif /* End of Header */ 665 #endif /* End of Header */
617 666
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