1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Universal Flash Storage Host controller dri 3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Softw 4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * 5 *
6 * Authors: 6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung 7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.c 8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */ 9 */
10 10
11 #ifndef _UFSHCI_H 11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H 12 #define _UFSHCI_H
13 13
14 #include <linux/types.h> 14 #include <linux/types.h>
15 #include <ufs/ufs.h> 15 #include <ufs/ufs.h>
16 16
17 enum { 17 enum {
18 TASK_REQ_UPIU_SIZE_DWORDS = 8, 18 TASK_REQ_UPIU_SIZE_DWORDS = 8,
19 TASK_RSP_UPIU_SIZE_DWORDS = 8, 19 TASK_RSP_UPIU_SIZE_DWORDS = 8,
20 ALIGNED_UPIU_SIZE = 512, 20 ALIGNED_UPIU_SIZE = 512,
21 }; 21 };
22 22
23 /* UFSHCI Registers */ 23 /* UFSHCI Registers */
24 enum { 24 enum {
25 REG_CONTROLLER_CAPABILITIES 25 REG_CONTROLLER_CAPABILITIES = 0x00,
26 REG_MCQCAP 26 REG_MCQCAP = 0x04,
27 REG_UFS_VERSION 27 REG_UFS_VERSION = 0x08,
28 REG_EXT_CONTROLLER_CAPABILITIES !! 28 REG_CONTROLLER_DEV_ID = 0x10,
29 REG_CONTROLLER_PID !! 29 REG_CONTROLLER_PROD_ID = 0x14,
30 REG_CONTROLLER_MID <<
31 REG_AUTO_HIBERNATE_IDLE_TIMER 30 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
32 REG_INTERRUPT_STATUS 31 REG_INTERRUPT_STATUS = 0x20,
33 REG_INTERRUPT_ENABLE 32 REG_INTERRUPT_ENABLE = 0x24,
34 REG_CONTROLLER_STATUS 33 REG_CONTROLLER_STATUS = 0x30,
35 REG_CONTROLLER_ENABLE 34 REG_CONTROLLER_ENABLE = 0x34,
36 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER 35 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
37 REG_UIC_ERROR_CODE_DATA_LINK_LAYER 36 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
38 REG_UIC_ERROR_CODE_NETWORK_LAYER 37 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
39 REG_UIC_ERROR_CODE_TRANSPORT_LAYER 38 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
40 REG_UIC_ERROR_CODE_DME 39 REG_UIC_ERROR_CODE_DME = 0x48,
41 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL 40 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
42 REG_UTP_TRANSFER_REQ_LIST_BASE_L 41 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
43 REG_UTP_TRANSFER_REQ_LIST_BASE_H 42 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
44 REG_UTP_TRANSFER_REQ_DOOR_BELL 43 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
45 REG_UTP_TRANSFER_REQ_LIST_CLEAR 44 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
46 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP 45 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
47 REG_UTP_TASK_REQ_LIST_BASE_L 46 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
48 REG_UTP_TASK_REQ_LIST_BASE_H 47 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
49 REG_UTP_TASK_REQ_DOOR_BELL 48 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
50 REG_UTP_TASK_REQ_LIST_CLEAR 49 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
51 REG_UTP_TASK_REQ_LIST_RUN_STOP 50 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
52 REG_UIC_COMMAND 51 REG_UIC_COMMAND = 0x90,
53 REG_UIC_COMMAND_ARG_1 52 REG_UIC_COMMAND_ARG_1 = 0x94,
54 REG_UIC_COMMAND_ARG_2 53 REG_UIC_COMMAND_ARG_2 = 0x98,
55 REG_UIC_COMMAND_ARG_3 54 REG_UIC_COMMAND_ARG_3 = 0x9C,
56 55
57 UFSHCI_REG_SPACE_SIZE 56 UFSHCI_REG_SPACE_SIZE = 0xA0,
58 57
59 REG_UFS_CCAP 58 REG_UFS_CCAP = 0x100,
60 REG_UFS_CRYPTOCAP 59 REG_UFS_CRYPTOCAP = 0x104,
61 60
62 REG_UFS_MEM_CFG 61 REG_UFS_MEM_CFG = 0x300,
63 REG_UFS_MCQ_CFG 62 REG_UFS_MCQ_CFG = 0x380,
64 REG_UFS_ESILBA 63 REG_UFS_ESILBA = 0x384,
65 REG_UFS_ESIUBA 64 REG_UFS_ESIUBA = 0x388,
66 UFSHCI_CRYPTO_REG_SPACE_SIZE 65 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
67 }; 66 };
68 67
69 /* Controller capability masks */ 68 /* Controller capability masks */
70 enum { 69 enum {
71 MASK_TRANSFER_REQUESTS_SLOTS_SDB !! 70 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
72 MASK_TRANSFER_REQUESTS_SLOTS_MCQ <<
73 MASK_NUMBER_OUTSTANDING_RTT <<
74 MASK_TASK_MANAGEMENT_REQUEST_SLOTS 71 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
75 MASK_EHSLUTRD_SUPPORTED 72 MASK_EHSLUTRD_SUPPORTED = 0x00400000,
76 MASK_AUTO_HIBERN8_SUPPORT 73 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
77 MASK_64_ADDRESSING_SUPPORT 74 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
78 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPOR 75 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
79 MASK_UIC_DME_TEST_MODE_SUPPORT 76 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
80 MASK_CRYPTO_SUPPORT 77 MASK_CRYPTO_SUPPORT = 0x10000000,
81 MASK_LSDB_SUPPORT <<
82 MASK_MCQ_SUPPORT 78 MASK_MCQ_SUPPORT = 0x40000000,
83 }; 79 };
84 80
85 /* MCQ capability mask */ 81 /* MCQ capability mask */
86 enum { 82 enum {
87 MASK_EXT_IID_SUPPORT = 0x00000400, 83 MASK_EXT_IID_SUPPORT = 0x00000400,
88 }; 84 };
89 85
90 enum { 86 enum {
91 REG_SQATTR = 0x0, 87 REG_SQATTR = 0x0,
92 REG_SQLBA = 0x4, 88 REG_SQLBA = 0x4,
93 REG_SQUBA = 0x8, 89 REG_SQUBA = 0x8,
94 REG_SQDAO = 0xC, 90 REG_SQDAO = 0xC,
95 REG_SQISAO = 0x10, 91 REG_SQISAO = 0x10,
96 92
97 REG_CQATTR = 0x20, 93 REG_CQATTR = 0x20,
98 REG_CQLBA = 0x24, 94 REG_CQLBA = 0x24,
99 REG_CQUBA = 0x28, 95 REG_CQUBA = 0x28,
100 REG_CQDAO = 0x2C, 96 REG_CQDAO = 0x2C,
101 REG_CQISAO = 0x30, 97 REG_CQISAO = 0x30,
102 }; 98 };
103 99
104 enum { 100 enum {
105 REG_SQHP = 0x0, 101 REG_SQHP = 0x0,
106 REG_SQTP = 0x4, 102 REG_SQTP = 0x4,
107 REG_SQRTC = 0x8, 103 REG_SQRTC = 0x8,
108 REG_SQCTI = 0xC, 104 REG_SQCTI = 0xC,
109 REG_SQRTS = 0x10, 105 REG_SQRTS = 0x10,
110 }; 106 };
111 107
112 enum { 108 enum {
113 REG_CQHP = 0x0, 109 REG_CQHP = 0x0,
114 REG_CQTP = 0x4, 110 REG_CQTP = 0x4,
115 }; 111 };
116 112
117 enum { 113 enum {
118 REG_CQIS = 0x0, 114 REG_CQIS = 0x0,
119 REG_CQIE = 0x4, 115 REG_CQIE = 0x4,
120 }; 116 };
121 117
122 enum { 118 enum {
123 SQ_START = 0x0, 119 SQ_START = 0x0,
124 SQ_STOP = 0x1, 120 SQ_STOP = 0x1,
125 SQ_ICU = 0x2, 121 SQ_ICU = 0x2,
126 }; 122 };
127 123
128 enum { 124 enum {
129 SQ_STS = 0x1, 125 SQ_STS = 0x1,
130 SQ_CUS = 0x2, 126 SQ_CUS = 0x2,
131 }; 127 };
132 128
133 #define SQ_ICU_ERR_CODE_MASK GENMAS 129 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
134 #define UFS_MASK(mask, offset) ((mask 130 #define UFS_MASK(mask, offset) ((mask) << (offset))
135 131
136 /* UFS Version 08h */ 132 /* UFS Version 08h */
137 #define MINOR_VERSION_NUM_MASK UFS_MA 133 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
138 #define MAJOR_VERSION_NUM_MASK UFS_MA 134 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
139 135
140 #define UFSHCD_NUM_RESERVED 1 136 #define UFSHCD_NUM_RESERVED 1
141 /* 137 /*
142 * Controller UFSHCI version 138 * Controller UFSHCI version
143 * - 2.x and newer use the following scheme: 139 * - 2.x and newer use the following scheme:
144 * major << 8 + minor << 4 140 * major << 8 + minor << 4
145 * - 1.x has been converted to match this in 141 * - 1.x has been converted to match this in
146 * ufshcd_get_ufs_version() 142 * ufshcd_get_ufs_version()
147 */ 143 */
148 static inline u32 ufshci_version(u32 major, u3 144 static inline u32 ufshci_version(u32 major, u32 minor)
149 { 145 {
150 return (major << 8) + (minor << 4); 146 return (major << 8) + (minor << 4);
151 } 147 }
152 148
153 /* 149 /*
154 * HCDDID - Host Controller Identification Des 150 * HCDDID - Host Controller Identification Descriptor
155 * - Device ID and Device Class 10h 151 * - Device ID and Device Class 10h
156 */ 152 */
157 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 153 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
158 #define DEVICE_ID UFS_MASK(0xFF, 24) 154 #define DEVICE_ID UFS_MASK(0xFF, 24)
159 155
160 /* 156 /*
161 * HCPMID - Host Controller Identification Des 157 * HCPMID - Host Controller Identification Descriptor
162 * - Product/Manufacturer ID 14h 158 * - Product/Manufacturer ID 14h
163 */ 159 */
164 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFF 160 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
165 #define PRODUCT_ID_MASK UFS_MASK(0xFFF 161 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
166 162
167 /* AHIT - Auto-Hibernate Idle Timer */ 163 /* AHIT - Auto-Hibernate Idle Timer */
168 #define UFSHCI_AHIBERN8_TIMER_MASK 164 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
169 #define UFSHCI_AHIBERN8_SCALE_MASK 165 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
170 #define UFSHCI_AHIBERN8_SCALE_FACTOR 166 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
171 #define UFSHCI_AHIBERN8_MAX 167 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
172 168
173 /* 169 /*
174 * IS - Interrupt Status - 20h 170 * IS - Interrupt Status - 20h
175 */ 171 */
176 #define UTP_TRANSFER_REQ_COMPL 172 #define UTP_TRANSFER_REQ_COMPL 0x1
177 #define UIC_DME_END_PT_RESET 173 #define UIC_DME_END_PT_RESET 0x2
178 #define UIC_ERROR 174 #define UIC_ERROR 0x4
179 #define UIC_TEST_MODE 175 #define UIC_TEST_MODE 0x8
180 #define UIC_POWER_MODE 176 #define UIC_POWER_MODE 0x10
181 #define UIC_HIBERNATE_EXIT 177 #define UIC_HIBERNATE_EXIT 0x20
182 #define UIC_HIBERNATE_ENTER 178 #define UIC_HIBERNATE_ENTER 0x40
183 #define UIC_LINK_LOST 179 #define UIC_LINK_LOST 0x80
184 #define UIC_LINK_STARTUP 180 #define UIC_LINK_STARTUP 0x100
185 #define UTP_TASK_REQ_COMPL 181 #define UTP_TASK_REQ_COMPL 0x200
186 #define UIC_COMMAND_COMPL 182 #define UIC_COMMAND_COMPL 0x400
187 #define DEVICE_FATAL_ERROR 183 #define DEVICE_FATAL_ERROR 0x800
188 #define CONTROLLER_FATAL_ERROR 184 #define CONTROLLER_FATAL_ERROR 0x10000
189 #define SYSTEM_BUS_FATAL_ERROR 185 #define SYSTEM_BUS_FATAL_ERROR 0x20000
190 #define CRYPTO_ENGINE_FATAL_ERROR 186 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
191 #define MCQ_CQ_EVENT_STATUS 187 #define MCQ_CQ_EVENT_STATUS 0x100000
192 188
193 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE 189 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
194 UIC_HIBERNATE_ 190 UIC_HIBERNATE_EXIT)
195 191
196 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HI 192 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
197 UIC_POWER_MODE 193 UIC_POWER_MODE)
198 194
199 #define UFSHCD_UIC_MASK (UIC_COMMAND_C 195 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
200 196
201 #define UFSHCD_ERROR_MASK (UIC_ERROR | I 197 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
202 198
203 #define INT_FATAL_ERRORS (DEVICE_FATAL_ 199 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
204 CONTROLLER_FAT 200 CONTROLLER_FATAL_ERROR |\
205 SYSTEM_BUS_FAT 201 SYSTEM_BUS_FATAL_ERROR |\
206 CRYPTO_ENGINE_ 202 CRYPTO_ENGINE_FATAL_ERROR |\
207 UIC_LINK_LOST) 203 UIC_LINK_LOST)
208 204
209 /* HCS - Host Controller Status 30h */ 205 /* HCS - Host Controller Status 30h */
210 #define DEVICE_PRESENT 206 #define DEVICE_PRESENT 0x1
211 #define UTP_TRANSFER_REQ_LIST_READY 207 #define UTP_TRANSFER_REQ_LIST_READY 0x2
212 #define UTP_TASK_REQ_LIST_READY 208 #define UTP_TASK_REQ_LIST_READY 0x4
213 #define UIC_COMMAND_READY 209 #define UIC_COMMAND_READY 0x8
214 #define HOST_ERROR_INDICATOR 210 #define HOST_ERROR_INDICATOR 0x10
215 #define DEVICE_ERROR_INDICATOR 211 #define DEVICE_ERROR_INDICATOR 0x20
216 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK 212 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
217 213
218 #define UFSHCD_STATUS_READY (UTP_TRANSFER_ 214 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
219 UTP_TASK_REQ_L 215 UTP_TASK_REQ_LIST_READY |\
220 UIC_COMMAND_RE 216 UIC_COMMAND_READY)
221 217
222 enum { 218 enum {
223 PWR_OK = 0x0, 219 PWR_OK = 0x0,
224 PWR_LOCAL = 0x01, 220 PWR_LOCAL = 0x01,
225 PWR_REMOTE = 0x02, 221 PWR_REMOTE = 0x02,
226 PWR_BUSY = 0x03, 222 PWR_BUSY = 0x03,
227 PWR_ERROR_CAP = 0x04, 223 PWR_ERROR_CAP = 0x04,
228 PWR_FATAL_ERROR = 0x05, 224 PWR_FATAL_ERROR = 0x05,
229 }; 225 };
230 226
231 /* HCE - Host Controller Enable 34h */ 227 /* HCE - Host Controller Enable 34h */
232 #define CONTROLLER_ENABLE 0x1 228 #define CONTROLLER_ENABLE 0x1
233 #define CONTROLLER_DISABLE 0x0 229 #define CONTROLLER_DISABLE 0x0
234 #define CRYPTO_GENERAL_ENABLE 0x2 230 #define CRYPTO_GENERAL_ENABLE 0x2
235 231
236 /* UECPA - Host UIC Error Code PHY Adapter Lay 232 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
237 #define UIC_PHY_ADAPTER_LAYER_ERROR 233 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
238 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 234 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
239 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 235 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
240 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 236 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
241 237
242 /* UECDL - Host UIC Error Code Data Link Layer 238 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
243 #define UIC_DATA_LINK_LAYER_ERROR 239 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
244 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 240 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
245 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIME 241 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
246 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIM 242 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
247 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIME 243 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
248 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 244 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
249 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 245 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
250 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 246 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
251 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_T 247 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
252 248
253 /* UECN - Host UIC Error Code Network Layer 40 249 /* UECN - Host UIC Error Code Network Layer 40h */
254 #define UIC_NETWORK_LAYER_ERROR 250 #define UIC_NETWORK_LAYER_ERROR 0x80000000
255 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 251 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
256 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 252 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
257 #define UIC_NETWORK_BAD_DEVICEID_ENC 253 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
258 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 254 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
259 255
260 /* UECT - Host UIC Error Code Transport Layer 256 /* UECT - Host UIC Error Code Transport Layer 44h */
261 #define UIC_TRANSPORT_LAYER_ERROR 257 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
262 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 258 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
263 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 259 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
264 #define UIC_TRANSPORT_UNKNOWN_CPORTID 260 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
265 #define UIC_TRANSPORT_NO_CONNECTION_RX 261 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
266 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPP 262 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
267 #define UIC_TRANSPORT_BAD_TC 263 #define UIC_TRANSPORT_BAD_TC 0x10
268 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 264 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
269 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 265 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
270 266
271 /* UECDME - Host UIC Error Code DME 48h */ 267 /* UECDME - Host UIC Error Code DME 48h */
272 #define UIC_DME_ERROR 0x8000 268 #define UIC_DME_ERROR 0x80000000
273 #define UIC_DME_ERROR_CODE_MASK 0x1 269 #define UIC_DME_ERROR_CODE_MASK 0x1
274 270
275 /* UTRIACR - Interrupt Aggregation control reg 271 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
276 #define INT_AGGR_TIMEOUT_VAL_MASK 272 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
277 #define INT_AGGR_COUNTER_THRESHOLD_MASK 273 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
278 #define INT_AGGR_COUNTER_AND_TIMER_RESET 274 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
279 #define INT_AGGR_STATUS_BIT 275 #define INT_AGGR_STATUS_BIT 0x100000
280 #define INT_AGGR_PARAM_WRITE 276 #define INT_AGGR_PARAM_WRITE 0x1000000
281 #define INT_AGGR_ENABLE 277 #define INT_AGGR_ENABLE 0x80000000
282 278
283 /* UTRLRSR - UTP Transfer Request Run-Stop Reg 279 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
284 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 280 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
285 281
286 /* UTMRLRSR - UTP Task Management Request Run- 282 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
287 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 283 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
288 284
289 /* REG_UFS_MEM_CFG - Global Config Registers 3 <<
290 #define MCQ_MODE_SELECT BIT(0) <<
291 <<
292 /* CQISy - CQ y Interrupt Status Register */ 285 /* CQISy - CQ y Interrupt Status Register */
293 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 286 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
294 287
295 /* UICCMD - UIC Command */ 288 /* UICCMD - UIC Command */
296 #define COMMAND_OPCODE_MASK 0xFF 289 #define COMMAND_OPCODE_MASK 0xFF
297 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 290 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
298 291
299 #define MIB_ATTRIBUTE_MASK UFS_MA 292 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
300 #define RESET_LEVEL 0xFF 293 #define RESET_LEVEL 0xFF
301 294
302 #define ATTR_SET_TYPE_MASK UFS_MA 295 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
303 #define CONFIG_RESULT_CODE_MASK 0xFF 296 #define CONFIG_RESULT_CODE_MASK 0xFF
304 #define GENERIC_ERROR_CODE_MASK 0xFF 297 #define GENERIC_ERROR_CODE_MASK 0xFF
305 298
306 /* GenSelectorIndex calculation macros for M-P 299 /* GenSelectorIndex calculation macros for M-PHY attributes */
307 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (l 300 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
308 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (P 301 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
309 302
310 #define UIC_ARG_MIB_SEL(attr, sel) ((((at 303 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
311 ((sel 304 ((sel) & 0xFFFF))
312 #define UIC_ARG_MIB(attr) UIC_AR 305 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
313 #define UIC_ARG_ATTR_TYPE(t) (((t) 306 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
314 #define UIC_GET_ATTR_ID(v) (((v) 307 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
315 308
316 /* Link Status*/ 309 /* Link Status*/
317 enum link_status { 310 enum link_status {
318 UFSHCD_LINK_IS_DOWN = 1, 311 UFSHCD_LINK_IS_DOWN = 1,
319 UFSHCD_LINK_IS_UP = 2, 312 UFSHCD_LINK_IS_UP = 2,
320 }; 313 };
321 314
322 /* UIC Commands */ 315 /* UIC Commands */
323 enum uic_cmd_dme { 316 enum uic_cmd_dme {
324 UIC_CMD_DME_GET = 0x01 317 UIC_CMD_DME_GET = 0x01,
325 UIC_CMD_DME_SET = 0x02 318 UIC_CMD_DME_SET = 0x02,
326 UIC_CMD_DME_PEER_GET = 0x03 319 UIC_CMD_DME_PEER_GET = 0x03,
327 UIC_CMD_DME_PEER_SET = 0x04 320 UIC_CMD_DME_PEER_SET = 0x04,
328 UIC_CMD_DME_POWERON = 0x10 321 UIC_CMD_DME_POWERON = 0x10,
329 UIC_CMD_DME_POWEROFF = 0x11 322 UIC_CMD_DME_POWEROFF = 0x11,
330 UIC_CMD_DME_ENABLE = 0x12 323 UIC_CMD_DME_ENABLE = 0x12,
331 UIC_CMD_DME_RESET = 0x14 324 UIC_CMD_DME_RESET = 0x14,
332 UIC_CMD_DME_END_PT_RST = 0x15 325 UIC_CMD_DME_END_PT_RST = 0x15,
333 UIC_CMD_DME_LINK_STARTUP = 0x16 326 UIC_CMD_DME_LINK_STARTUP = 0x16,
334 UIC_CMD_DME_HIBER_ENTER = 0x17 327 UIC_CMD_DME_HIBER_ENTER = 0x17,
335 UIC_CMD_DME_HIBER_EXIT = 0x18 328 UIC_CMD_DME_HIBER_EXIT = 0x18,
336 UIC_CMD_DME_TEST_MODE = 0x1A 329 UIC_CMD_DME_TEST_MODE = 0x1A,
337 }; 330 };
338 331
339 /* UIC Config result code / Generic error code 332 /* UIC Config result code / Generic error code */
340 enum { 333 enum {
341 UIC_CMD_RESULT_SUCCESS 334 UIC_CMD_RESULT_SUCCESS = 0x00,
342 UIC_CMD_RESULT_INVALID_ATTR 335 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
343 UIC_CMD_RESULT_FAILURE 336 UIC_CMD_RESULT_FAILURE = 0x01,
344 UIC_CMD_RESULT_INVALID_ATTR_VALUE 337 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
345 UIC_CMD_RESULT_READ_ONLY_ATTR 338 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
346 UIC_CMD_RESULT_WRITE_ONLY_ATTR 339 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
347 UIC_CMD_RESULT_BAD_INDEX 340 UIC_CMD_RESULT_BAD_INDEX = 0x05,
348 UIC_CMD_RESULT_LOCKED_ATTR 341 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
349 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX 342 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
350 UIC_CMD_RESULT_PEER_COMM_FAILURE 343 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
351 UIC_CMD_RESULT_BUSY 344 UIC_CMD_RESULT_BUSY = 0x09,
352 UIC_CMD_RESULT_DME_FAILURE 345 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
353 }; 346 };
354 347
355 #define MASK_UIC_COMMAND_RESULT 348 #define MASK_UIC_COMMAND_RESULT 0xFF
356 349
357 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) 350 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
358 #define INT_AGGR_TIMEOUT_VAL(t) (((t) 351 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
359 352
360 /* Interrupt disable masks */ 353 /* Interrupt disable masks */
361 enum { 354 enum {
>> 355 /* Interrupt disable mask for UFSHCI v1.0 */
>> 356 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
>> 357 INTERRUPT_MASK_RW_VER_10 = 0x30000,
>> 358
362 /* Interrupt disable mask for UFSHCI v 359 /* Interrupt disable mask for UFSHCI v1.1 */
363 INTERRUPT_MASK_ALL_VER_11 = 0x31 !! 360 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
364 361
365 /* Interrupt disable mask for UFSHCI v 362 /* Interrupt disable mask for UFSHCI v2.1 */
366 INTERRUPT_MASK_ALL_VER_21 = 0x71 363 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
367 }; 364 };
368 365
369 /* CCAP - Crypto Capability 100h */ 366 /* CCAP - Crypto Capability 100h */
370 union ufs_crypto_capabilities { 367 union ufs_crypto_capabilities {
371 __le32 reg_val; 368 __le32 reg_val;
372 struct { 369 struct {
373 u8 num_crypto_cap; 370 u8 num_crypto_cap;
374 u8 config_count; 371 u8 config_count;
375 u8 reserved; 372 u8 reserved;
376 u8 config_array_ptr; 373 u8 config_array_ptr;
377 }; 374 };
378 }; 375 };
379 376
380 enum ufs_crypto_key_size { 377 enum ufs_crypto_key_size {
381 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 378 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
382 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 379 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
383 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 380 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
384 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 381 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
385 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 382 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
386 }; 383 };
387 384
388 enum ufs_crypto_alg { 385 enum ufs_crypto_alg {
389 UFS_CRYPTO_ALG_AES_XTS 386 UFS_CRYPTO_ALG_AES_XTS = 0x0,
390 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC 387 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
391 UFS_CRYPTO_ALG_AES_ECB 388 UFS_CRYPTO_ALG_AES_ECB = 0x2,
392 UFS_CRYPTO_ALG_ESSIV_AES_CBC 389 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
393 }; 390 };
394 391
395 /* x-CRYPTOCAP - Crypto Capability X */ 392 /* x-CRYPTOCAP - Crypto Capability X */
396 union ufs_crypto_cap_entry { 393 union ufs_crypto_cap_entry {
397 __le32 reg_val; 394 __le32 reg_val;
398 struct { 395 struct {
399 u8 algorithm_id; 396 u8 algorithm_id;
400 u8 sdus_mask; /* Supported dat 397 u8 sdus_mask; /* Supported data unit size mask */
401 u8 key_size; 398 u8 key_size;
402 u8 reserved; 399 u8 reserved;
403 }; 400 };
404 }; 401 };
405 402
406 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 403 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
407 #define UFS_CRYPTO_KEY_MAX_SIZE 64 404 #define UFS_CRYPTO_KEY_MAX_SIZE 64
408 /* x-CRYPTOCFG - Crypto Configuration X */ 405 /* x-CRYPTOCFG - Crypto Configuration X */
409 union ufs_crypto_cfg_entry { 406 union ufs_crypto_cfg_entry {
410 __le32 reg_val[32]; 407 __le32 reg_val[32];
411 struct { 408 struct {
412 u8 crypto_key[UFS_CRYPTO_KEY_M 409 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
413 u8 data_unit_size; 410 u8 data_unit_size;
414 u8 crypto_cap_idx; 411 u8 crypto_cap_idx;
415 u8 reserved_1; 412 u8 reserved_1;
416 u8 config_enable; 413 u8 config_enable;
417 u8 reserved_multi_host; 414 u8 reserved_multi_host;
418 u8 reserved_2; 415 u8 reserved_2;
419 u8 vsb[2]; 416 u8 vsb[2];
420 u8 reserved_3[56]; 417 u8 reserved_3[56];
421 }; 418 };
422 }; 419 };
423 420
424 /* 421 /*
425 * Request Descriptor Definitions 422 * Request Descriptor Definitions
426 */ 423 */
>> 424
>> 425 /* Transfer request command type */
>> 426 enum {
>> 427 UTP_CMD_TYPE_SCSI = 0x0,
>> 428 UTP_CMD_TYPE_UFS = 0x1,
>> 429 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
>> 430 };
427 431
428 /* To accommodate UFS2.0 required Command type 432 /* To accommodate UFS2.0 required Command type */
429 enum { 433 enum {
430 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 434 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
431 }; 435 };
432 436
433 enum { 437 enum {
434 UTP_SCSI_COMMAND = 0x00 438 UTP_SCSI_COMMAND = 0x00000000,
435 UTP_NATIVE_UFS_COMMAND = 0x10 439 UTP_NATIVE_UFS_COMMAND = 0x10000000,
436 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20 440 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
437 }; 441 };
438 442
439 /* UTP Transfer Request Data Direction (DD) */ 443 /* UTP Transfer Request Data Direction (DD) */
440 enum utp_data_direction { 444 enum utp_data_direction {
441 UTP_NO_DATA_TRANSFER = 0, 445 UTP_NO_DATA_TRANSFER = 0,
442 UTP_HOST_TO_DEVICE = 1, 446 UTP_HOST_TO_DEVICE = 1,
443 UTP_DEVICE_TO_HOST = 2, 447 UTP_DEVICE_TO_HOST = 2,
444 }; 448 };
445 449
446 /* Overall command status values */ 450 /* Overall command status values */
447 enum utp_ocs { 451 enum utp_ocs {
448 OCS_SUCCESS = 0x0, 452 OCS_SUCCESS = 0x0,
449 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 453 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
450 OCS_INVALID_PRDT_ATTR = 0x2, 454 OCS_INVALID_PRDT_ATTR = 0x2,
451 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 455 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
452 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 456 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
453 OCS_PEER_COMM_FAILURE = 0x5, 457 OCS_PEER_COMM_FAILURE = 0x5,
454 OCS_ABORTED = 0x6, 458 OCS_ABORTED = 0x6,
455 OCS_FATAL_ERROR = 0x7, 459 OCS_FATAL_ERROR = 0x7,
456 OCS_DEVICE_FATAL_ERROR = 0x8, 460 OCS_DEVICE_FATAL_ERROR = 0x8,
457 OCS_INVALID_CRYPTO_CONFIG = 0x9, 461 OCS_INVALID_CRYPTO_CONFIG = 0x9,
458 OCS_GENERAL_CRYPTO_ERROR = 0xA, 462 OCS_GENERAL_CRYPTO_ERROR = 0xA,
459 OCS_INVALID_COMMAND_STATUS = 0x0F 463 OCS_INVALID_COMMAND_STATUS = 0x0F,
460 }; 464 };
461 465
462 enum { 466 enum {
463 MASK_OCS = 0x0F 467 MASK_OCS = 0x0F,
464 }; 468 };
465 469
466 /* The maximum length of the data byte count f 470 /* The maximum length of the data byte count field in the PRDT is 256KB */
467 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256 471 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
468 /* The granularity of the data byte count fiel 472 /* The granularity of the data byte count field in the PRDT is 32-bit */
469 #define PRDT_DATA_BYTE_COUNT_PAD 4 473 #define PRDT_DATA_BYTE_COUNT_PAD 4
470 474
471 /** 475 /**
472 * struct ufshcd_sg_entry - UFSHCI PRD Entry 476 * struct ufshcd_sg_entry - UFSHCI PRD Entry
473 * @addr: Physical address; DW-0 and DW-1. 477 * @addr: Physical address; DW-0 and DW-1.
474 * @reserved: Reserved for future use DW-2 478 * @reserved: Reserved for future use DW-2
475 * @size: size of physical segment DW-3 479 * @size: size of physical segment DW-3
476 */ 480 */
477 struct ufshcd_sg_entry { 481 struct ufshcd_sg_entry {
478 __le64 addr; 482 __le64 addr;
479 __le32 reserved; 483 __le32 reserved;
480 __le32 size; 484 __le32 size;
481 /* 485 /*
482 * followed by variant-specific fields 486 * followed by variant-specific fields if
483 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_S 487 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
484 */ 488 */
485 }; 489 };
486 490
487 /** 491 /**
488 * struct utp_transfer_cmd_desc - UTP Command 492 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
489 * @command_upiu: Command UPIU Frame address 493 * @command_upiu: Command UPIU Frame address
490 * @response_upiu: Response UPIU Frame address 494 * @response_upiu: Response UPIU Frame address
491 * @prd_table: Physical Region Descriptor: an 495 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
492 * ufshcd_sg_entry's. Variant-specific f 496 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
493 */ 497 */
494 struct utp_transfer_cmd_desc { 498 struct utp_transfer_cmd_desc {
495 u8 command_upiu[ALIGNED_UPIU_SIZE]; 499 u8 command_upiu[ALIGNED_UPIU_SIZE];
496 u8 response_upiu[ALIGNED_UPIU_SIZE]; 500 u8 response_upiu[ALIGNED_UPIU_SIZE];
497 u8 prd_table[]; 501 u8 prd_table[];
498 }; 502 };
499 503
500 /** 504 /**
501 * struct request_desc_header - Descriptor Hea 505 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
502 */ 506 */
503 struct request_desc_header { 507 struct request_desc_header {
504 u8 cci; 508 u8 cci;
505 u8 ehs_length; 509 u8 ehs_length;
506 #if defined(__BIG_ENDIAN) 510 #if defined(__BIG_ENDIAN)
507 u8 enable_crypto:1; 511 u8 enable_crypto:1;
508 u8 reserved2:7; 512 u8 reserved2:7;
509 513
510 u8 command_type:4; 514 u8 command_type:4;
511 u8 reserved1:1; 515 u8 reserved1:1;
512 u8 data_direction:2; 516 u8 data_direction:2;
513 u8 interrupt:1; 517 u8 interrupt:1;
514 #elif defined(__LITTLE_ENDIAN) 518 #elif defined(__LITTLE_ENDIAN)
515 u8 reserved2:7; 519 u8 reserved2:7;
516 u8 enable_crypto:1; 520 u8 enable_crypto:1;
517 521
518 u8 interrupt:1; 522 u8 interrupt:1;
519 u8 data_direction:2; 523 u8 data_direction:2;
520 u8 reserved1:1; 524 u8 reserved1:1;
521 u8 command_type:4; 525 u8 command_type:4;
522 #else 526 #else
523 #error 527 #error
524 #endif 528 #endif
525 529
526 __le32 dunl; 530 __le32 dunl;
527 u8 ocs; 531 u8 ocs;
528 u8 cds; 532 u8 cds;
529 __le16 ldbc; 533 __le16 ldbc;
530 __le32 dunu; 534 __le32 dunu;
531 }; 535 };
532 536
533 static_assert(sizeof(struct request_desc_heade 537 static_assert(sizeof(struct request_desc_header) == 16);
534 538
535 /** 539 /**
536 * struct utp_transfer_req_desc - UTP Transfer 540 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
537 * @header: UTRD header DW-0 to DW-3 541 * @header: UTRD header DW-0 to DW-3
538 * @command_desc_base_addr: UCD base address D 542 * @command_desc_base_addr: UCD base address DW 4-5
539 * @response_upiu_length: response UPIU length 543 * @response_upiu_length: response UPIU length DW-6
540 * @response_upiu_offset: response UPIU offset 544 * @response_upiu_offset: response UPIU offset DW-6
541 * @prd_table_length: Physical region descript 545 * @prd_table_length: Physical region descriptor length DW-7
542 * @prd_table_offset: Physical region descript 546 * @prd_table_offset: Physical region descriptor offset DW-7
543 */ 547 */
544 struct utp_transfer_req_desc { 548 struct utp_transfer_req_desc {
545 549
546 /* DW 0-3 */ 550 /* DW 0-3 */
547 struct request_desc_header header; 551 struct request_desc_header header;
548 552
549 /* DW 4-5*/ 553 /* DW 4-5*/
550 __le64 command_desc_base_addr; 554 __le64 command_desc_base_addr;
551 555
552 /* DW 6 */ 556 /* DW 6 */
553 __le16 response_upiu_length; 557 __le16 response_upiu_length;
554 __le16 response_upiu_offset; 558 __le16 response_upiu_offset;
555 559
556 /* DW 7 */ 560 /* DW 7 */
557 __le16 prd_table_length; 561 __le16 prd_table_length;
558 __le16 prd_table_offset; 562 __le16 prd_table_offset;
559 }; 563 };
560 564
561 /* MCQ Completion Queue Entry */ 565 /* MCQ Completion Queue Entry */
562 struct cq_entry { 566 struct cq_entry {
563 /* DW 0-1 */ 567 /* DW 0-1 */
564 __le64 command_desc_base_addr; 568 __le64 command_desc_base_addr;
565 569
566 /* DW 2 */ 570 /* DW 2 */
567 __le16 response_upiu_length; 571 __le16 response_upiu_length;
568 __le16 response_upiu_offset; 572 __le16 response_upiu_offset;
569 573
570 /* DW 3 */ 574 /* DW 3 */
571 __le16 prd_table_length; 575 __le16 prd_table_length;
572 __le16 prd_table_offset; 576 __le16 prd_table_offset;
573 577
574 /* DW 4 */ 578 /* DW 4 */
575 __le32 status; 579 __le32 status;
576 580
577 /* DW 5-7 */ 581 /* DW 5-7 */
578 __le32 reserved[3]; 582 __le32 reserved[3];
579 }; 583 };
580 584
581 static_assert(sizeof(struct cq_entry) == 32); 585 static_assert(sizeof(struct cq_entry) == 32);
582 586
583 /* 587 /*
584 * UTMRD structure. 588 * UTMRD structure.
585 */ 589 */
586 struct utp_task_req_desc { 590 struct utp_task_req_desc {
587 /* DW 0-3 */ 591 /* DW 0-3 */
588 struct request_desc_header header; 592 struct request_desc_header header;
589 593
590 /* DW 4-11 - Task request UPIU structu 594 /* DW 4-11 - Task request UPIU structure */
591 struct { 595 struct {
592 struct utp_upiu_header req_he 596 struct utp_upiu_header req_header;
593 __be32 input_ 597 __be32 input_param1;
594 __be32 input_ 598 __be32 input_param2;
595 __be32 input_ 599 __be32 input_param3;
596 __be32 __rese 600 __be32 __reserved1[2];
597 } upiu_req; 601 } upiu_req;
598 602
599 /* DW 12-19 - Task Management Response 603 /* DW 12-19 - Task Management Response UPIU structure */
600 struct { 604 struct {
601 struct utp_upiu_header rsp_he 605 struct utp_upiu_header rsp_header;
602 __be32 output 606 __be32 output_param1;
603 __be32 output 607 __be32 output_param2;
604 __be32 __rese 608 __be32 __reserved2[3];
605 } upiu_rsp; 609 } upiu_rsp;
606 }; 610 };
607 611
608 #endif /* End of Header */ 612 #endif /* End of Header */
609 613
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