1 /* 1 /*
2 * Copyright 2005-2009 Freescale Semiconductor 2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 * 3 *
4 * The code contained herein is licensed under 4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of t 5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the 6 * Public License Version 2.1 or later at the following locations:
7 * 7 *
8 * http://www.opensource.org/licenses/lgpl-lic 8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html 9 * http://www.gnu.org/copyleft/lgpl.html
10 */ 10 */
11 11
12 #ifndef __DRM_IPU_H__ 12 #ifndef __DRM_IPU_H__
13 #define __DRM_IPU_H__ 13 #define __DRM_IPU_H__
14 14
15 #include <linux/types.h> 15 #include <linux/types.h>
16 #include <linux/videodev2.h> 16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h> 17 #include <linux/bitmap.h>
18 #include <linux/fb.h> 18 #include <linux/fb.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <drm/drm_color_mgmt.h> <<
21 #include <media/v4l2-mediabus.h> 20 #include <media/v4l2-mediabus.h>
22 #include <video/videomode.h> 21 #include <video/videomode.h>
23 22
24 struct ipu_soc; 23 struct ipu_soc;
25 24
26 enum ipuv3_type { 25 enum ipuv3_type {
27 IPUV3EX, 26 IPUV3EX,
28 IPUV3M, 27 IPUV3M,
29 IPUV3H, 28 IPUV3H,
30 }; 29 };
31 30
32 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G 31 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
33 32
34 /* 33 /*
35 * Bitfield of Display Interface signal polari 34 * Bitfield of Display Interface signal polarities.
36 */ 35 */
37 struct ipu_di_signal_cfg { 36 struct ipu_di_signal_cfg {
38 unsigned data_pol:1; /* true = inve 37 unsigned data_pol:1; /* true = inverted */
39 unsigned clk_pol:1; /* true = risi 38 unsigned clk_pol:1; /* true = rising edge */
40 unsigned enable_pol:1; 39 unsigned enable_pol:1;
41 40
42 struct videomode mode; 41 struct videomode mode;
43 42
44 u32 bus_format; 43 u32 bus_format;
45 u32 v_to_h_sync; 44 u32 v_to_h_sync;
46 45
47 #define IPU_DI_CLKMODE_SYNC (1 << 0) 46 #define IPU_DI_CLKMODE_SYNC (1 << 0)
48 #define IPU_DI_CLKMODE_EXT (1 << 1) 47 #define IPU_DI_CLKMODE_EXT (1 << 1)
49 unsigned long clkflags; 48 unsigned long clkflags;
50 49
51 u8 hsync_pin; 50 u8 hsync_pin;
52 u8 vsync_pin; 51 u8 vsync_pin;
53 }; 52 };
54 53
55 /* 54 /*
56 * Enumeration of CSI destinations 55 * Enumeration of CSI destinations
57 */ 56 */
58 enum ipu_csi_dest { 57 enum ipu_csi_dest {
59 IPU_CSI_DEST_IDMAC, /* to memory via S 58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
60 IPU_CSI_DEST_IC, /* to Image Co 59 IPU_CSI_DEST_IC, /* to Image Converter */
61 IPU_CSI_DEST_VDIC, /* to VDIC */ 60 IPU_CSI_DEST_VDIC, /* to VDIC */
62 }; 61 };
63 62
64 /* 63 /*
65 * Enumeration of IPU rotation modes 64 * Enumeration of IPU rotation modes
66 */ 65 */
67 #define IPU_ROT_BIT_VFLIP (1 << 0) <<
68 #define IPU_ROT_BIT_HFLIP (1 << 1) <<
69 #define IPU_ROT_BIT_90 (1 << 2) <<
70 <<
71 enum ipu_rotate_mode { 66 enum ipu_rotate_mode {
72 IPU_ROTATE_NONE = 0, 67 IPU_ROTATE_NONE = 0,
73 IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFL !! 68 IPU_ROTATE_VERT_FLIP,
74 IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HF !! 69 IPU_ROTATE_HORIZ_FLIP,
75 IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | !! 70 IPU_ROTATE_180,
76 IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90, !! 71 IPU_ROTATE_90_RIGHT,
77 IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_B !! 72 IPU_ROTATE_90_RIGHT_VFLIP,
78 IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_B !! 73 IPU_ROTATE_90_RIGHT_HFLIP,
79 IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 | !! 74 IPU_ROTATE_90_LEFT,
80 IPU_ROT_BIT_VFLI <<
81 }; 75 };
82 76
83 /* 90-degree rotations require the IRT unit */ <<
84 #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT <<
85 <<
86 enum ipu_color_space { 77 enum ipu_color_space {
87 IPUV3_COLORSPACE_RGB, 78 IPUV3_COLORSPACE_RGB,
88 IPUV3_COLORSPACE_YUV, 79 IPUV3_COLORSPACE_YUV,
89 IPUV3_COLORSPACE_UNKNOWN, 80 IPUV3_COLORSPACE_UNKNOWN,
90 }; 81 };
91 82
92 /* <<
93 * Enumeration of VDI MOTION select <<
94 */ <<
95 enum ipu_motion_sel { <<
96 MOTION_NONE = 0, <<
97 LOW_MOTION, <<
98 MED_MOTION, <<
99 HIGH_MOTION, <<
100 }; <<
101 <<
102 struct ipuv3_channel; 83 struct ipuv3_channel;
103 84
104 enum ipu_channel_irq { 85 enum ipu_channel_irq {
105 IPU_IRQ_EOF = 0, 86 IPU_IRQ_EOF = 0,
106 IPU_IRQ_NFACK = 64, 87 IPU_IRQ_NFACK = 64,
107 IPU_IRQ_NFB4EOF = 128, 88 IPU_IRQ_NFB4EOF = 128,
108 IPU_IRQ_EOS = 192, 89 IPU_IRQ_EOS = 192,
109 }; 90 };
110 91
111 /* 92 /*
112 * Enumeration of IDMAC channels 93 * Enumeration of IDMAC channels
113 */ 94 */
114 #define IPUV3_CHANNEL_CSI0 95 #define IPUV3_CHANNEL_CSI0 0
115 #define IPUV3_CHANNEL_CSI1 96 #define IPUV3_CHANNEL_CSI1 1
116 #define IPUV3_CHANNEL_CSI2 97 #define IPUV3_CHANNEL_CSI2 2
117 #define IPUV3_CHANNEL_CSI3 98 #define IPUV3_CHANNEL_CSI3 3
118 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 99 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
119 /* <<
120 * NOTE: channels 6,7 are unused in the IPU an <<
121 * but the direct CSI->VDI linking is handled <<
122 * channel linking in the FSU via the IPU_FS_P <<
123 * these channel names are used to support the <<
124 */ <<
125 #define IPUV3_CHANNEL_CSI_DIRECT <<
126 #define IPUV3_CHANNEL_CSI_VDI_PREV <<
127 #define IPUV3_CHANNEL_MEM_VDI_PREV <<
128 #define IPUV3_CHANNEL_MEM_VDI_CUR <<
129 #define IPUV3_CHANNEL_MEM_VDI_NEXT <<
130 #define IPUV3_CHANNEL_MEM_IC_PP 100 #define IPUV3_CHANNEL_MEM_IC_PP 11
131 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 101 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
132 #define IPUV3_CHANNEL_VDI_MEM_RECENT <<
133 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 102 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
134 #define IPUV3_CHANNEL_G_MEM_IC_PP 103 #define IPUV3_CHANNEL_G_MEM_IC_PP 15
135 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA <<
136 #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA <<
137 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPH <<
138 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 104 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
139 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 105 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
140 #define IPUV3_CHANNEL_IC_PP_MEM 106 #define IPUV3_CHANNEL_IC_PP_MEM 22
141 #define IPUV3_CHANNEL_MEM_BG_SYNC 107 #define IPUV3_CHANNEL_MEM_BG_SYNC 23
142 #define IPUV3_CHANNEL_MEM_BG_ASYNC 108 #define IPUV3_CHANNEL_MEM_BG_ASYNC 24
143 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB <<
144 #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB <<
145 #define IPUV3_CHANNEL_MEM_FG_SYNC 109 #define IPUV3_CHANNEL_MEM_FG_SYNC 27
146 #define IPUV3_CHANNEL_MEM_DC_SYNC 110 #define IPUV3_CHANNEL_MEM_DC_SYNC 28
147 #define IPUV3_CHANNEL_MEM_FG_ASYNC 111 #define IPUV3_CHANNEL_MEM_FG_ASYNC 29
148 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 112 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
149 #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA <<
150 #define IPUV3_CHANNEL_DC_MEM_READ <<
151 #define IPUV3_CHANNEL_MEM_DC_ASYNC 113 #define IPUV3_CHANNEL_MEM_DC_ASYNC 41
152 #define IPUV3_CHANNEL_MEM_DC_COMMAND <<
153 #define IPUV3_CHANNEL_MEM_DC_COMMAND2 <<
154 #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK <<
155 #define IPUV3_CHANNEL_MEM_ROT_ENC 114 #define IPUV3_CHANNEL_MEM_ROT_ENC 45
156 #define IPUV3_CHANNEL_MEM_ROT_VF 115 #define IPUV3_CHANNEL_MEM_ROT_VF 46
157 #define IPUV3_CHANNEL_MEM_ROT_PP 116 #define IPUV3_CHANNEL_MEM_ROT_PP 47
158 #define IPUV3_CHANNEL_ROT_ENC_MEM 117 #define IPUV3_CHANNEL_ROT_ENC_MEM 48
159 #define IPUV3_CHANNEL_ROT_VF_MEM 118 #define IPUV3_CHANNEL_ROT_VF_MEM 49
160 #define IPUV3_CHANNEL_ROT_PP_MEM 119 #define IPUV3_CHANNEL_ROT_PP_MEM 50
161 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 120 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
162 #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA <<
163 #define IPUV3_NUM_CHANNELS <<
164 <<
165 static inline int ipu_channel_alpha_channel(in <<
166 { <<
167 switch (ch_num) { <<
168 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: <<
169 return IPUV3_CHANNEL_G_MEM_IC_ <<
170 case IPUV3_CHANNEL_G_MEM_IC_PP: <<
171 return IPUV3_CHANNEL_G_MEM_IC_ <<
172 case IPUV3_CHANNEL_MEM_FG_SYNC: <<
173 return IPUV3_CHANNEL_MEM_FG_SY <<
174 case IPUV3_CHANNEL_MEM_FG_ASYNC: <<
175 return IPUV3_CHANNEL_MEM_FG_AS <<
176 case IPUV3_CHANNEL_MEM_BG_SYNC: <<
177 return IPUV3_CHANNEL_MEM_BG_SY <<
178 case IPUV3_CHANNEL_MEM_BG_ASYNC: <<
179 return IPUV3_CHANNEL_MEM_BG_AS <<
180 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB <<
181 return IPUV3_CHANNEL_MEM_VDI_P <<
182 default: <<
183 return -EINVAL; <<
184 } <<
185 } <<
186 121
187 int ipu_map_irq(struct ipu_soc *ipu, int irq); 122 int ipu_map_irq(struct ipu_soc *ipu, int irq);
188 int ipu_idmac_channel_irq(struct ipu_soc *ipu, 123 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
189 enum ipu_channel_irq irq); 124 enum ipu_channel_irq irq);
190 125
191 #define IPU_IRQ_DP_SF_START (448 + 126 #define IPU_IRQ_DP_SF_START (448 + 2)
192 #define IPU_IRQ_DP_SF_END (448 + 127 #define IPU_IRQ_DP_SF_END (448 + 3)
193 #define IPU_IRQ_BG_SF_END IPU_IR 128 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
194 #define IPU_IRQ_DC_FC_0 (448 + 129 #define IPU_IRQ_DC_FC_0 (448 + 8)
195 #define IPU_IRQ_DC_FC_1 (448 + 130 #define IPU_IRQ_DC_FC_1 (448 + 9)
196 #define IPU_IRQ_DC_FC_2 (448 + 131 #define IPU_IRQ_DC_FC_2 (448 + 10)
197 #define IPU_IRQ_DC_FC_3 (448 + 132 #define IPU_IRQ_DC_FC_3 (448 + 11)
198 #define IPU_IRQ_DC_FC_4 (448 + 133 #define IPU_IRQ_DC_FC_4 (448 + 12)
199 #define IPU_IRQ_DC_FC_6 (448 + 134 #define IPU_IRQ_DC_FC_6 (448 + 13)
200 #define IPU_IRQ_VSYNC_PRE_0 (448 + 135 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
201 #define IPU_IRQ_VSYNC_PRE_1 (448 + 136 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
202 137
203 /* 138 /*
204 * IPU Common functions 139 * IPU Common functions
205 */ 140 */
206 int ipu_get_num(struct ipu_soc *ipu); <<
207 void ipu_set_csi_src_mux(struct ipu_soc *ipu, 141 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
208 void ipu_set_ic_src_mux(struct ipu_soc *ipu, i 142 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
209 void ipu_dump(struct ipu_soc *ipu); 143 void ipu_dump(struct ipu_soc *ipu);
210 144
211 /* 145 /*
212 * IPU Image DMA Controller (idmac) functions 146 * IPU Image DMA Controller (idmac) functions
213 */ 147 */
214 struct ipuv3_channel *ipu_idmac_get(struct ipu 148 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
215 void ipu_idmac_put(struct ipuv3_channel *); 149 void ipu_idmac_put(struct ipuv3_channel *);
216 150
217 int ipu_idmac_enable_channel(struct ipuv3_chan 151 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
218 int ipu_idmac_disable_channel(struct ipuv3_cha 152 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
219 void ipu_idmac_enable_watermark(struct ipuv3_c 153 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
220 int ipu_idmac_lock_enable(struct ipuv3_channel 154 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
221 int ipu_idmac_wait_busy(struct ipuv3_channel * 155 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
222 156
223 void ipu_idmac_set_double_buffer(struct ipuv3_ 157 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
224 bool doublebuffer); 158 bool doublebuffer);
225 int ipu_idmac_get_current_buffer(struct ipuv3_ 159 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
226 bool ipu_idmac_buffer_is_ready(struct ipuv3_ch 160 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
227 void ipu_idmac_select_buffer(struct ipuv3_chan 161 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
228 void ipu_idmac_clear_buffer(struct ipuv3_chann 162 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
229 int ipu_fsu_link(struct ipu_soc *ipu, int src_ <<
230 int ipu_fsu_unlink(struct ipu_soc *ipu, int sr <<
231 int ipu_idmac_link(struct ipuv3_channel *src, <<
232 int ipu_idmac_unlink(struct ipuv3_channel *src <<
233 163
234 /* 164 /*
235 * IPU Channel Parameter Memory (cpmem) functi 165 * IPU Channel Parameter Memory (cpmem) functions
236 */ 166 */
237 struct ipu_rgb { 167 struct ipu_rgb {
238 struct fb_bitfield red; 168 struct fb_bitfield red;
239 struct fb_bitfield green; 169 struct fb_bitfield green;
240 struct fb_bitfield blue; 170 struct fb_bitfield blue;
241 struct fb_bitfield transp; 171 struct fb_bitfield transp;
242 int bits_per_pixel 172 int bits_per_pixel;
243 }; 173 };
244 174
245 struct ipu_image { 175 struct ipu_image {
246 struct v4l2_pix_format pix; 176 struct v4l2_pix_format pix;
247 struct v4l2_rect rect; 177 struct v4l2_rect rect;
248 dma_addr_t phys0; 178 dma_addr_t phys0;
249 dma_addr_t phys1; 179 dma_addr_t phys1;
250 /* chroma plane offset overrides */ <<
251 u32 u_offset; <<
252 u32 v_offset; <<
253 }; 180 };
254 181
255 void ipu_cpmem_zero(struct ipuv3_channel *ch); 182 void ipu_cpmem_zero(struct ipuv3_channel *ch);
256 void ipu_cpmem_set_resolution(struct ipuv3_cha 183 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
257 void ipu_cpmem_skip_odd_chroma_rows(struct ipu <<
258 void ipu_cpmem_set_stride(struct ipuv3_channel 184 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
259 void ipu_cpmem_set_high_priority(struct ipuv3_ 185 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
260 void ipu_cpmem_set_buffer(struct ipuv3_channel 186 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
261 void ipu_cpmem_set_uv_offset(struct ipuv3_chan !! 187 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
262 void ipu_cpmem_interlaced_scan(struct ipuv3_ch <<
263 u32 pixelformat <<
264 void ipu_cpmem_set_axi_id(struct ipuv3_channel 188 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
265 int ipu_cpmem_get_burstsize(struct ipuv3_chann <<
266 void ipu_cpmem_set_burstsize(struct ipuv3_chan 189 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
267 void ipu_cpmem_set_block_mode(struct ipuv3_cha 190 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
268 void ipu_cpmem_set_rotation(struct ipuv3_chann 191 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
269 enum ipu_rotate_mo 192 enum ipu_rotate_mode rot);
270 int ipu_cpmem_set_format_rgb(struct ipuv3_chan 193 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
271 const struct ipu_ 194 const struct ipu_rgb *rgb);
272 int ipu_cpmem_set_format_passthrough(struct ip 195 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
273 void ipu_cpmem_set_yuv_interleaved(struct ipuv 196 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
274 void ipu_cpmem_set_yuv_planar_full(struct ipuv 197 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
275 unsigned in !! 198 u32 pixel_format, int stride,
276 unsigned in !! 199 int u_offset, int v_offset);
277 unsigned in !! 200 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
>> 201 u32 pixel_format, int stride, int height);
278 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch 202 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
279 int ipu_cpmem_set_image(struct ipuv3_channel * 203 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
280 void ipu_cpmem_dump(struct ipuv3_channel *ch); 204 void ipu_cpmem_dump(struct ipuv3_channel *ch);
281 205
282 /* 206 /*
283 * IPU Display Controller (dc) functions 207 * IPU Display Controller (dc) functions
284 */ 208 */
285 struct ipu_dc; 209 struct ipu_dc;
286 struct ipu_di; 210 struct ipu_di;
287 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, 211 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
288 void ipu_dc_put(struct ipu_dc *dc); 212 void ipu_dc_put(struct ipu_dc *dc);
289 int ipu_dc_init_sync(struct ipu_dc *dc, struct 213 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
290 u32 pixel_fmt, u32 width); 214 u32 pixel_fmt, u32 width);
291 void ipu_dc_enable(struct ipu_soc *ipu); 215 void ipu_dc_enable(struct ipu_soc *ipu);
292 void ipu_dc_enable_channel(struct ipu_dc *dc); 216 void ipu_dc_enable_channel(struct ipu_dc *dc);
293 void ipu_dc_disable_channel(struct ipu_dc *dc) 217 void ipu_dc_disable_channel(struct ipu_dc *dc);
294 void ipu_dc_disable(struct ipu_soc *ipu); 218 void ipu_dc_disable(struct ipu_soc *ipu);
295 219
296 /* 220 /*
297 * IPU Display Interface (di) functions 221 * IPU Display Interface (di) functions
298 */ 222 */
299 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, 223 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
300 void ipu_di_put(struct ipu_di *); 224 void ipu_di_put(struct ipu_di *);
301 int ipu_di_disable(struct ipu_di *); 225 int ipu_di_disable(struct ipu_di *);
302 int ipu_di_enable(struct ipu_di *); 226 int ipu_di_enable(struct ipu_di *);
303 int ipu_di_get_num(struct ipu_di *); 227 int ipu_di_get_num(struct ipu_di *);
304 int ipu_di_adjust_videomode(struct ipu_di *di, 228 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
305 int ipu_di_init_sync_panel(struct ipu_di *, st 229 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
306 230
307 /* 231 /*
308 * IPU Display Multi FIFO Controller (dmfc) fu 232 * IPU Display Multi FIFO Controller (dmfc) functions
309 */ 233 */
310 struct dmfc_channel; 234 struct dmfc_channel;
311 int ipu_dmfc_enable_channel(struct dmfc_channe 235 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
312 void ipu_dmfc_disable_channel(struct dmfc_chan 236 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
313 void ipu_dmfc_config_wait4eot(struct dmfc_chan !! 237 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
>> 238 unsigned long bandwidth_mbs, int burstsize);
>> 239 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
>> 240 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
314 struct dmfc_channel *ipu_dmfc_get(struct ipu_s 241 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
315 void ipu_dmfc_put(struct dmfc_channel *dmfc); 242 void ipu_dmfc_put(struct dmfc_channel *dmfc);
316 243
317 /* 244 /*
318 * IPU Display Processor (dp) functions 245 * IPU Display Processor (dp) functions
319 */ 246 */
320 #define IPU_DP_FLOW_SYNC_BG 0 247 #define IPU_DP_FLOW_SYNC_BG 0
321 #define IPU_DP_FLOW_SYNC_FG 1 248 #define IPU_DP_FLOW_SYNC_FG 1
322 #define IPU_DP_FLOW_ASYNC0_BG 2 249 #define IPU_DP_FLOW_ASYNC0_BG 2
323 #define IPU_DP_FLOW_ASYNC0_FG 3 250 #define IPU_DP_FLOW_ASYNC0_FG 3
324 #define IPU_DP_FLOW_ASYNC1_BG 4 251 #define IPU_DP_FLOW_ASYNC1_BG 4
325 #define IPU_DP_FLOW_ASYNC1_FG 5 252 #define IPU_DP_FLOW_ASYNC1_FG 5
326 253
327 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, 254 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
328 void ipu_dp_put(struct ipu_dp *); 255 void ipu_dp_put(struct ipu_dp *);
329 int ipu_dp_enable(struct ipu_soc *ipu); 256 int ipu_dp_enable(struct ipu_soc *ipu);
330 int ipu_dp_enable_channel(struct ipu_dp *dp); 257 int ipu_dp_enable_channel(struct ipu_dp *dp);
331 void ipu_dp_disable_channel(struct ipu_dp *dp, !! 258 void ipu_dp_disable_channel(struct ipu_dp *dp);
332 void ipu_dp_disable(struct ipu_soc *ipu); 259 void ipu_dp_disable(struct ipu_soc *ipu);
333 int ipu_dp_setup_channel(struct ipu_dp *dp, 260 int ipu_dp_setup_channel(struct ipu_dp *dp,
334 enum drm_color_encoding ycbcr_ <<
335 enum ipu_color_space in, enum 261 enum ipu_color_space in, enum ipu_color_space out);
336 int ipu_dp_set_window_pos(struct ipu_dp *, u16 262 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
337 int ipu_dp_set_global_alpha(struct ipu_dp *dp, 263 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
338 bool bg_chan); 264 bool bg_chan);
339 265
340 /* 266 /*
341 * IPU Prefetch Resolve Gasket (prg) functions <<
342 */ <<
343 int ipu_prg_max_active_channels(void); <<
344 bool ipu_prg_present(struct ipu_soc *ipu); <<
345 bool ipu_prg_format_supported(struct ipu_soc * <<
346 uint64_t modifie <<
347 int ipu_prg_enable(struct ipu_soc *ipu); <<
348 void ipu_prg_disable(struct ipu_soc *ipu); <<
349 void ipu_prg_channel_disable(struct ipuv3_chan <<
350 int ipu_prg_channel_configure(struct ipuv3_cha <<
351 unsigned int axi <<
352 unsigned int hei <<
353 u32 format, uint <<
354 bool ipu_prg_channel_configure_pending(struct <<
355 <<
356 /* <<
357 * IPU CMOS Sensor Interface (csi) functions 267 * IPU CMOS Sensor Interface (csi) functions
358 */ 268 */
359 struct ipu_csi; 269 struct ipu_csi;
360 int ipu_csi_init_interface(struct ipu_csi *csi 270 int ipu_csi_init_interface(struct ipu_csi *csi,
361 const struct v4l2_m !! 271 struct v4l2_mbus_config *mbus_cfg,
362 const struct v4l2_m !! 272 struct v4l2_mbus_framefmt *mbus_fmt);
363 const struct v4l2_m <<
364 bool ipu_csi_is_interlaced(struct ipu_csi *csi 273 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
365 void ipu_csi_get_window(struct ipu_csi *csi, s 274 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
366 void ipu_csi_set_window(struct ipu_csi *csi, s 275 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
367 void ipu_csi_set_downsize(struct ipu_csi *csi, <<
368 void ipu_csi_set_test_generator(struct ipu_csi 276 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
369 u32 r_value, u 277 u32 r_value, u32 g_value, u32 b_value,
370 u32 pix_clk); 278 u32 pix_clk);
371 int ipu_csi_set_mipi_datatype(struct ipu_csi * 279 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
372 struct v4l2_mbus 280 struct v4l2_mbus_framefmt *mbus_fmt);
373 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, 281 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
374 u32 max_ratio, u32 i 282 u32 max_ratio, u32 id);
375 int ipu_csi_set_dest(struct ipu_csi *csi, enum 283 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
376 int ipu_csi_enable(struct ipu_csi *csi); 284 int ipu_csi_enable(struct ipu_csi *csi);
377 int ipu_csi_disable(struct ipu_csi *csi); 285 int ipu_csi_disable(struct ipu_csi *csi);
378 struct ipu_csi *ipu_csi_get(struct ipu_soc *ip 286 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
379 void ipu_csi_put(struct ipu_csi *csi); 287 void ipu_csi_put(struct ipu_csi *csi);
380 void ipu_csi_dump(struct ipu_csi *csi); 288 void ipu_csi_dump(struct ipu_csi *csi);
381 289
382 /* 290 /*
383 * IPU Image Converter (ic) functions 291 * IPU Image Converter (ic) functions
384 */ 292 */
385 enum ipu_ic_task { 293 enum ipu_ic_task {
386 IC_TASK_ENCODER, 294 IC_TASK_ENCODER,
387 IC_TASK_VIEWFINDER, 295 IC_TASK_VIEWFINDER,
388 IC_TASK_POST_PROCESSOR, 296 IC_TASK_POST_PROCESSOR,
389 IC_NUM_TASKS, 297 IC_NUM_TASKS,
390 }; 298 };
391 299
392 /* <<
393 * The parameters that describe a colorspace a <<
394 * Image Converter: <<
395 * - Y'CbCr encoding <<
396 * - quantization <<
397 * - "colorspace" (RGB or YUV). <<
398 */ <<
399 struct ipu_ic_colorspace { <<
400 enum v4l2_ycbcr_encoding enc; <<
401 enum v4l2_quantization quant; <<
402 enum ipu_color_space cs; <<
403 }; <<
404 <<
405 static inline void <<
406 ipu_ic_fill_colorspace(struct ipu_ic_colorspac <<
407 enum v4l2_ycbcr_encodin <<
408 enum v4l2_quantization <<
409 enum ipu_color_space cs <<
410 { <<
411 ic_cs->enc = enc; <<
412 ic_cs->quant = quant; <<
413 ic_cs->cs = cs; <<
414 } <<
415 <<
416 struct ipu_ic_csc_params { <<
417 s16 coeff[3][3]; /* signed 9-bi <<
418 s16 offset[3]; /* signed 11+2 <<
419 u8 scale:2; /* scale coeff <<
420 bool sat:1; /* saturate to <<
421 }; <<
422 <<
423 struct ipu_ic_csc { <<
424 struct ipu_ic_colorspace in_cs; <<
425 struct ipu_ic_colorspace out_cs; <<
426 struct ipu_ic_csc_params params; <<
427 }; <<
428 <<
429 struct ipu_ic; 300 struct ipu_ic;
430 <<
431 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc); <<
432 int ipu_ic_calc_csc(struct ipu_ic_csc *csc, <<
433 enum v4l2_ycbcr_encoding i <<
434 enum v4l2_quantization in_ <<
435 enum ipu_color_space in_cs <<
436 enum v4l2_ycbcr_encoding o <<
437 enum v4l2_quantization out <<
438 enum ipu_color_space out_c <<
439 int ipu_ic_task_init(struct ipu_ic *ic, 301 int ipu_ic_task_init(struct ipu_ic *ic,
440 const struct ipu_ic_csc * <<
441 int in_width, int in_heig 302 int in_width, int in_height,
442 int out_width, int out_he !! 303 int out_width, int out_height,
443 int ipu_ic_task_init_rsc(struct ipu_ic *ic, !! 304 enum ipu_color_space in_cs,
444 const struct ipu_ic_c !! 305 enum ipu_color_space out_cs);
445 int in_width, int in_ <<
446 int out_width, int ou <<
447 u32 rsc); <<
448 int ipu_ic_task_graphics_init(struct ipu_ic *i 306 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
449 const struct ipu !! 307 enum ipu_color_space in_g_cs,
450 bool galpha_en, 308 bool galpha_en, u32 galpha,
451 bool colorkey_en 309 bool colorkey_en, u32 colorkey);
452 void ipu_ic_task_enable(struct ipu_ic *ic); 310 void ipu_ic_task_enable(struct ipu_ic *ic);
453 void ipu_ic_task_disable(struct ipu_ic *ic); 311 void ipu_ic_task_disable(struct ipu_ic *ic);
454 int ipu_ic_task_idma_init(struct ipu_ic *ic, s 312 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
455 u32 width, u32 heigh 313 u32 width, u32 height, int burst_size,
456 enum ipu_rotate_mode 314 enum ipu_rotate_mode rot);
457 int ipu_ic_enable(struct ipu_ic *ic); 315 int ipu_ic_enable(struct ipu_ic *ic);
458 int ipu_ic_disable(struct ipu_ic *ic); 316 int ipu_ic_disable(struct ipu_ic *ic);
459 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, 317 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
460 void ipu_ic_put(struct ipu_ic *ic); 318 void ipu_ic_put(struct ipu_ic *ic);
461 void ipu_ic_dump(struct ipu_ic *ic); 319 void ipu_ic_dump(struct ipu_ic *ic);
462 320
463 /* 321 /*
464 * IPU Video De-Interlacer (vdi) functions <<
465 */ <<
466 struct ipu_vdi; <<
467 void ipu_vdi_set_field_order(struct ipu_vdi *v <<
468 void ipu_vdi_set_motion(struct ipu_vdi *vdi, e <<
469 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 co <<
470 void ipu_vdi_unsetup(struct ipu_vdi *vdi); <<
471 int ipu_vdi_enable(struct ipu_vdi *vdi); <<
472 int ipu_vdi_disable(struct ipu_vdi *vdi); <<
473 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ip <<
474 void ipu_vdi_put(struct ipu_vdi *vdi); <<
475 <<
476 /* <<
477 * IPU Sensor Multiple FIFO Controller (SMFC) 322 * IPU Sensor Multiple FIFO Controller (SMFC) functions
478 */ 323 */
479 struct ipu_smfc *ipu_smfc_get(struct ipu_soc * 324 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
480 void ipu_smfc_put(struct ipu_smfc *smfc); 325 void ipu_smfc_put(struct ipu_smfc *smfc);
481 int ipu_smfc_enable(struct ipu_smfc *smfc); 326 int ipu_smfc_enable(struct ipu_smfc *smfc);
482 int ipu_smfc_disable(struct ipu_smfc *smfc); 327 int ipu_smfc_disable(struct ipu_smfc *smfc);
483 int ipu_smfc_map_channel(struct ipu_smfc *smfc 328 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
484 int ipu_smfc_set_burstsize(struct ipu_smfc *sm 329 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
485 int ipu_smfc_set_watermark(struct ipu_smfc *sm 330 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
486 331
487 enum ipu_color_space ipu_drm_fourcc_to_colorsp 332 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
488 enum ipu_color_space ipu_pixelformat_to_colors 333 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
>> 334 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
>> 335 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
>> 336 bool ipu_pixelformat_is_planar(u32 pixelformat);
489 int ipu_degrees_to_rot_mode(enum ipu_rotate_mo 337 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
490 bool hflip, bool v 338 bool hflip, bool vflip);
491 int ipu_rot_mode_to_degrees(int *degrees, enum 339 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
492 bool hflip, bool v 340 bool hflip, bool vflip);
493 341
494 struct ipu_client_platformdata { 342 struct ipu_client_platformdata {
495 int csi; 343 int csi;
496 int di; 344 int di;
497 int dc; 345 int dc;
498 int dp; 346 int dp;
499 int dma[2]; 347 int dma[2];
500 struct device_node *of_node; 348 struct device_node *of_node;
501 }; 349 };
502 350
503 #endif /* __DRM_IPU_H__ */ 351 #endif /* __DRM_IPU_H__ */
504 352
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