1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2009 Marvell International L 2 * Copyright (C) 2009 Marvell International Ltd.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 8
6 #ifndef __ASM_MACH_PXA168FB_H 9 #ifndef __ASM_MACH_PXA168FB_H
7 #define __ASM_MACH_PXA168FB_H 10 #define __ASM_MACH_PXA168FB_H
8 11
9 #include <linux/fb.h> 12 #include <linux/fb.h>
10 #include <linux/interrupt.h> 13 #include <linux/interrupt.h>
11 14
12 /* Dumb interface */ 15 /* Dumb interface */
13 #define PIN_MODE_DUMB_24 0 16 #define PIN_MODE_DUMB_24 0
14 #define PIN_MODE_DUMB_18_SPI 1 17 #define PIN_MODE_DUMB_18_SPI 1
15 #define PIN_MODE_DUMB_18_GPIO 2 18 #define PIN_MODE_DUMB_18_GPIO 2
16 #define PIN_MODE_DUMB_16_SPI 3 19 #define PIN_MODE_DUMB_16_SPI 3
17 #define PIN_MODE_DUMB_16_GPIO 4 20 #define PIN_MODE_DUMB_16_GPIO 4
18 #define PIN_MODE_DUMB_12_SPI_GPIO 5 21 #define PIN_MODE_DUMB_12_SPI_GPIO 5
19 #define PIN_MODE_SMART_18_SPI 6 22 #define PIN_MODE_SMART_18_SPI 6
20 #define PIN_MODE_SMART_16_SPI 7 23 #define PIN_MODE_SMART_16_SPI 7
21 #define PIN_MODE_SMART_8_SPI_GPIO 8 24 #define PIN_MODE_SMART_8_SPI_GPIO 8
22 25
23 /* Dumb interface pin allocation */ 26 /* Dumb interface pin allocation */
24 #define DUMB_MODE_RGB565 0 27 #define DUMB_MODE_RGB565 0
25 #define DUMB_MODE_RGB565_UPPER 1 28 #define DUMB_MODE_RGB565_UPPER 1
26 #define DUMB_MODE_RGB666 2 29 #define DUMB_MODE_RGB666 2
27 #define DUMB_MODE_RGB666_UPPER 3 30 #define DUMB_MODE_RGB666_UPPER 3
28 #define DUMB_MODE_RGB444 4 31 #define DUMB_MODE_RGB444 4
29 #define DUMB_MODE_RGB444_UPPER 5 32 #define DUMB_MODE_RGB444_UPPER 5
30 #define DUMB_MODE_RGB888 6 33 #define DUMB_MODE_RGB888 6
31 34
32 /* default fb buffer size WVGA-32bits */ 35 /* default fb buffer size WVGA-32bits */
33 #define DEFAULT_FB_SIZE (800 * 480 * 4) 36 #define DEFAULT_FB_SIZE (800 * 480 * 4)
34 37
35 /* 38 /*
36 * Buffer pixel format 39 * Buffer pixel format
37 * bit0 is for rb swap. 40 * bit0 is for rb swap.
38 * bit12 is for Y UorV swap 41 * bit12 is for Y UorV swap
39 */ 42 */
40 #define PIX_FMT_RGB565 0 43 #define PIX_FMT_RGB565 0
41 #define PIX_FMT_BGR565 1 44 #define PIX_FMT_BGR565 1
42 #define PIX_FMT_RGB1555 2 45 #define PIX_FMT_RGB1555 2
43 #define PIX_FMT_BGR1555 3 46 #define PIX_FMT_BGR1555 3
44 #define PIX_FMT_RGB888PACK 4 47 #define PIX_FMT_RGB888PACK 4
45 #define PIX_FMT_BGR888PACK 5 48 #define PIX_FMT_BGR888PACK 5
46 #define PIX_FMT_RGB888UNPACK 6 49 #define PIX_FMT_RGB888UNPACK 6
47 #define PIX_FMT_BGR888UNPACK 7 50 #define PIX_FMT_BGR888UNPACK 7
48 #define PIX_FMT_RGBA888 8 51 #define PIX_FMT_RGBA888 8
49 #define PIX_FMT_BGRA888 9 52 #define PIX_FMT_BGRA888 9
50 #define PIX_FMT_YUV422PACK 10 53 #define PIX_FMT_YUV422PACK 10
51 #define PIX_FMT_YVU422PACK 11 54 #define PIX_FMT_YVU422PACK 11
52 #define PIX_FMT_YUV422PLANAR 12 55 #define PIX_FMT_YUV422PLANAR 12
53 #define PIX_FMT_YVU422PLANAR 13 56 #define PIX_FMT_YVU422PLANAR 13
54 #define PIX_FMT_YUV420PLANAR 14 57 #define PIX_FMT_YUV420PLANAR 14
55 #define PIX_FMT_YVU420PLANAR 15 58 #define PIX_FMT_YVU420PLANAR 15
56 #define PIX_FMT_PSEUDOCOLOR 20 59 #define PIX_FMT_PSEUDOCOLOR 20
57 #define PIX_FMT_UYVY422PACK (0x1000|PIX_FM 60 #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK)
58 61
59 /* 62 /*
60 * PXA LCD controller private state. 63 * PXA LCD controller private state.
61 */ 64 */
62 struct pxa168fb_info { 65 struct pxa168fb_info {
63 struct device *dev; 66 struct device *dev;
64 struct clk *clk; 67 struct clk *clk;
65 struct fb_info *info; 68 struct fb_info *info;
66 69
67 void __iomem *reg_base; 70 void __iomem *reg_base;
68 dma_addr_t fb_start_dma; 71 dma_addr_t fb_start_dma;
69 u32 pseudo_palette 72 u32 pseudo_palette[16];
70 73
71 int pix_fmt; 74 int pix_fmt;
72 unsigned is_blanked:1; 75 unsigned is_blanked:1;
73 unsigned panel_rbswap:1 76 unsigned panel_rbswap:1;
74 unsigned active:1; 77 unsigned active:1;
75 }; 78 };
76 79
77 /* 80 /*
78 * PXA fb machine information 81 * PXA fb machine information
79 */ 82 */
80 struct pxa168fb_mach_info { 83 struct pxa168fb_mach_info {
81 char id[16]; 84 char id[16];
82 85
83 int num_modes; 86 int num_modes;
84 struct fb_videomode *modes; 87 struct fb_videomode *modes;
85 88
86 /* 89 /*
87 * Pix_fmt 90 * Pix_fmt
88 */ 91 */
89 unsigned pix_fmt; 92 unsigned pix_fmt;
90 93
91 /* 94 /*
92 * I/O pin allocation. 95 * I/O pin allocation.
93 */ 96 */
94 unsigned io_pin_allocation_mode 97 unsigned io_pin_allocation_mode:4;
95 98
96 /* 99 /*
97 * Dumb panel -- assignment of R/G/B c 100 * Dumb panel -- assignment of R/G/B component info to the 24
98 * available external data lanes. 101 * available external data lanes.
99 */ 102 */
100 unsigned dumb_mode:4; 103 unsigned dumb_mode:4;
101 unsigned panel_rgb_reverse_lane 104 unsigned panel_rgb_reverse_lanes:1;
102 105
103 /* 106 /*
104 * Dumb panel -- GPIO output data. 107 * Dumb panel -- GPIO output data.
105 */ 108 */
106 unsigned gpio_output_mask:8; 109 unsigned gpio_output_mask:8;
107 unsigned gpio_output_data:8; 110 unsigned gpio_output_data:8;
108 111
109 /* 112 /*
110 * Dumb panel -- configurable output s 113 * Dumb panel -- configurable output signal polarity.
111 */ 114 */
112 unsigned invert_composite_blank 115 unsigned invert_composite_blank:1;
113 unsigned invert_pix_val_ena:1; 116 unsigned invert_pix_val_ena:1;
114 unsigned invert_pixclock:1; 117 unsigned invert_pixclock:1;
115 unsigned panel_rbswap:1; 118 unsigned panel_rbswap:1;
116 unsigned active:1; 119 unsigned active:1;
117 unsigned enable_lcd:1; 120 unsigned enable_lcd:1;
118 }; 121 };
119 122
120 #endif /* __ASM_MACH_PXA168FB_H */ 123 #endif /* __ASM_MACH_PXA168FB_H */
121 124
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