1 /* include/video/s1d13xxxfb.h 1
2 *
3 * (c) 2004 Simtec Electronics
4 * (c) 2005 Thibaut VARENE <varenet@parisc-lin
5 *
6 * Header file for Epson S1D13XXX driver code
7 *
8 * This file is subject to the terms and condi
9 * License. See the file COPYING in the main d
10 * more details.
11 */
12
13 #ifndef S1D13XXXFB_H
14 #define S1D13XXXFB_H
15
16 #define S1D_PALETTE_SIZE 256
17 #define S1D_FBID "S1D13
18 #define S1D_DEVICENAME "s1d13
19
20 /* S1DREG_REV_CODE register = prod_id (6 bits)
21 #define S1D13505_PROD_ID 0x3
22 #define S1D13506_PROD_ID 0x4
23 #define S1D13806_PROD_ID 0x7
24
25 /* register definitions (tested on s1d13896) *
26 #define S1DREG_REV_CODE 0x0000
27 #define S1DREG_MISC 0x0001
28 #define S1DREG_GPIO_CNF0 0x0004
29 #define S1DREG_GPIO_CNF1 0x0005
30 #define S1DREG_GPIO_CTL0 0x0008
31 #define S1DREG_GPIO_CTL1 0x0009
32 #define S1DREG_CNF_STATUS 0x000C
33 #define S1DREG_CLK_CNF 0x0010
34 #define S1DREG_LCD_CLK_CNF 0x0014
35 #define S1DREG_CRT_CLK_CNF 0x0018
36 #define S1DREG_MPLUG_CLK_CNF 0x001C
37 #define S1DREG_CPU2MEM_WST_SEL 0x001E
38 #define S1DREG_MEM_CNF 0x0020
39 #define S1DREG_SDRAM_REF_RATE 0x0021
40 #define S1DREG_SDRAM_TC0 0x002A
41 #define S1DREG_SDRAM_TC1 0x002B
42 #define S1DREG_PANEL_TYPE 0x0030
43 #define S1DREG_MOD_RATE 0x0031
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032
45 #define S1DREG_LCD_NDISP_HPER 0x0034
46 #define S1DREG_TFT_FPLINE_START 0x0035
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039
50 #define S1DREG_LCD_NDISP_VPER 0x003A
51 #define S1DREG_TFT_FPFRAME_START 0x003B
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C
53 #define S1DREG_LCD_DISP_MODE 0x0040
54 #define S1DREG_LCD_MISC 0x0041
55 #define S1DREG_LCD_DISP_START0 0x0042
56 #define S1DREG_LCD_DISP_START1 0x0043
57 #define S1DREG_LCD_DISP_START2 0x0044
58 #define S1DREG_LCD_MEM_OFF0 0x0046
59 #define S1DREG_LCD_MEM_OFF1 0x0047
60 #define S1DREG_LCD_PIX_PAN 0x0048
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050
64 #define S1DREG_CRT_NDISP_HPER 0x0052
65 #define S1DREG_CRT_HRTC_START 0x0053
66 #define S1DREG_CRT_HRTC_PWIDTH 0x0054
67 #define S1DREG_CRT_DISP_VHEIGHT0 0x0056
68 #define S1DREG_CRT_DISP_VHEIGHT1 0x0057
69 #define S1DREG_CRT_NDISP_VPER 0x0058
70 #define S1DREG_CRT_VRTC_START 0x0059
71 #define S1DREG_CRT_VRTC_PWIDTH 0x005A
72 #define S1DREG_TV_OUT_CTL 0x005B
73 #define S1DREG_CRT_DISP_MODE 0x0060
74 #define S1DREG_CRT_DISP_START0 0x0062
75 #define S1DREG_CRT_DISP_START1 0x0063
76 #define S1DREG_CRT_DISP_START2 0x0064
77 #define S1DREG_CRT_MEM_OFF0 0x0066
78 #define S1DREG_CRT_MEM_OFF1 0x0067
79 #define S1DREG_CRT_PIX_PAN 0x0068
80 #define S1DREG_CRT_DISP_FIFO_HTC 0x006A
81 #define S1DREG_CRT_DISP_FIFO_LTC 0x006B
82 #define S1DREG_LCD_CUR_CTL 0x0070
83 #define S1DREG_LCD_CUR_START 0x0071
84 #define S1DREG_LCD_CUR_XPOS0 0x0072
85 #define S1DREG_LCD_CUR_XPOS1 0x0073
86 #define S1DREG_LCD_CUR_YPOS0 0x0074
87 #define S1DREG_LCD_CUR_YPOS1 0x0075
88 #define S1DREG_LCD_CUR_BCTL0 0x0076
89 #define S1DREG_LCD_CUR_GCTL0 0x0077
90 #define S1DREG_LCD_CUR_RCTL0 0x0078
91 #define S1DREG_LCD_CUR_BCTL1 0x007A
92 #define S1DREG_LCD_CUR_GCTL1 0x007B
93 #define S1DREG_LCD_CUR_RCTL1 0x007C
94 #define S1DREG_LCD_CUR_FIFO_HTC 0x007E
95 #define S1DREG_CRT_CUR_CTL 0x0080
96 #define S1DREG_CRT_CUR_START 0x0081
97 #define S1DREG_CRT_CUR_XPOS0 0x0082
98 #define S1DREG_CRT_CUR_XPOS1 0x0083
99 #define S1DREG_CRT_CUR_YPOS0 0x0084
100 #define S1DREG_CRT_CUR_YPOS1 0x0085
101 #define S1DREG_CRT_CUR_BCTL0 0x0086
102 #define S1DREG_CRT_CUR_GCTL0 0x0087
103 #define S1DREG_CRT_CUR_RCTL0 0x0088
104 #define S1DREG_CRT_CUR_BCTL1 0x008A
105 #define S1DREG_CRT_CUR_GCTL1 0x008B
106 #define S1DREG_CRT_CUR_RCTL1 0x008C
107 #define S1DREG_CRT_CUR_FIFO_HTC 0x008E
108 #define S1DREG_BBLT_CTL0 0x0100
109 #define S1DREG_BBLT_CTL1 0x0101
110 #define S1DREG_BBLT_CC_EXP 0x0102
111 #define S1DREG_BBLT_OP 0x0103
112 #define S1DREG_BBLT_SRC_START0 0x0104
113 #define S1DREG_BBLT_SRC_START1 0x0105
114 #define S1DREG_BBLT_SRC_START2 0x0106
115 #define S1DREG_BBLT_DST_START0 0x0108
116 #define S1DREG_BBLT_DST_START1 0x0109
117 #define S1DREG_BBLT_DST_START2 0x010A
118 #define S1DREG_BBLT_MEM_OFF0 0x010C
119 #define S1DREG_BBLT_MEM_OFF1 0x010D
120 #define S1DREG_BBLT_WIDTH0 0x0110
121 #define S1DREG_BBLT_WIDTH1 0x0111
122 #define S1DREG_BBLT_HEIGHT0 0x0112
123 #define S1DREG_BBLT_HEIGHT1 0x0113
124 #define S1DREG_BBLT_BGC0 0x0114
125 #define S1DREG_BBLT_BGC1 0x0115
126 #define S1DREG_BBLT_FGC0 0x0118
127 #define S1DREG_BBLT_FGC1 0x0119
128 #define S1DREG_LKUP_MODE 0x01E0
129 #define S1DREG_LKUP_ADDR 0x01E2
130 #define S1DREG_LKUP_DATA 0x01E4
131 #define S1DREG_PS_CNF 0x01F0
132 #define S1DREG_PS_STATUS 0x01F1
133 #define S1DREG_CPU2MEM_WDOGT 0x01F4
134 #define S1DREG_COM_DISP_MODE 0x01FC
135
136 #define S1DREG_DELAYOFF 0xFFFE
137 #define S1DREG_DELAYON 0xFFFF
138
139 #define BBLT_SOLID_FILL 0x0c
140
141
142 /* Note: all above defines should go in separa
143 when implementing other S1D13xxx chip suppo
144
145 struct s1d13xxxfb_regval {
146 u16 addr;
147 u8 value;
148 };
149
150 struct s1d13xxxfb_par {
151 void __iomem *regs;
152 unsigned char display;
153 unsigned char prod_id;
154 unsigned char revision;
155
156 unsigned int pseudo_palette[16];
157 #ifdef CONFIG_PM
158 void *regs_save; /* pm
159 void *disp_save; /* pm
160 #endif
161 };
162
163 struct s1d13xxxfb_pdata {
164 const struct s1d13xxxfb_regval *initr
165 const unsigned int initre
166 void (*plat
167 #ifdef CONFIG_PM
168 int (*plat
169 int (*plat
170 #endif
171 };
172
173 #endif
174
175
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