1 /* include/video/s1d13xxxfb.h 1 /* include/video/s1d13xxxfb.h
2 * 2 *
3 * (c) 2004 Simtec Electronics 3 * (c) 2004 Simtec Electronics
4 * (c) 2005 Thibaut VARENE <varenet@parisc-lin 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * 5 *
6 * Header file for Epson S1D13XXX driver code 6 * Header file for Epson S1D13XXX driver code
7 * 7 *
8 * This file is subject to the terms and condi 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main d 9 * License. See the file COPYING in the main directory of this archive for
10 * more details. 10 * more details.
11 */ 11 */
12 12
13 #ifndef S1D13XXXFB_H 13 #ifndef S1D13XXXFB_H
14 #define S1D13XXXFB_H 14 #define S1D13XXXFB_H
15 15
16 #define S1D_PALETTE_SIZE 256 16 #define S1D_PALETTE_SIZE 256
17 #define S1D_FBID "S1D13 17 #define S1D_FBID "S1D13xxx"
18 #define S1D_DEVICENAME "s1d13 18 #define S1D_DEVICENAME "s1d13xxxfb"
19 19
20 /* S1DREG_REV_CODE register = prod_id (6 bits) 20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
21 #define S1D13505_PROD_ID 0x3 21 #define S1D13505_PROD_ID 0x3 /* 000011 */
22 #define S1D13506_PROD_ID 0x4 22 #define S1D13506_PROD_ID 0x4 /* 000100 */
23 #define S1D13806_PROD_ID 0x7 23 #define S1D13806_PROD_ID 0x7 /* 000111 */
24 24
25 /* register definitions (tested on s1d13896) * 25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C 32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
34 #define S1DREG_LCD_CLK_CNF 0x0014 34 #define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
35 #define S1DREG_CRT_CLK_CNF 0x0018 35 #define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
36 #define S1DREG_MPLUG_CLK_CNF 0x001C 36 #define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
37 #define S1DREG_CPU2MEM_WST_SEL 0x001E 37 #define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
38 #define S1DREG_MEM_CNF 0x0020 38 #define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
39 #define S1DREG_SDRAM_REF_RATE 0x0021 39 #define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */
40 #define S1DREG_SDRAM_TC0 0x002A 40 #define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
41 #define S1DREG_SDRAM_TC1 0x002B 41 #define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
42 #define S1DREG_PANEL_TYPE 0x0030 42 #define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */
43 #define S1DREG_MOD_RATE 0x0031 43 #define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
45 #define S1DREG_LCD_NDISP_HPER 0x0034 45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
46 #define S1DREG_TFT_FPLINE_START 0x0035 46 #define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A 50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
51 #define S1DREG_TFT_FPFRAME_START 0x003B 51 #define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C 52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
53 #define S1DREG_LCD_DISP_MODE 0x0040 53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
54 #define S1DREG_LCD_MISC 0x0041 54 #define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
59 #define S1DREG_LCD_MEM_OFF1 0x0047 59 #define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
60 #define S1DREG_LCD_PIX_PAN 0x0048 60 #define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A 61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B 62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
64 #define S1DREG_CRT_NDISP_HPER 0x0052 64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
65 #define S1DREG_CRT_HRTC_START 0x0053 65 #define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
66 #define S1DREG_CRT_HRTC_PWIDTH 0x0054 66 #define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
67 #define S1DREG_CRT_DISP_VHEIGHT0 0x0056 67 #define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
68 #define S1DREG_CRT_DISP_VHEIGHT1 0x0057 68 #define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
69 #define S1DREG_CRT_NDISP_VPER 0x0058 69 #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
70 #define S1DREG_CRT_VRTC_START 0x0059 70 #define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
71 #define S1DREG_CRT_VRTC_PWIDTH 0x005A 71 #define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
72 #define S1DREG_TV_OUT_CTL 0x005B 72 #define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */
73 #define S1DREG_CRT_DISP_MODE 0x0060 73 #define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
74 #define S1DREG_CRT_DISP_START0 0x0062 74 #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
75 #define S1DREG_CRT_DISP_START1 0x0063 75 #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
76 #define S1DREG_CRT_DISP_START2 0x0064 76 #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
77 #define S1DREG_CRT_MEM_OFF0 0x0066 77 #define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
78 #define S1DREG_CRT_MEM_OFF1 0x0067 78 #define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
79 #define S1DREG_CRT_PIX_PAN 0x0068 79 #define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */
80 #define S1DREG_CRT_DISP_FIFO_HTC 0x006A 80 #define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
81 #define S1DREG_CRT_DISP_FIFO_LTC 0x006B 81 #define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
82 #define S1DREG_LCD_CUR_CTL 0x0070 82 #define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */
83 #define S1DREG_LCD_CUR_START 0x0071 83 #define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
84 #define S1DREG_LCD_CUR_XPOS0 0x0072 84 #define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */
85 #define S1DREG_LCD_CUR_XPOS1 0x0073 85 #define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */
86 #define S1DREG_LCD_CUR_YPOS0 0x0074 86 #define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */
87 #define S1DREG_LCD_CUR_YPOS1 0x0075 87 #define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */
88 #define S1DREG_LCD_CUR_BCTL0 0x0076 88 #define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */
89 #define S1DREG_LCD_CUR_GCTL0 0x0077 89 #define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */
90 #define S1DREG_LCD_CUR_RCTL0 0x0078 90 #define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */
91 #define S1DREG_LCD_CUR_BCTL1 0x007A 91 #define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */
92 #define S1DREG_LCD_CUR_GCTL1 0x007B 92 #define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */
93 #define S1DREG_LCD_CUR_RCTL1 0x007C 93 #define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */
94 #define S1DREG_LCD_CUR_FIFO_HTC 0x007E 94 #define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */
95 #define S1DREG_CRT_CUR_CTL 0x0080 95 #define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */
96 #define S1DREG_CRT_CUR_START 0x0081 96 #define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
97 #define S1DREG_CRT_CUR_XPOS0 0x0082 97 #define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */
98 #define S1DREG_CRT_CUR_XPOS1 0x0083 98 #define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */
99 #define S1DREG_CRT_CUR_YPOS0 0x0084 99 #define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */
100 #define S1DREG_CRT_CUR_YPOS1 0x0085 100 #define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */
101 #define S1DREG_CRT_CUR_BCTL0 0x0086 101 #define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */
102 #define S1DREG_CRT_CUR_GCTL0 0x0087 102 #define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */
103 #define S1DREG_CRT_CUR_RCTL0 0x0088 103 #define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */
104 #define S1DREG_CRT_CUR_BCTL1 0x008A 104 #define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */
105 #define S1DREG_CRT_CUR_GCTL1 0x008B 105 #define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */
106 #define S1DREG_CRT_CUR_RCTL1 0x008C 106 #define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */
107 #define S1DREG_CRT_CUR_FIFO_HTC 0x008E 107 #define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */
108 #define S1DREG_BBLT_CTL0 0x0100 108 #define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */
109 #define S1DREG_BBLT_CTL1 0x0101 109 #define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */
110 #define S1DREG_BBLT_CC_EXP 0x0102 110 #define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */
111 #define S1DREG_BBLT_OP 0x0103 111 #define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */
112 #define S1DREG_BBLT_SRC_START0 0x0104 112 #define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
113 #define S1DREG_BBLT_SRC_START1 0x0105 113 #define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
114 #define S1DREG_BBLT_SRC_START2 0x0106 114 #define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
115 #define S1DREG_BBLT_DST_START0 0x0108 115 #define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
116 #define S1DREG_BBLT_DST_START1 0x0109 116 #define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
117 #define S1DREG_BBLT_DST_START2 0x010A 117 #define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
118 #define S1DREG_BBLT_MEM_OFF0 0x010C 118 #define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
119 #define S1DREG_BBLT_MEM_OFF1 0x010D 119 #define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
120 #define S1DREG_BBLT_WIDTH0 0x0110 120 #define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
121 #define S1DREG_BBLT_WIDTH1 0x0111 121 #define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
122 #define S1DREG_BBLT_HEIGHT0 0x0112 122 #define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */
123 #define S1DREG_BBLT_HEIGHT1 0x0113 123 #define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */
124 #define S1DREG_BBLT_BGC0 0x0114 124 #define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */
125 #define S1DREG_BBLT_BGC1 0x0115 125 #define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */
126 #define S1DREG_BBLT_FGC0 0x0118 126 #define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */
127 #define S1DREG_BBLT_FGC1 0x0119 127 #define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */
128 #define S1DREG_LKUP_MODE 0x01E0 128 #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
129 #define S1DREG_LKUP_ADDR 0x01E2 129 #define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
130 #define S1DREG_LKUP_DATA 0x01E4 130 #define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
131 #define S1DREG_PS_CNF 0x01F0 131 #define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */
132 #define S1DREG_PS_STATUS 0x01F1 132 #define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */
133 #define S1DREG_CPU2MEM_WDOGT 0x01F4 133 #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
134 #define S1DREG_COM_DISP_MODE 0x01FC 134 #define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
135 135
136 #define S1DREG_DELAYOFF 0xFFFE 136 #define S1DREG_DELAYOFF 0xFFFE
137 #define S1DREG_DELAYON 0xFFFF 137 #define S1DREG_DELAYON 0xFFFF
138 138
139 #define BBLT_SOLID_FILL 0x0c 139 #define BBLT_SOLID_FILL 0x0c
140 140
141 141
142 /* Note: all above defines should go in separa 142 /* Note: all above defines should go in separate header files
143 when implementing other S1D13xxx chip suppo 143 when implementing other S1D13xxx chip support. */
144 144
145 struct s1d13xxxfb_regval { 145 struct s1d13xxxfb_regval {
146 u16 addr; 146 u16 addr;
147 u8 value; 147 u8 value;
148 }; 148 };
149 149
150 struct s1d13xxxfb_par { 150 struct s1d13xxxfb_par {
151 void __iomem *regs; 151 void __iomem *regs;
152 unsigned char display; 152 unsigned char display;
153 unsigned char prod_id; 153 unsigned char prod_id;
154 unsigned char revision; 154 unsigned char revision;
155 155
156 unsigned int pseudo_palette[16]; 156 unsigned int pseudo_palette[16];
157 #ifdef CONFIG_PM 157 #ifdef CONFIG_PM
158 void *regs_save; /* pm 158 void *regs_save; /* pm saves all registers here */
159 void *disp_save; /* pm 159 void *disp_save; /* pm saves entire screen here */
160 #endif 160 #endif
161 }; 161 };
162 162
163 struct s1d13xxxfb_pdata { 163 struct s1d13xxxfb_pdata {
164 const struct s1d13xxxfb_regval *initr 164 const struct s1d13xxxfb_regval *initregs;
165 const unsigned int initre 165 const unsigned int initregssize;
166 void (*plat 166 void (*platform_init_video)(void);
167 #ifdef CONFIG_PM 167 #ifdef CONFIG_PM
168 int (*plat 168 int (*platform_suspend_video)(void);
169 int (*plat 169 int (*platform_resume_video)(void);
170 #endif 170 #endif
171 }; 171 };
172 172
173 #endif 173 #endif
174 174
175 175
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