1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2018-2020 Christoph Hellwig. !! 3 * DMA operations that map physical memory directly without using an IOMMU or
4 * !! 4 * flushing caches.
5 * DMA operations that map physical memory dir <<
6 */ 5 */
7 #include <linux/memblock.h> /* for max_pfn */ <<
8 #include <linux/export.h> 6 #include <linux/export.h>
9 #include <linux/mm.h> 7 #include <linux/mm.h>
10 #include <linux/dma-map-ops.h> !! 8 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h> 9 #include <linux/scatterlist.h>
>> 10 #include <linux/dma-contiguous.h>
12 #include <linux/pfn.h> 11 #include <linux/pfn.h>
13 #include <linux/vmalloc.h> <<
14 #include <linux/set_memory.h> 12 #include <linux/set_memory.h>
15 #include <linux/slab.h> !! 13
16 #include "direct.h" !! 14 #define DIRECT_MAPPING_ERROR 0
17 15
18 /* 16 /*
19 * Most architectures use ZONE_DMA for the fir !! 17 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
20 * it for entirely different regions. In that !! 18 * some use it for entirely different regions:
21 * override the variable below for dma-direct <<
22 */ 19 */
23 u64 zone_dma_limit __ro_after_init = DMA_BIT_M !! 20 #ifndef ARCH_ZONE_DMA_BITS
24 !! 21 #define ARCH_ZONE_DMA_BITS 24
25 static inline dma_addr_t phys_to_dma_direct(st !! 22 #endif
26 phys_addr_t phys) <<
27 { <<
28 if (force_dma_unencrypted(dev)) <<
29 return phys_to_dma_unencrypted <<
30 return phys_to_dma(dev, phys); <<
31 } <<
32 <<
33 static inline struct page *dma_direct_to_page( <<
34 dma_addr_t dma_addr) <<
35 { <<
36 return pfn_to_page(PHYS_PFN(dma_to_phy <<
37 } <<
38 23
39 u64 dma_direct_get_required_mask(struct device !! 24 /*
>> 25 * For AMD SEV all DMA must be to unencrypted addresses.
>> 26 */
>> 27 static inline bool force_dma_unencrypted(void)
40 { 28 {
41 phys_addr_t phys = (phys_addr_t)(max_p !! 29 return sev_active();
42 u64 max_dma = phys_to_dma_direct(dev, <<
43 <<
44 return (1ULL << (fls64(max_dma) - 1)) <<
45 } 30 }
46 31
47 static gfp_t dma_direct_optimal_gfp_mask(struc !! 32 static bool
>> 33 check_addr(struct device *dev, dma_addr_t dma_addr, size_t size,
>> 34 const char *caller)
48 { 35 {
49 u64 dma_limit = min_not_zero( !! 36 if (unlikely(dev && !dma_capable(dev, dma_addr, size))) {
50 dev->coherent_dma_mask, !! 37 if (!dev->dma_mask) {
51 dev->bus_dma_limit); !! 38 dev_err(dev,
52 !! 39 "%s: call on device without dma_mask\n",
53 /* !! 40 caller);
54 * Optimistically try the zone that th !! 41 return false;
55 * into first. If that returns memory !! 42 }
56 * we will fallback to the next lower <<
57 * <<
58 * Note that GFP_DMA32 and GFP_DMA are <<
59 * zones. <<
60 */ <<
61 *phys_limit = dma_to_phys(dev, dma_lim <<
62 if (*phys_limit <= zone_dma_limit) <<
63 return GFP_DMA; <<
64 if (*phys_limit <= DMA_BIT_MASK(32)) <<
65 return GFP_DMA32; <<
66 return 0; <<
67 } <<
68 <<
69 bool dma_coherent_ok(struct device *dev, phys_ <<
70 { <<
71 dma_addr_t dma_addr = phys_to_dma_dire <<
72 43
73 if (dma_addr == DMA_MAPPING_ERROR) !! 44 if (*dev->dma_mask >= DMA_BIT_MASK(32)) {
>> 45 dev_err(dev,
>> 46 "%s: overflow %pad+%zu of device mask %llx\n",
>> 47 caller, &dma_addr, size, *dev->dma_mask);
>> 48 }
74 return false; 49 return false;
75 return dma_addr + size - 1 <= !! 50 }
76 min_not_zero(dev->coherent_dma !! 51 return true;
77 } <<
78 <<
79 static int dma_set_decrypted(struct device *de <<
80 { <<
81 if (!force_dma_unencrypted(dev)) <<
82 return 0; <<
83 return set_memory_decrypted((unsigned <<
84 } <<
85 <<
86 static int dma_set_encrypted(struct device *de <<
87 { <<
88 int ret; <<
89 <<
90 if (!force_dma_unencrypted(dev)) <<
91 return 0; <<
92 ret = set_memory_encrypted((unsigned l <<
93 if (ret) <<
94 pr_warn_ratelimited("leaking D <<
95 return ret; <<
96 } 52 }
97 53
98 static void __dma_direct_free_pages(struct dev !! 54 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
99 size_t siz <<
100 { 55 {
101 if (swiotlb_free(dev, page, size)) !! 56 dma_addr_t addr = force_dma_unencrypted() ?
102 return; !! 57 __phys_to_dma(dev, phys) : phys_to_dma(dev, phys);
103 dma_free_contiguous(dev, page, size); !! 58 return addr + size - 1 <= dev->coherent_dma_mask;
104 } 59 }
105 60
106 static struct page *dma_direct_alloc_swiotlb(s !! 61 void *dma_direct_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
>> 62 gfp_t gfp, unsigned long attrs)
107 { 63 {
108 struct page *page = swiotlb_alloc(dev, !! 64 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
109 !! 65 int page_order = get_order(size);
110 if (page && !dma_coherent_ok(dev, page <<
111 swiotlb_free(dev, page, size); <<
112 return NULL; <<
113 } <<
114 <<
115 return page; <<
116 } <<
117 <<
118 static struct page *__dma_direct_alloc_pages(s <<
119 gfp_t gfp, bool allow_highmem) <<
120 { <<
121 int node = dev_to_node(dev); <<
122 struct page *page = NULL; 66 struct page *page = NULL;
123 u64 phys_limit; !! 67 void *ret;
124 68
125 WARN_ON_ONCE(!PAGE_ALIGNED(size)); !! 69 /* we always manually zero the memory once we are done: */
>> 70 gfp &= ~__GFP_ZERO;
126 71
127 if (is_swiotlb_for_alloc(dev)) !! 72 /* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */
128 return dma_direct_alloc_swiotl !! 73 if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
>> 74 gfp |= GFP_DMA;
>> 75 if (dev->coherent_dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
>> 76 gfp |= GFP_DMA32;
129 77
130 gfp |= dma_direct_optimal_gfp_mask(dev !! 78 again:
131 page = dma_alloc_contiguous(dev, size, !! 79 /* CMA can be used only in the context which permits sleeping */
132 if (page) { !! 80 if (gfpflags_allow_blocking(gfp)) {
133 if (!dma_coherent_ok(dev, page !! 81 page = dma_alloc_from_contiguous(dev, count, page_order,
134 (!allow_highmem && PageHig !! 82 gfp & __GFP_NOWARN);
135 dma_free_contiguous(de !! 83 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
>> 84 dma_release_from_contiguous(dev, page, count);
136 page = NULL; 85 page = NULL;
137 } 86 }
138 } 87 }
139 again: <<
140 if (!page) 88 if (!page)
141 page = alloc_pages_node(node, !! 89 page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
>> 90
142 if (page && !dma_coherent_ok(dev, page 91 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
143 __free_pages(page, get_order(s !! 92 __free_pages(page, page_order);
144 page = NULL; 93 page = NULL;
145 94
146 if (IS_ENABLED(CONFIG_ZONE_DMA 95 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
147 phys_limit < DMA_BIT_MASK( !! 96 dev->coherent_dma_mask < DMA_BIT_MASK(64) &&
148 !(gfp & (GFP_DMA32 | GFP_D 97 !(gfp & (GFP_DMA32 | GFP_DMA))) {
149 gfp |= GFP_DMA32; 98 gfp |= GFP_DMA32;
150 goto again; 99 goto again;
151 } 100 }
152 101
153 if (IS_ENABLED(CONFIG_ZONE_DMA !! 102 if (IS_ENABLED(CONFIG_ZONE_DMA) &&
>> 103 dev->coherent_dma_mask < DMA_BIT_MASK(32) &&
>> 104 !(gfp & GFP_DMA)) {
154 gfp = (gfp & ~GFP_DMA3 105 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
155 goto again; 106 goto again;
156 } 107 }
157 } 108 }
158 109
159 return page; <<
160 } <<
161 <<
162 /* <<
163 * Check if a potentially blocking operations <<
164 * pools for the given device/gfp. <<
165 */ <<
166 static bool dma_direct_use_pool(struct device <<
167 { <<
168 return !gfpflags_allow_blocking(gfp) & <<
169 } <<
170 <<
171 static void *dma_direct_alloc_from_pool(struct <<
172 dma_addr_t *dma_handle, gfp_t <<
173 { <<
174 struct page *page; <<
175 u64 phys_limit; <<
176 void *ret; <<
177 <<
178 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DM <<
179 return NULL; <<
180 <<
181 gfp |= dma_direct_optimal_gfp_mask(dev <<
182 page = dma_alloc_from_pool(dev, size, <<
183 if (!page) <<
184 return NULL; <<
185 *dma_handle = phys_to_dma_direct(dev, <<
186 return ret; <<
187 } <<
188 <<
189 static void *dma_direct_alloc_no_mapping(struc <<
190 dma_addr_t *dma_handle, gfp_t <<
191 { <<
192 struct page *page; <<
193 <<
194 page = __dma_direct_alloc_pages(dev, s <<
195 if (!page) <<
196 return NULL; <<
197 <<
198 /* remove any dirty cache lines on the <<
199 if (!PageHighMem(page)) <<
200 arch_dma_prep_coherent(page, s <<
201 <<
202 /* return the page pointer as the opaq <<
203 *dma_handle = phys_to_dma_direct(dev, <<
204 return page; <<
205 } <<
206 <<
207 void *dma_direct_alloc(struct device *dev, siz <<
208 dma_addr_t *dma_handle, gfp_t <<
209 { <<
210 bool remap = false, set_uncached = fal <<
211 struct page *page; <<
212 void *ret; <<
213 <<
214 size = PAGE_ALIGN(size); <<
215 if (attrs & DMA_ATTR_NO_WARN) <<
216 gfp |= __GFP_NOWARN; <<
217 <<
218 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN <<
219 !force_dma_unencrypted(dev) && !is <<
220 return dma_direct_alloc_no_map <<
221 <<
222 if (!dev_is_dma_coherent(dev)) { <<
223 if (IS_ENABLED(CONFIG_ARCH_HAS <<
224 !is_swiotlb_for_alloc(dev) <<
225 return arch_dma_alloc( <<
226 <<
227 <<
228 /* <<
229 * If there is a global pool, <<
230 * non-coherent devices. <<
231 */ <<
232 if (IS_ENABLED(CONFIG_DMA_GLOB <<
233 return dma_alloc_from_ <<
234 dma_ha <<
235 <<
236 /* <<
237 * Otherwise we require the ar <<
238 * mark arbitrary parts of the <<
239 * or remapped it uncached. <<
240 */ <<
241 set_uncached = IS_ENABLED(CONF <<
242 remap = IS_ENABLED(CONFIG_DMA_ <<
243 if (!set_uncached && !remap) { <<
244 pr_warn_once("coherent <<
245 return NULL; <<
246 } <<
247 } <<
248 <<
249 /* <<
250 * Remapping or decrypting memory may <<
251 * the atomic pools instead if we aren <<
252 */ <<
253 if ((remap || force_dma_unencrypted(de <<
254 dma_direct_use_pool(dev, gfp)) <<
255 return dma_direct_alloc_from_p <<
256 <<
257 /* we always manually zero the memory <<
258 page = __dma_direct_alloc_pages(dev, s <<
259 if (!page) 110 if (!page)
260 return NULL; 111 return NULL;
261 !! 112 ret = page_address(page);
262 /* !! 113 if (force_dma_unencrypted()) {
263 * dma_alloc_contiguous can return hig !! 114 set_memory_decrypted((unsigned long)ret, 1 << page_order);
264 * combination the cma= arguments and !! 115 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
265 * remapped to return a kernel virtual <<
266 */ <<
267 if (PageHighMem(page)) { <<
268 remap = true; <<
269 set_uncached = false; <<
270 } <<
271 <<
272 if (remap) { <<
273 pgprot_t prot = dma_pgprot(dev <<
274 <<
275 if (force_dma_unencrypted(dev) <<
276 prot = pgprot_decrypte <<
277 <<
278 /* remove any dirty cache line <<
279 arch_dma_prep_coherent(page, s <<
280 <<
281 /* create a coherent mapping * <<
282 ret = dma_common_contiguous_re <<
283 __builtin_retu <<
284 if (!ret) <<
285 goto out_free_pages; <<
286 } else { 116 } else {
287 ret = page_address(page); !! 117 *dma_handle = phys_to_dma(dev, page_to_phys(page));
288 if (dma_set_decrypted(dev, ret <<
289 goto out_leak_pages; <<
290 } 118 }
291 <<
292 memset(ret, 0, size); 119 memset(ret, 0, size);
293 <<
294 if (set_uncached) { <<
295 arch_dma_prep_coherent(page, s <<
296 ret = arch_dma_set_uncached(re <<
297 if (IS_ERR(ret)) <<
298 goto out_encrypt_pages <<
299 } <<
300 <<
301 *dma_handle = phys_to_dma_direct(dev, <<
302 return ret; 120 return ret;
303 <<
304 out_encrypt_pages: <<
305 if (dma_set_encrypted(dev, page_addres <<
306 return NULL; <<
307 out_free_pages: <<
308 __dma_direct_free_pages(dev, page, siz <<
309 return NULL; <<
310 out_leak_pages: <<
311 return NULL; <<
312 } 121 }
313 122
314 void dma_direct_free(struct device *dev, size_ !! 123 /*
315 void *cpu_addr, dma_addr_t dma !! 124 * NOTE: this function must never look at the dma_addr argument, because we want
>> 125 * to be able to use it as a helper for iommu implementations as well.
>> 126 */
>> 127 void dma_direct_free(struct device *dev, size_t size, void *cpu_addr,
>> 128 dma_addr_t dma_addr, unsigned long attrs)
316 { 129 {
>> 130 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
317 unsigned int page_order = get_order(si 131 unsigned int page_order = get_order(size);
318 132
319 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN !! 133 if (force_dma_unencrypted())
320 !force_dma_unencrypted(dev) && !is !! 134 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
321 /* cpu_addr is a struct page c !! 135 if (!dma_release_from_contiguous(dev, virt_to_page(cpu_addr), count))
322 dma_free_contiguous(dev, cpu_a !! 136 free_pages((unsigned long)cpu_addr, page_order);
323 return; <<
324 } <<
325 <<
326 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALL <<
327 !dev_is_dma_coherent(dev) && <<
328 !is_swiotlb_for_alloc(dev)) { <<
329 arch_dma_free(dev, size, cpu_a <<
330 return; <<
331 } <<
332 <<
333 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) <<
334 !dev_is_dma_coherent(dev)) { <<
335 if (!dma_release_from_global_c <<
336 WARN_ON_ONCE(1); <<
337 return; <<
338 } <<
339 <<
340 /* If cpu_addr is not from an atomic p <<
341 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO <<
342 dma_free_from_pool(dev, cpu_addr, <<
343 return; <<
344 <<
345 if (is_vmalloc_addr(cpu_addr)) { <<
346 vunmap(cpu_addr); <<
347 } else { <<
348 if (IS_ENABLED(CONFIG_ARCH_HAS <<
349 arch_dma_clear_uncache <<
350 if (dma_set_encrypted(dev, cpu <<
351 return; <<
352 } <<
353 <<
354 __dma_direct_free_pages(dev, dma_direc <<
355 } 137 }
356 138
357 struct page *dma_direct_alloc_pages(struct dev !! 139 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
358 dma_addr_t *dma_handle, enum d !! 140 unsigned long offset, size_t size, enum dma_data_direction dir,
359 { !! 141 unsigned long attrs)
360 struct page *page; <<
361 void *ret; <<
362 <<
363 if (force_dma_unencrypted(dev) && dma_ <<
364 return dma_direct_alloc_from_p <<
365 <<
366 page = __dma_direct_alloc_pages(dev, s <<
367 if (!page) <<
368 return NULL; <<
369 <<
370 ret = page_address(page); <<
371 if (dma_set_decrypted(dev, ret, size)) <<
372 goto out_leak_pages; <<
373 memset(ret, 0, size); <<
374 *dma_handle = phys_to_dma_direct(dev, <<
375 return page; <<
376 out_leak_pages: <<
377 return NULL; <<
378 } <<
379 <<
380 void dma_direct_free_pages(struct device *dev, <<
381 struct page *page, dma_addr_t <<
382 enum dma_data_direction dir) <<
383 { <<
384 void *vaddr = page_address(page); <<
385 <<
386 /* If cpu_addr is not from an atomic p <<
387 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO <<
388 dma_free_from_pool(dev, vaddr, siz <<
389 return; <<
390 <<
391 if (dma_set_encrypted(dev, vaddr, size <<
392 return; <<
393 __dma_direct_free_pages(dev, page, siz <<
394 } <<
395 <<
396 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVIC <<
397 defined(CONFIG_SWIOTLB) <<
398 void dma_direct_sync_sg_for_device(struct devi <<
399 struct scatterlist *sgl, int n <<
400 { <<
401 struct scatterlist *sg; <<
402 int i; <<
403 <<
404 for_each_sg(sgl, sg, nents, i) { <<
405 phys_addr_t paddr = dma_to_phy <<
406 <<
407 swiotlb_sync_single_for_device <<
408 <<
409 if (!dev_is_dma_coherent(dev)) <<
410 arch_sync_dma_for_devi <<
411 dir); <<
412 } <<
413 } <<
414 #endif <<
415 <<
416 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) <<
417 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_A <<
418 defined(CONFIG_SWIOTLB) <<
419 void dma_direct_sync_sg_for_cpu(struct device <<
420 struct scatterlist *sgl, int n <<
421 { <<
422 struct scatterlist *sg; <<
423 int i; <<
424 <<
425 for_each_sg(sgl, sg, nents, i) { <<
426 phys_addr_t paddr = dma_to_phy <<
427 <<
428 if (!dev_is_dma_coherent(dev)) <<
429 arch_sync_dma_for_cpu( <<
430 <<
431 swiotlb_sync_single_for_cpu(de <<
432 <<
433 if (dir == DMA_FROM_DEVICE) <<
434 arch_dma_mark_clean(pa <<
435 } <<
436 <<
437 if (!dev_is_dma_coherent(dev)) <<
438 arch_sync_dma_for_cpu_all(); <<
439 } <<
440 <<
441 /* <<
442 * Unmaps segments, except for ones marked as <<
443 * require any further action as they contain <<
444 */ <<
445 void dma_direct_unmap_sg(struct device *dev, s <<
446 int nents, enum dma_data_direc <<
447 { 142 {
448 struct scatterlist *sg; !! 143 dma_addr_t dma_addr = phys_to_dma(dev, page_to_phys(page)) + offset;
449 int i; <<
450 144
451 for_each_sg(sgl, sg, nents, i) { !! 145 if (!check_addr(dev, dma_addr, size, __func__))
452 if (sg_dma_is_bus_address(sg)) !! 146 return DIRECT_MAPPING_ERROR;
453 sg_dma_unmark_bus_addr !! 147 return dma_addr;
454 else <<
455 dma_direct_unmap_page( <<
456 <<
457 } <<
458 } 148 }
459 #endif <<
460 149
461 int dma_direct_map_sg(struct device *dev, stru 150 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
462 enum dma_data_direction dir, u 151 enum dma_data_direction dir, unsigned long attrs)
463 { 152 {
464 struct pci_p2pdma_map_state p2pdma_sta !! 153 int i;
465 enum pci_p2pdma_map_type map; <<
466 struct scatterlist *sg; 154 struct scatterlist *sg;
467 int i, ret; <<
468 155
469 for_each_sg(sgl, sg, nents, i) { 156 for_each_sg(sgl, sg, nents, i) {
470 if (is_pci_p2pdma_page(sg_page !! 157 BUG_ON(!sg_page(sg));
471 map = pci_p2pdma_map_s <<
472 switch (map) { <<
473 case PCI_P2PDMA_MAP_BU <<
474 continue; <<
475 case PCI_P2PDMA_MAP_TH <<
476 /* <<
477 * Any P2P map <<
478 * host bridge <<
479 * address and <<
480 * done with d <<
481 */ <<
482 break; <<
483 default: <<
484 ret = -EREMOTE <<
485 goto out_unmap <<
486 } <<
487 } <<
488 158
489 sg->dma_address = dma_direct_m !! 159 sg_dma_address(sg) = phys_to_dma(dev, sg_phys(sg));
490 sg->offset, sg !! 160 if (!check_addr(dev, sg_dma_address(sg), sg->length, __func__))
491 if (sg->dma_address == DMA_MAP !! 161 return 0;
492 ret = -EIO; <<
493 goto out_unmap; <<
494 } <<
495 sg_dma_len(sg) = sg->length; 162 sg_dma_len(sg) = sg->length;
496 } 163 }
497 164
498 return nents; 165 return nents;
499 <<
500 out_unmap: <<
501 dma_direct_unmap_sg(dev, sgl, i, dir, <<
502 return ret; <<
503 } <<
504 <<
505 dma_addr_t dma_direct_map_resource(struct devi <<
506 size_t size, enum dma_data_dir <<
507 { <<
508 dma_addr_t dma_addr = paddr; <<
509 <<
510 if (unlikely(!dma_capable(dev, dma_add <<
511 dev_err_once(dev, <<
512 "DMA addr %pad+%z <<
513 &dma_addr, size, <<
514 WARN_ON_ONCE(1); <<
515 return DMA_MAPPING_ERROR; <<
516 } <<
517 <<
518 return dma_addr; <<
519 } <<
520 <<
521 int dma_direct_get_sgtable(struct device *dev, <<
522 void *cpu_addr, dma_addr_t dma <<
523 unsigned long attrs) <<
524 { <<
525 struct page *page = dma_direct_to_page <<
526 int ret; <<
527 <<
528 ret = sg_alloc_table(sgt, 1, GFP_KERNE <<
529 if (!ret) <<
530 sg_set_page(sgt->sgl, page, PA <<
531 return ret; <<
532 } <<
533 <<
534 bool dma_direct_can_mmap(struct device *dev) <<
535 { <<
536 return dev_is_dma_coherent(dev) || <<
537 IS_ENABLED(CONFIG_DMA_NONCOHER <<
538 } <<
539 <<
540 int dma_direct_mmap(struct device *dev, struct <<
541 void *cpu_addr, dma_addr_t dma <<
542 unsigned long attrs) <<
543 { <<
544 unsigned long user_count = vma_pages(v <<
545 unsigned long count = PAGE_ALIGN(size) <<
546 unsigned long pfn = PHYS_PFN(dma_to_ph <<
547 int ret = -ENXIO; <<
548 <<
549 vma->vm_page_prot = dma_pgprot(dev, vm <<
550 if (force_dma_unencrypted(dev)) <<
551 vma->vm_page_prot = pgprot_dec <<
552 <<
553 if (dma_mmap_from_dev_coherent(dev, vm <<
554 return ret; <<
555 if (dma_mmap_from_global_coherent(vma, <<
556 return ret; <<
557 <<
558 if (vma->vm_pgoff >= count || user_cou <<
559 return -ENXIO; <<
560 return remap_pfn_range(vma, vma->vm_st <<
561 user_count << PAGE_SHI <<
562 } 166 }
563 167
564 int dma_direct_supported(struct device *dev, u 168 int dma_direct_supported(struct device *dev, u64 mask)
565 { 169 {
566 u64 min_mask = (max_pfn - 1) << PAGE_S !! 170 #ifdef CONFIG_ZONE_DMA
567 !! 171 /*
>> 172 * This check needs to be against the actual bit mask value, so
>> 173 * use __phys_to_dma() here so that the SME encryption mask isn't
>> 174 * part of the check.
>> 175 */
>> 176 if (mask < __phys_to_dma(dev, DMA_BIT_MASK(ARCH_ZONE_DMA_BITS)))
>> 177 return 0;
>> 178 #else
568 /* 179 /*
569 * Because 32-bit DMA masks are so com 180 * Because 32-bit DMA masks are so common we expect every architecture
570 * to be able to satisfy them - either 181 * to be able to satisfy them - either by not supporting more physical
571 * memory, or by providing a ZONE_DMA3 182 * memory, or by providing a ZONE_DMA32. If neither is the case, the
572 * architecture needs to use an IOMMU 183 * architecture needs to use an IOMMU instead of the direct mapping.
>> 184 *
>> 185 * This check needs to be against the actual bit mask value, so
>> 186 * use __phys_to_dma() here so that the SME encryption mask isn't
>> 187 * part of the check.
573 */ 188 */
574 if (mask >= DMA_BIT_MASK(32)) !! 189 if (mask < __phys_to_dma(dev, DMA_BIT_MASK(32)))
575 return 1; !! 190 return 0;
576 !! 191 #endif
577 /* 192 /*
578 * This check needs to be against the !! 193 * Upstream PCI/PCIe bridges or SoC interconnects may not carry
579 * phys_to_dma_unencrypted() here so t !! 194 * as many DMA address bits as the device itself supports.
580 * part of the check. <<
581 */ 195 */
582 if (IS_ENABLED(CONFIG_ZONE_DMA)) !! 196 if (dev->bus_dma_mask && mask > dev->bus_dma_mask)
583 min_mask = min_t(u64, min_mask !! 197 return 0;
584 return mask >= phys_to_dma_unencrypted !! 198 return 1;
585 } <<
586 <<
587 /* <<
588 * To check whether all ram resource ranges ar <<
589 * Returns 0 when further check is needed <<
590 * Returns 1 if there is some RAM range can't <<
591 */ <<
592 static int check_ram_in_range_map(unsigned lon <<
593 unsigned lon <<
594 { <<
595 unsigned long end_pfn = start_pfn + nr <<
596 const struct bus_dma_region *bdr = NUL <<
597 const struct bus_dma_region *m; <<
598 struct device *dev = data; <<
599 <<
600 while (start_pfn < end_pfn) { <<
601 for (m = dev->dma_range_map; P <<
602 unsigned long cpu_star <<
603 <<
604 if (start_pfn >= cpu_s <<
605 start_pfn - cpu_st <<
606 bdr = m; <<
607 break; <<
608 } <<
609 } <<
610 if (!bdr) <<
611 return 1; <<
612 <<
613 start_pfn = PFN_DOWN(bdr->cpu_ <<
614 } <<
615 <<
616 return 0; <<
617 } <<
618 <<
619 bool dma_direct_all_ram_mapped(struct device * <<
620 { <<
621 if (!dev->dma_range_map) <<
622 return true; <<
623 return !walk_system_ram_range(0, PFN_D <<
624 check_ra <<
625 } <<
626 <<
627 size_t dma_direct_max_mapping_size(struct devi <<
628 { <<
629 /* If SWIOTLB is active, use its maxim <<
630 if (is_swiotlb_active(dev) && <<
631 (dma_addressing_limited(dev) || is <<
632 return swiotlb_max_mapping_siz <<
633 return SIZE_MAX; <<
634 } 199 }
635 200
636 bool dma_direct_need_sync(struct device *dev, !! 201 int dma_direct_mapping_error(struct device *dev, dma_addr_t dma_addr)
637 { 202 {
638 return !dev_is_dma_coherent(dev) || !! 203 return dma_addr == DIRECT_MAPPING_ERROR;
639 swiotlb_find_pool(dev, dma_to_p <<
640 } 204 }
641 205
642 /** !! 206 const struct dma_map_ops dma_direct_ops = {
643 * dma_direct_set_offset - Assign scalar offse !! 207 .alloc = dma_direct_alloc,
644 * @dev: device pointer; needed to "own !! 208 .free = dma_direct_free,
645 * @cpu_start: beginning of memory region cov !! 209 .map_page = dma_direct_map_page,
646 * @dma_start: beginning of DMA/PCI region co !! 210 .map_sg = dma_direct_map_sg,
647 * @size: size of the region. !! 211 .dma_supported = dma_direct_supported,
648 * !! 212 .mapping_error = dma_direct_mapping_error,
649 * This is for the simple case of a uniform of !! 213 };
650 * be discovered by "dma-ranges". !! 214 EXPORT_SYMBOL(dma_direct_ops);
651 * <<
652 * It returns -ENOMEM if out of memory, -EINVA <<
653 * already exists, 0 otherwise. <<
654 * <<
655 * Note: any call to this from a driver is a b <<
656 * to be described by the device tree or other <<
657 */ <<
658 int dma_direct_set_offset(struct device *dev, <<
659 dma_addr_t dma_start, <<
660 { <<
661 struct bus_dma_region *map; <<
662 u64 offset = (u64)cpu_start - (u64)dma <<
663 <<
664 if (dev->dma_range_map) { <<
665 dev_err(dev, "attempt to add D <<
666 return -EINVAL; <<
667 } <<
668 <<
669 if (!offset) <<
670 return 0; <<
671 <<
672 map = kcalloc(2, sizeof(*map), GFP_KER <<
673 if (!map) <<
674 return -ENOMEM; <<
675 map[0].cpu_start = cpu_start; <<
676 map[0].dma_start = dma_start; <<
677 map[0].size = size; <<
678 dev->dma_range_map = map; <<
679 return 0; <<
680 } <<
681 215
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