1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2018-2020 Christoph Hellwig. !! 3 * Copyright (C) 2018 Christoph Hellwig.
4 * 4 *
5 * DMA operations that map physical memory dir 5 * DMA operations that map physical memory directly without using an IOMMU.
6 */ 6 */
7 #include <linux/memblock.h> /* for max_pfn */ 7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h> 8 #include <linux/export.h>
9 #include <linux/mm.h> 9 #include <linux/mm.h>
10 #include <linux/dma-map-ops.h> !! 10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h> 11 #include <linux/scatterlist.h>
>> 12 #include <linux/dma-contiguous.h>
>> 13 #include <linux/dma-noncoherent.h>
12 #include <linux/pfn.h> 14 #include <linux/pfn.h>
13 #include <linux/vmalloc.h> 15 #include <linux/vmalloc.h>
14 #include <linux/set_memory.h> 16 #include <linux/set_memory.h>
15 #include <linux/slab.h> !! 17 #include <linux/swiotlb.h>
16 #include "direct.h" <<
17 18
18 /* 19 /*
19 * Most architectures use ZONE_DMA for the fir !! 20 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it
20 * it for entirely different regions. In that 21 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct 22 * override the variable below for dma-direct to work properly.
22 */ 23 */
23 unsigned int zone_dma_bits __ro_after_init = 2 24 unsigned int zone_dma_bits __ro_after_init = 24;
24 25
25 static inline dma_addr_t phys_to_dma_direct(st 26 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
26 phys_addr_t phys) 27 phys_addr_t phys)
27 { 28 {
28 if (force_dma_unencrypted(dev)) 29 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted !! 30 return __phys_to_dma(dev, phys);
30 return phys_to_dma(dev, phys); 31 return phys_to_dma(dev, phys);
31 } 32 }
32 33
33 static inline struct page *dma_direct_to_page( 34 static inline struct page *dma_direct_to_page(struct device *dev,
34 dma_addr_t dma_addr) 35 dma_addr_t dma_addr)
35 { 36 {
36 return pfn_to_page(PHYS_PFN(dma_to_phy 37 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
37 } 38 }
38 39
39 u64 dma_direct_get_required_mask(struct device 40 u64 dma_direct_get_required_mask(struct device *dev)
40 { 41 {
41 phys_addr_t phys = (phys_addr_t)(max_p 42 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, 43 u64 max_dma = phys_to_dma_direct(dev, phys);
43 44
44 return (1ULL << (fls64(max_dma) - 1)) 45 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
45 } 46 }
46 47
47 static gfp_t dma_direct_optimal_gfp_mask(struc !! 48 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
>> 49 u64 *phys_limit)
48 { 50 {
49 u64 dma_limit = min_not_zero( !! 51 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
50 dev->coherent_dma_mask, !! 52
51 dev->bus_dma_limit); !! 53 if (force_dma_unencrypted(dev))
>> 54 *phys_limit = __dma_to_phys(dev, dma_limit);
>> 55 else
>> 56 *phys_limit = dma_to_phys(dev, dma_limit);
52 57
53 /* 58 /*
54 * Optimistically try the zone that th 59 * Optimistically try the zone that the physical address mask falls
55 * into first. If that returns memory 60 * into first. If that returns memory that isn't actually addressable
56 * we will fallback to the next lower 61 * we will fallback to the next lower zone and try again.
57 * 62 *
58 * Note that GFP_DMA32 and GFP_DMA are 63 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
59 * zones. 64 * zones.
60 */ 65 */
61 *phys_limit = dma_to_phys(dev, dma_lim <<
62 if (*phys_limit <= DMA_BIT_MASK(zone_d 66 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
63 return GFP_DMA; 67 return GFP_DMA;
64 if (*phys_limit <= DMA_BIT_MASK(32)) 68 if (*phys_limit <= DMA_BIT_MASK(32))
65 return GFP_DMA32; 69 return GFP_DMA32;
66 return 0; 70 return 0;
67 } 71 }
68 72
69 bool dma_coherent_ok(struct device *dev, phys_ !! 73 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
70 { <<
71 dma_addr_t dma_addr = phys_to_dma_dire <<
72 <<
73 if (dma_addr == DMA_MAPPING_ERROR) <<
74 return false; <<
75 return dma_addr + size - 1 <= <<
76 min_not_zero(dev->coherent_dma <<
77 } <<
78 <<
79 static int dma_set_decrypted(struct device *de <<
80 { <<
81 if (!force_dma_unencrypted(dev)) <<
82 return 0; <<
83 return set_memory_decrypted((unsigned <<
84 } <<
85 <<
86 static int dma_set_encrypted(struct device *de <<
87 { 74 {
88 int ret; !! 75 return phys_to_dma_direct(dev, phys) + size - 1 <=
89 !! 76 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
90 if (!force_dma_unencrypted(dev)) <<
91 return 0; <<
92 ret = set_memory_encrypted((unsigned l <<
93 if (ret) <<
94 pr_warn_ratelimited("leaking D <<
95 return ret; <<
96 } 77 }
97 78
98 static void __dma_direct_free_pages(struct dev !! 79 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
99 size_t siz !! 80 gfp_t gfp, unsigned long attrs)
100 { <<
101 if (swiotlb_free(dev, page, size)) <<
102 return; <<
103 dma_free_contiguous(dev, page, size); <<
104 } <<
105 <<
106 static struct page *dma_direct_alloc_swiotlb(s <<
107 { <<
108 struct page *page = swiotlb_alloc(dev, <<
109 <<
110 if (page && !dma_coherent_ok(dev, page <<
111 swiotlb_free(dev, page, size); <<
112 return NULL; <<
113 } <<
114 <<
115 return page; <<
116 } <<
117 <<
118 static struct page *__dma_direct_alloc_pages(s <<
119 gfp_t gfp, bool allow_highmem) <<
120 { 81 {
>> 82 size_t alloc_size = PAGE_ALIGN(size);
121 int node = dev_to_node(dev); 83 int node = dev_to_node(dev);
122 struct page *page = NULL; 84 struct page *page = NULL;
123 u64 phys_limit; 85 u64 phys_limit;
124 86
125 WARN_ON_ONCE(!PAGE_ALIGNED(size)); !! 87 if (attrs & DMA_ATTR_NO_WARN)
126 !! 88 gfp |= __GFP_NOWARN;
127 if (is_swiotlb_for_alloc(dev)) <<
128 return dma_direct_alloc_swiotl <<
129 89
130 gfp |= dma_direct_optimal_gfp_mask(dev !! 90 /* we always manually zero the memory once we are done: */
131 page = dma_alloc_contiguous(dev, size, !! 91 gfp &= ~__GFP_ZERO;
132 if (page) { !! 92 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
133 if (!dma_coherent_ok(dev, page !! 93 &phys_limit);
134 (!allow_highmem && PageHig !! 94 page = dma_alloc_contiguous(dev, alloc_size, gfp);
135 dma_free_contiguous(de !! 95 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
136 page = NULL; !! 96 dma_free_contiguous(dev, page, alloc_size);
137 } !! 97 page = NULL;
138 } 98 }
139 again: 99 again:
140 if (!page) 100 if (!page)
141 page = alloc_pages_node(node, !! 101 page = alloc_pages_node(node, gfp, get_order(alloc_size));
142 if (page && !dma_coherent_ok(dev, page 102 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
143 dma_free_contiguous(dev, page, 103 dma_free_contiguous(dev, page, size);
144 page = NULL; 104 page = NULL;
145 105
146 if (IS_ENABLED(CONFIG_ZONE_DMA 106 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
147 phys_limit < DMA_BIT_MASK( 107 phys_limit < DMA_BIT_MASK(64) &&
148 !(gfp & (GFP_DMA32 | GFP_D 108 !(gfp & (GFP_DMA32 | GFP_DMA))) {
149 gfp |= GFP_DMA32; 109 gfp |= GFP_DMA32;
150 goto again; 110 goto again;
151 } 111 }
152 112
153 if (IS_ENABLED(CONFIG_ZONE_DMA 113 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
154 gfp = (gfp & ~GFP_DMA3 114 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
155 goto again; 115 goto again;
156 } 116 }
157 } 117 }
158 118
159 return page; 119 return page;
160 } 120 }
161 121
162 /* !! 122 void *dma_direct_alloc_pages(struct device *dev, size_t size,
163 * Check if a potentially blocking operations <<
164 * pools for the given device/gfp. <<
165 */ <<
166 static bool dma_direct_use_pool(struct device <<
167 { <<
168 return !gfpflags_allow_blocking(gfp) & <<
169 } <<
170 <<
171 static void *dma_direct_alloc_from_pool(struct <<
172 dma_addr_t *dma_handle, gfp_t <<
173 { <<
174 struct page *page; <<
175 u64 phys_limit; <<
176 void *ret; <<
177 <<
178 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DM <<
179 return NULL; <<
180 <<
181 gfp |= dma_direct_optimal_gfp_mask(dev <<
182 page = dma_alloc_from_pool(dev, size, <<
183 if (!page) <<
184 return NULL; <<
185 *dma_handle = phys_to_dma_direct(dev, <<
186 return ret; <<
187 } <<
188 <<
189 static void *dma_direct_alloc_no_mapping(struc <<
190 dma_addr_t *dma_handle, gfp_t <<
191 { <<
192 struct page *page; <<
193 <<
194 page = __dma_direct_alloc_pages(dev, s <<
195 if (!page) <<
196 return NULL; <<
197 <<
198 /* remove any dirty cache lines on the <<
199 if (!PageHighMem(page)) <<
200 arch_dma_prep_coherent(page, s <<
201 <<
202 /* return the page pointer as the opaq <<
203 *dma_handle = phys_to_dma_direct(dev, <<
204 return page; <<
205 } <<
206 <<
207 void *dma_direct_alloc(struct device *dev, siz <<
208 dma_addr_t *dma_handle, gfp_t 123 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
209 { 124 {
210 bool remap = false, set_uncached = fal <<
211 struct page *page; 125 struct page *page;
212 void *ret; 126 void *ret;
213 127
214 size = PAGE_ALIGN(size); !! 128 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
215 if (attrs & DMA_ATTR_NO_WARN) !! 129 dma_alloc_need_uncached(dev, attrs) &&
216 gfp |= __GFP_NOWARN; !! 130 !gfpflags_allow_blocking(gfp)) {
217 !! 131 ret = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp);
218 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN !! 132 if (!ret)
219 !force_dma_unencrypted(dev) && !is <<
220 return dma_direct_alloc_no_map <<
221 <<
222 if (!dev_is_dma_coherent(dev)) { <<
223 if (IS_ENABLED(CONFIG_ARCH_HAS <<
224 !is_swiotlb_for_alloc(dev) <<
225 return arch_dma_alloc( <<
226 <<
227 <<
228 /* <<
229 * If there is a global pool, <<
230 * non-coherent devices. <<
231 */ <<
232 if (IS_ENABLED(CONFIG_DMA_GLOB <<
233 return dma_alloc_from_ <<
234 dma_ha <<
235 <<
236 /* <<
237 * Otherwise we require the ar <<
238 * mark arbitrary parts of the <<
239 * or remapped it uncached. <<
240 */ <<
241 set_uncached = IS_ENABLED(CONF <<
242 remap = IS_ENABLED(CONFIG_DMA_ <<
243 if (!set_uncached && !remap) { <<
244 pr_warn_once("coherent <<
245 return NULL; 133 return NULL;
246 } !! 134 goto done;
247 } 135 }
248 136
249 /* !! 137 page = __dma_direct_alloc_pages(dev, size, gfp, attrs);
250 * Remapping or decrypting memory may <<
251 * the atomic pools instead if we aren <<
252 */ <<
253 if ((remap || force_dma_unencrypted(de <<
254 dma_direct_use_pool(dev, gfp)) <<
255 return dma_direct_alloc_from_p <<
256 <<
257 /* we always manually zero the memory <<
258 page = __dma_direct_alloc_pages(dev, s <<
259 if (!page) 138 if (!page)
260 return NULL; 139 return NULL;
261 140
262 /* !! 141 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
263 * dma_alloc_contiguous can return hig !! 142 !force_dma_unencrypted(dev)) {
264 * combination the cma= arguments and !! 143 /* remove any dirty cache lines on the kernel alias */
265 * remapped to return a kernel virtual !! 144 if (!PageHighMem(page))
266 */ !! 145 arch_dma_prep_coherent(page, size);
267 if (PageHighMem(page)) { !! 146 /* return the page pointer as the opaque cookie */
268 remap = true; !! 147 ret = page;
269 set_uncached = false; !! 148 goto done;
270 } 149 }
271 150
272 if (remap) { !! 151 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
273 pgprot_t prot = dma_pgprot(dev !! 152 dma_alloc_need_uncached(dev, attrs)) ||
274 !! 153 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
275 if (force_dma_unencrypted(dev) <<
276 prot = pgprot_decrypte <<
277 <<
278 /* remove any dirty cache line 154 /* remove any dirty cache lines on the kernel alias */
279 arch_dma_prep_coherent(page, s !! 155 arch_dma_prep_coherent(page, PAGE_ALIGN(size));
280 156
281 /* create a coherent mapping * 157 /* create a coherent mapping */
282 ret = dma_common_contiguous_re !! 158 ret = dma_common_contiguous_remap(page, PAGE_ALIGN(size),
>> 159 dma_pgprot(dev, PAGE_KERNEL, attrs),
283 __builtin_retu 160 __builtin_return_address(0));
284 if (!ret) !! 161 if (!ret) {
285 goto out_free_pages; !! 162 dma_free_contiguous(dev, page, size);
286 } else { !! 163 return ret;
287 ret = page_address(page); !! 164 }
288 if (dma_set_decrypted(dev, ret !! 165
289 goto out_leak_pages; !! 166 memset(ret, 0, size);
>> 167 goto done;
>> 168 }
>> 169
>> 170 if (PageHighMem(page)) {
>> 171 /*
>> 172 * Depending on the cma= arguments and per-arch setup
>> 173 * dma_alloc_contiguous could return highmem pages.
>> 174 * Without remapping there is no way to return them here,
>> 175 * so log an error and fail.
>> 176 */
>> 177 dev_info(dev, "Rejecting highmem page from CMA.\n");
>> 178 dma_free_contiguous(dev, page, size);
>> 179 return NULL;
290 } 180 }
291 181
>> 182 ret = page_address(page);
>> 183 if (force_dma_unencrypted(dev))
>> 184 set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
>> 185
292 memset(ret, 0, size); 186 memset(ret, 0, size);
293 187
294 if (set_uncached) { !! 188 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
>> 189 dma_alloc_need_uncached(dev, attrs)) {
295 arch_dma_prep_coherent(page, s 190 arch_dma_prep_coherent(page, size);
296 ret = arch_dma_set_uncached(re !! 191 ret = uncached_kernel_address(ret);
297 if (IS_ERR(ret)) <<
298 goto out_encrypt_pages <<
299 } 192 }
300 !! 193 done:
301 *dma_handle = phys_to_dma_direct(dev, !! 194 if (force_dma_unencrypted(dev))
>> 195 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
>> 196 else
>> 197 *dma_handle = phys_to_dma(dev, page_to_phys(page));
302 return ret; 198 return ret;
303 <<
304 out_encrypt_pages: <<
305 if (dma_set_encrypted(dev, page_addres <<
306 return NULL; <<
307 out_free_pages: <<
308 __dma_direct_free_pages(dev, page, siz <<
309 return NULL; <<
310 out_leak_pages: <<
311 return NULL; <<
312 } 199 }
313 200
314 void dma_direct_free(struct device *dev, size_ !! 201 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
315 void *cpu_addr, dma_addr_t dma !! 202 dma_addr_t dma_addr, unsigned long attrs)
316 { 203 {
317 unsigned int page_order = get_order(si 204 unsigned int page_order = get_order(size);
318 205
319 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN 206 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
320 !force_dma_unencrypted(dev) && !is !! 207 !force_dma_unencrypted(dev)) {
321 /* cpu_addr is a struct page c 208 /* cpu_addr is a struct page cookie, not a kernel address */
322 dma_free_contiguous(dev, cpu_a 209 dma_free_contiguous(dev, cpu_addr, size);
323 return; 210 return;
324 } 211 }
325 212
326 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALL !! 213 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
327 !dev_is_dma_coherent(dev) && !! 214 dma_free_from_pool(cpu_addr, PAGE_ALIGN(size)))
328 !is_swiotlb_for_alloc(dev)) { <<
329 arch_dma_free(dev, size, cpu_a <<
330 return; 215 return;
331 } <<
332 216
333 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) !! 217 if (force_dma_unencrypted(dev))
334 !dev_is_dma_coherent(dev)) { !! 218 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
335 if (!dma_release_from_global_c <<
336 WARN_ON_ONCE(1); <<
337 return; <<
338 } <<
339 <<
340 /* If cpu_addr is not from an atomic p <<
341 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO <<
342 dma_free_from_pool(dev, cpu_addr, <<
343 return; <<
344 219
345 if (is_vmalloc_addr(cpu_addr)) { !! 220 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
346 vunmap(cpu_addr); 221 vunmap(cpu_addr);
347 } else { <<
348 if (IS_ENABLED(CONFIG_ARCH_HAS <<
349 arch_dma_clear_uncache <<
350 if (dma_set_encrypted(dev, cpu <<
351 return; <<
352 } <<
353 222
354 __dma_direct_free_pages(dev, dma_direc !! 223 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
355 } 224 }
356 225
357 struct page *dma_direct_alloc_pages(struct dev !! 226 void *dma_direct_alloc(struct device *dev, size_t size,
358 dma_addr_t *dma_handle, enum d !! 227 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
359 { 228 {
360 struct page *page; !! 229 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
361 void *ret; !! 230 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
362 !! 231 dma_alloc_need_uncached(dev, attrs))
363 if (force_dma_unencrypted(dev) && dma_ !! 232 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
364 return dma_direct_alloc_from_p !! 233 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
365 !! 234 }
366 page = __dma_direct_alloc_pages(dev, s <<
367 if (!page) <<
368 return NULL; <<
369 235
370 ret = page_address(page); !! 236 void dma_direct_free(struct device *dev, size_t size,
371 if (dma_set_decrypted(dev, ret, size)) !! 237 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
372 goto out_leak_pages; !! 238 {
373 memset(ret, 0, size); !! 239 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
374 *dma_handle = phys_to_dma_direct(dev, !! 240 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
375 return page; !! 241 dma_alloc_need_uncached(dev, attrs))
376 out_leak_pages: !! 242 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
377 return NULL; !! 243 else
>> 244 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
378 } 245 }
379 246
380 void dma_direct_free_pages(struct device *dev, !! 247 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
381 struct page *page, dma_addr_t !! 248 defined(CONFIG_SWIOTLB)
382 enum dma_data_direction dir) !! 249 void dma_direct_sync_single_for_device(struct device *dev,
>> 250 dma_addr_t addr, size_t size, enum dma_data_direction dir)
383 { 251 {
384 void *vaddr = page_address(page); !! 252 phys_addr_t paddr = dma_to_phys(dev, addr);
385 253
386 /* If cpu_addr is not from an atomic p !! 254 if (unlikely(is_swiotlb_buffer(paddr)))
387 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO !! 255 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
388 dma_free_from_pool(dev, vaddr, siz <<
389 return; <<
390 256
391 if (dma_set_encrypted(dev, vaddr, size !! 257 if (!dev_is_dma_coherent(dev))
392 return; !! 258 arch_sync_dma_for_device(paddr, size, dir);
393 __dma_direct_free_pages(dev, page, siz <<
394 } 259 }
>> 260 EXPORT_SYMBOL(dma_direct_sync_single_for_device);
395 261
396 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVIC <<
397 defined(CONFIG_SWIOTLB) <<
398 void dma_direct_sync_sg_for_device(struct devi 262 void dma_direct_sync_sg_for_device(struct device *dev,
399 struct scatterlist *sgl, int n 263 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
400 { 264 {
401 struct scatterlist *sg; 265 struct scatterlist *sg;
402 int i; 266 int i;
403 267
404 for_each_sg(sgl, sg, nents, i) { 268 for_each_sg(sgl, sg, nents, i) {
405 phys_addr_t paddr = dma_to_phy 269 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
406 270
407 swiotlb_sync_single_for_device !! 271 if (unlikely(is_swiotlb_buffer(paddr)))
>> 272 swiotlb_tbl_sync_single(dev, paddr, sg->length,
>> 273 dir, SYNC_FOR_DEVICE);
408 274
409 if (!dev_is_dma_coherent(dev)) 275 if (!dev_is_dma_coherent(dev))
410 arch_sync_dma_for_devi 276 arch_sync_dma_for_device(paddr, sg->length,
411 dir); 277 dir);
412 } 278 }
413 } 279 }
>> 280 EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
414 #endif 281 #endif
415 282
416 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) 283 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
417 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_A 284 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
418 defined(CONFIG_SWIOTLB) 285 defined(CONFIG_SWIOTLB)
>> 286 void dma_direct_sync_single_for_cpu(struct device *dev,
>> 287 dma_addr_t addr, size_t size, enum dma_data_direction dir)
>> 288 {
>> 289 phys_addr_t paddr = dma_to_phys(dev, addr);
>> 290
>> 291 if (!dev_is_dma_coherent(dev)) {
>> 292 arch_sync_dma_for_cpu(paddr, size, dir);
>> 293 arch_sync_dma_for_cpu_all();
>> 294 }
>> 295
>> 296 if (unlikely(is_swiotlb_buffer(paddr)))
>> 297 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
>> 298 }
>> 299 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
>> 300
419 void dma_direct_sync_sg_for_cpu(struct device 301 void dma_direct_sync_sg_for_cpu(struct device *dev,
420 struct scatterlist *sgl, int n 302 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
421 { 303 {
422 struct scatterlist *sg; 304 struct scatterlist *sg;
423 int i; 305 int i;
424 306
425 for_each_sg(sgl, sg, nents, i) { 307 for_each_sg(sgl, sg, nents, i) {
426 phys_addr_t paddr = dma_to_phy 308 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
427 309
428 if (!dev_is_dma_coherent(dev)) 310 if (!dev_is_dma_coherent(dev))
429 arch_sync_dma_for_cpu( 311 arch_sync_dma_for_cpu(paddr, sg->length, dir);
430 312
431 swiotlb_sync_single_for_cpu(de !! 313 if (unlikely(is_swiotlb_buffer(paddr)))
432 !! 314 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
433 if (dir == DMA_FROM_DEVICE) !! 315 SYNC_FOR_CPU);
434 arch_dma_mark_clean(pa <<
435 } 316 }
436 317
437 if (!dev_is_dma_coherent(dev)) 318 if (!dev_is_dma_coherent(dev))
438 arch_sync_dma_for_cpu_all(); 319 arch_sync_dma_for_cpu_all();
439 } 320 }
>> 321 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
>> 322
>> 323 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
>> 324 size_t size, enum dma_data_direction dir, unsigned long attrs)
>> 325 {
>> 326 phys_addr_t phys = dma_to_phys(dev, addr);
>> 327
>> 328 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
>> 329 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
>> 330
>> 331 if (unlikely(is_swiotlb_buffer(phys)))
>> 332 swiotlb_tbl_unmap_single(dev, phys, size, size, dir, attrs);
>> 333 }
>> 334 EXPORT_SYMBOL(dma_direct_unmap_page);
440 335
441 /* <<
442 * Unmaps segments, except for ones marked as <<
443 * require any further action as they contain <<
444 */ <<
445 void dma_direct_unmap_sg(struct device *dev, s 336 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
446 int nents, enum dma_data_direc 337 int nents, enum dma_data_direction dir, unsigned long attrs)
447 { 338 {
448 struct scatterlist *sg; 339 struct scatterlist *sg;
449 int i; 340 int i;
450 341
451 for_each_sg(sgl, sg, nents, i) { !! 342 for_each_sg(sgl, sg, nents, i)
452 if (sg_dma_is_bus_address(sg)) !! 343 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
453 sg_dma_unmark_bus_addr !! 344 attrs);
454 else <<
455 dma_direct_unmap_page( <<
456 <<
457 } <<
458 } 345 }
>> 346 EXPORT_SYMBOL(dma_direct_unmap_sg);
459 #endif 347 #endif
460 348
>> 349 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
>> 350 unsigned long offset, size_t size, enum dma_data_direction dir,
>> 351 unsigned long attrs)
>> 352 {
>> 353 phys_addr_t phys = page_to_phys(page) + offset;
>> 354 dma_addr_t dma_addr = phys_to_dma(dev, phys);
>> 355
>> 356 if (unlikely(swiotlb_force == SWIOTLB_FORCE))
>> 357 return swiotlb_map(dev, phys, size, dir, attrs);
>> 358
>> 359 if (unlikely(!dma_capable(dev, dma_addr, size, true))) {
>> 360 if (swiotlb_force != SWIOTLB_NO_FORCE)
>> 361 return swiotlb_map(dev, phys, size, dir, attrs);
>> 362
>> 363 dev_WARN_ONCE(dev, 1,
>> 364 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
>> 365 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
>> 366 return DMA_MAPPING_ERROR;
>> 367 }
>> 368
>> 369 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
>> 370 arch_sync_dma_for_device(phys, size, dir);
>> 371 return dma_addr;
>> 372 }
>> 373 EXPORT_SYMBOL(dma_direct_map_page);
>> 374
461 int dma_direct_map_sg(struct device *dev, stru 375 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
462 enum dma_data_direction dir, u 376 enum dma_data_direction dir, unsigned long attrs)
463 { 377 {
464 struct pci_p2pdma_map_state p2pdma_sta !! 378 int i;
465 enum pci_p2pdma_map_type map; <<
466 struct scatterlist *sg; 379 struct scatterlist *sg;
467 int i, ret; <<
468 380
469 for_each_sg(sgl, sg, nents, i) { 381 for_each_sg(sgl, sg, nents, i) {
470 if (is_pci_p2pdma_page(sg_page <<
471 map = pci_p2pdma_map_s <<
472 switch (map) { <<
473 case PCI_P2PDMA_MAP_BU <<
474 continue; <<
475 case PCI_P2PDMA_MAP_TH <<
476 /* <<
477 * Any P2P map <<
478 * host bridge <<
479 * address and <<
480 * done with d <<
481 */ <<
482 break; <<
483 default: <<
484 ret = -EREMOTE <<
485 goto out_unmap <<
486 } <<
487 } <<
488 <<
489 sg->dma_address = dma_direct_m 382 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
490 sg->offset, sg 383 sg->offset, sg->length, dir, attrs);
491 if (sg->dma_address == DMA_MAP !! 384 if (sg->dma_address == DMA_MAPPING_ERROR)
492 ret = -EIO; <<
493 goto out_unmap; 385 goto out_unmap;
494 } <<
495 sg_dma_len(sg) = sg->length; 386 sg_dma_len(sg) = sg->length;
496 } 387 }
497 388
498 return nents; 389 return nents;
499 390
500 out_unmap: 391 out_unmap:
501 dma_direct_unmap_sg(dev, sgl, i, dir, 392 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
502 return ret; !! 393 return 0;
503 } 394 }
>> 395 EXPORT_SYMBOL(dma_direct_map_sg);
504 396
505 dma_addr_t dma_direct_map_resource(struct devi 397 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
506 size_t size, enum dma_data_dir 398 size_t size, enum dma_data_direction dir, unsigned long attrs)
507 { 399 {
508 dma_addr_t dma_addr = paddr; 400 dma_addr_t dma_addr = paddr;
509 401
510 if (unlikely(!dma_capable(dev, dma_add 402 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
511 dev_err_once(dev, 403 dev_err_once(dev,
512 "DMA addr %pad+%z 404 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
513 &dma_addr, size, 405 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
514 WARN_ON_ONCE(1); 406 WARN_ON_ONCE(1);
515 return DMA_MAPPING_ERROR; 407 return DMA_MAPPING_ERROR;
516 } 408 }
517 409
518 return dma_addr; 410 return dma_addr;
519 } 411 }
>> 412 EXPORT_SYMBOL(dma_direct_map_resource);
520 413
521 int dma_direct_get_sgtable(struct device *dev, 414 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
522 void *cpu_addr, dma_addr_t dma 415 void *cpu_addr, dma_addr_t dma_addr, size_t size,
523 unsigned long attrs) 416 unsigned long attrs)
524 { 417 {
525 struct page *page = dma_direct_to_page 418 struct page *page = dma_direct_to_page(dev, dma_addr);
526 int ret; 419 int ret;
527 420
528 ret = sg_alloc_table(sgt, 1, GFP_KERNE 421 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
529 if (!ret) 422 if (!ret)
530 sg_set_page(sgt->sgl, page, PA 423 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
531 return ret; 424 return ret;
532 } 425 }
533 426
>> 427 #ifdef CONFIG_MMU
534 bool dma_direct_can_mmap(struct device *dev) 428 bool dma_direct_can_mmap(struct device *dev)
535 { 429 {
536 return dev_is_dma_coherent(dev) || 430 return dev_is_dma_coherent(dev) ||
537 IS_ENABLED(CONFIG_DMA_NONCOHER 431 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
538 } 432 }
539 433
540 int dma_direct_mmap(struct device *dev, struct 434 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
541 void *cpu_addr, dma_addr_t dma 435 void *cpu_addr, dma_addr_t dma_addr, size_t size,
542 unsigned long attrs) 436 unsigned long attrs)
543 { 437 {
544 unsigned long user_count = vma_pages(v 438 unsigned long user_count = vma_pages(vma);
545 unsigned long count = PAGE_ALIGN(size) 439 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
546 unsigned long pfn = PHYS_PFN(dma_to_ph 440 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
547 int ret = -ENXIO; 441 int ret = -ENXIO;
548 442
549 vma->vm_page_prot = dma_pgprot(dev, vm 443 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
550 if (force_dma_unencrypted(dev)) <<
551 vma->vm_page_prot = pgprot_dec <<
552 444
553 if (dma_mmap_from_dev_coherent(dev, vm 445 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
554 return ret; 446 return ret;
555 if (dma_mmap_from_global_coherent(vma, <<
556 return ret; <<
557 447
558 if (vma->vm_pgoff >= count || user_cou 448 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
559 return -ENXIO; 449 return -ENXIO;
560 return remap_pfn_range(vma, vma->vm_st 450 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
561 user_count << PAGE_SHI 451 user_count << PAGE_SHIFT, vma->vm_page_prot);
562 } 452 }
>> 453 #else /* CONFIG_MMU */
>> 454 bool dma_direct_can_mmap(struct device *dev)
>> 455 {
>> 456 return false;
>> 457 }
>> 458
>> 459 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
>> 460 void *cpu_addr, dma_addr_t dma_addr, size_t size,
>> 461 unsigned long attrs)
>> 462 {
>> 463 return -ENXIO;
>> 464 }
>> 465 #endif /* CONFIG_MMU */
563 466
564 int dma_direct_supported(struct device *dev, u 467 int dma_direct_supported(struct device *dev, u64 mask)
565 { 468 {
566 u64 min_mask = (max_pfn - 1) << PAGE_S 469 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
567 470
568 /* 471 /*
569 * Because 32-bit DMA masks are so com 472 * Because 32-bit DMA masks are so common we expect every architecture
570 * to be able to satisfy them - either 473 * to be able to satisfy them - either by not supporting more physical
571 * memory, or by providing a ZONE_DMA3 474 * memory, or by providing a ZONE_DMA32. If neither is the case, the
572 * architecture needs to use an IOMMU 475 * architecture needs to use an IOMMU instead of the direct mapping.
573 */ 476 */
574 if (mask >= DMA_BIT_MASK(32)) 477 if (mask >= DMA_BIT_MASK(32))
575 return 1; 478 return 1;
576 479
577 /* 480 /*
578 * This check needs to be against the !! 481 * This check needs to be against the actual bit mask value, so
579 * phys_to_dma_unencrypted() here so t !! 482 * use __phys_to_dma() here so that the SME encryption mask isn't
580 * part of the check. 483 * part of the check.
581 */ 484 */
582 if (IS_ENABLED(CONFIG_ZONE_DMA)) 485 if (IS_ENABLED(CONFIG_ZONE_DMA))
583 min_mask = min_t(u64, min_mask 486 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
584 return mask >= phys_to_dma_unencrypted !! 487 return mask >= __phys_to_dma(dev, min_mask);
585 } <<
586 <<
587 /* <<
588 * To check whether all ram resource ranges ar <<
589 * Returns 0 when further check is needed <<
590 * Returns 1 if there is some RAM range can't <<
591 */ <<
592 static int check_ram_in_range_map(unsigned lon <<
593 unsigned lon <<
594 { <<
595 unsigned long end_pfn = start_pfn + nr <<
596 const struct bus_dma_region *bdr = NUL <<
597 const struct bus_dma_region *m; <<
598 struct device *dev = data; <<
599 <<
600 while (start_pfn < end_pfn) { <<
601 for (m = dev->dma_range_map; P <<
602 unsigned long cpu_star <<
603 <<
604 if (start_pfn >= cpu_s <<
605 start_pfn - cpu_st <<
606 bdr = m; <<
607 break; <<
608 } <<
609 } <<
610 if (!bdr) <<
611 return 1; <<
612 <<
613 start_pfn = PFN_DOWN(bdr->cpu_ <<
614 } <<
615 <<
616 return 0; <<
617 } <<
618 <<
619 bool dma_direct_all_ram_mapped(struct device * <<
620 { <<
621 if (!dev->dma_range_map) <<
622 return true; <<
623 return !walk_system_ram_range(0, PFN_D <<
624 check_ra <<
625 } 488 }
626 489
627 size_t dma_direct_max_mapping_size(struct devi 490 size_t dma_direct_max_mapping_size(struct device *dev)
628 { 491 {
629 /* If SWIOTLB is active, use its maxim 492 /* If SWIOTLB is active, use its maximum mapping size */
630 if (is_swiotlb_active(dev) && !! 493 if (is_swiotlb_active() &&
631 (dma_addressing_limited(dev) || is !! 494 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
632 return swiotlb_max_mapping_siz 495 return swiotlb_max_mapping_size(dev);
633 return SIZE_MAX; 496 return SIZE_MAX;
634 } <<
635 <<
636 bool dma_direct_need_sync(struct device *dev, <<
637 { <<
638 return !dev_is_dma_coherent(dev) || <<
639 swiotlb_find_pool(dev, dma_to_p <<
640 } <<
641 <<
642 /** <<
643 * dma_direct_set_offset - Assign scalar offse <<
644 * @dev: device pointer; needed to "own <<
645 * @cpu_start: beginning of memory region cov <<
646 * @dma_start: beginning of DMA/PCI region co <<
647 * @size: size of the region. <<
648 * <<
649 * This is for the simple case of a uniform of <<
650 * be discovered by "dma-ranges". <<
651 * <<
652 * It returns -ENOMEM if out of memory, -EINVA <<
653 * already exists, 0 otherwise. <<
654 * <<
655 * Note: any call to this from a driver is a b <<
656 * to be described by the device tree or other <<
657 */ <<
658 int dma_direct_set_offset(struct device *dev, <<
659 dma_addr_t dma_start, <<
660 { <<
661 struct bus_dma_region *map; <<
662 u64 offset = (u64)cpu_start - (u64)dma <<
663 <<
664 if (dev->dma_range_map) { <<
665 dev_err(dev, "attempt to add D <<
666 return -EINVAL; <<
667 } <<
668 <<
669 if (!offset) <<
670 return 0; <<
671 <<
672 map = kcalloc(2, sizeof(*map), GFP_KER <<
673 if (!map) <<
674 return -ENOMEM; <<
675 map[0].cpu_start = cpu_start; <<
676 map[0].dma_start = dma_start; <<
677 map[0].size = size; <<
678 dev->dma_range_map = map; <<
679 return 0; <<
680 } 497 }
681 498
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