1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2018-2020 Christoph Hellwig. !! 3 * Copyright (C) 2018 Christoph Hellwig.
4 * 4 *
5 * DMA operations that map physical memory dir 5 * DMA operations that map physical memory directly without using an IOMMU.
6 */ 6 */
7 #include <linux/memblock.h> /* for max_pfn */ 7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h> 8 #include <linux/export.h>
9 #include <linux/mm.h> 9 #include <linux/mm.h>
10 #include <linux/dma-map-ops.h> !! 10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h> 11 #include <linux/scatterlist.h>
>> 12 #include <linux/dma-contiguous.h>
>> 13 #include <linux/dma-noncoherent.h>
12 #include <linux/pfn.h> 14 #include <linux/pfn.h>
13 #include <linux/vmalloc.h> 15 #include <linux/vmalloc.h>
14 #include <linux/set_memory.h> 16 #include <linux/set_memory.h>
15 #include <linux/slab.h> !! 17 #include <linux/swiotlb.h>
16 #include "direct.h" <<
17 18
18 /* 19 /*
19 * Most architectures use ZONE_DMA for the fir !! 20 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it
20 * it for entirely different regions. In that 21 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct 22 * override the variable below for dma-direct to work properly.
22 */ 23 */
23 unsigned int zone_dma_bits __ro_after_init = 2 24 unsigned int zone_dma_bits __ro_after_init = 24;
24 25
25 static inline dma_addr_t phys_to_dma_direct(st 26 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
26 phys_addr_t phys) 27 phys_addr_t phys)
27 { 28 {
28 if (force_dma_unencrypted(dev)) 29 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted !! 30 return __phys_to_dma(dev, phys);
30 return phys_to_dma(dev, phys); 31 return phys_to_dma(dev, phys);
31 } 32 }
32 33
33 static inline struct page *dma_direct_to_page( 34 static inline struct page *dma_direct_to_page(struct device *dev,
34 dma_addr_t dma_addr) 35 dma_addr_t dma_addr)
35 { 36 {
36 return pfn_to_page(PHYS_PFN(dma_to_phy 37 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
37 } 38 }
38 39
39 u64 dma_direct_get_required_mask(struct device 40 u64 dma_direct_get_required_mask(struct device *dev)
40 { 41 {
41 phys_addr_t phys = (phys_addr_t)(max_p 42 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, 43 u64 max_dma = phys_to_dma_direct(dev, phys);
43 44
44 return (1ULL << (fls64(max_dma) - 1)) 45 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
45 } 46 }
46 47
47 static gfp_t dma_direct_optimal_gfp_mask(struc !! 48 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
>> 49 u64 *phys_limit)
48 { 50 {
49 u64 dma_limit = min_not_zero( !! 51 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
50 dev->coherent_dma_mask, !! 52
51 dev->bus_dma_limit); !! 53 if (force_dma_unencrypted(dev))
>> 54 *phys_limit = __dma_to_phys(dev, dma_limit);
>> 55 else
>> 56 *phys_limit = dma_to_phys(dev, dma_limit);
52 57
53 /* 58 /*
54 * Optimistically try the zone that th 59 * Optimistically try the zone that the physical address mask falls
55 * into first. If that returns memory 60 * into first. If that returns memory that isn't actually addressable
56 * we will fallback to the next lower 61 * we will fallback to the next lower zone and try again.
57 * 62 *
58 * Note that GFP_DMA32 and GFP_DMA are 63 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
59 * zones. 64 * zones.
60 */ 65 */
61 *phys_limit = dma_to_phys(dev, dma_lim <<
62 if (*phys_limit <= DMA_BIT_MASK(zone_d 66 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
63 return GFP_DMA; 67 return GFP_DMA;
64 if (*phys_limit <= DMA_BIT_MASK(32)) 68 if (*phys_limit <= DMA_BIT_MASK(32))
65 return GFP_DMA32; 69 return GFP_DMA32;
66 return 0; 70 return 0;
67 } 71 }
68 72
69 bool dma_coherent_ok(struct device *dev, phys_ !! 73 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
70 { <<
71 dma_addr_t dma_addr = phys_to_dma_dire <<
72 <<
73 if (dma_addr == DMA_MAPPING_ERROR) <<
74 return false; <<
75 return dma_addr + size - 1 <= <<
76 min_not_zero(dev->coherent_dma <<
77 } <<
78 <<
79 static int dma_set_decrypted(struct device *de <<
80 { 74 {
81 if (!force_dma_unencrypted(dev)) !! 75 return phys_to_dma_direct(dev, phys) + size - 1 <=
82 return 0; !! 76 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
83 return set_memory_decrypted((unsigned <<
84 } 77 }
85 78
86 static int dma_set_encrypted(struct device *de !! 79 /*
87 { !! 80 * Decrypting memory is allowed to block, so if this device requires
88 int ret; !! 81 * unencrypted memory it must come from atomic pools.
89 !! 82 */
90 if (!force_dma_unencrypted(dev)) !! 83 static inline bool dma_should_alloc_from_pool(struct device *dev, gfp_t gfp,
91 return 0; !! 84 unsigned long attrs)
92 ret = set_memory_encrypted((unsigned l <<
93 if (ret) <<
94 pr_warn_ratelimited("leaking D <<
95 return ret; <<
96 } <<
97 <<
98 static void __dma_direct_free_pages(struct dev <<
99 size_t siz <<
100 { 85 {
101 if (swiotlb_free(dev, page, size)) !! 86 if (!IS_ENABLED(CONFIG_DMA_COHERENT_POOL))
102 return; !! 87 return false;
103 dma_free_contiguous(dev, page, size); !! 88 if (gfpflags_allow_blocking(gfp))
>> 89 return false;
>> 90 if (force_dma_unencrypted(dev))
>> 91 return true;
>> 92 if (!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP))
>> 93 return false;
>> 94 if (dma_alloc_need_uncached(dev, attrs))
>> 95 return true;
>> 96 return false;
104 } 97 }
105 98
106 static struct page *dma_direct_alloc_swiotlb(s !! 99 static inline bool dma_should_free_from_pool(struct device *dev,
>> 100 unsigned long attrs)
107 { 101 {
108 struct page *page = swiotlb_alloc(dev, !! 102 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL))
109 !! 103 return true;
110 if (page && !dma_coherent_ok(dev, page !! 104 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
111 swiotlb_free(dev, page, size); !! 105 !force_dma_unencrypted(dev))
112 return NULL; !! 106 return false;
113 } !! 107 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP))
114 !! 108 return true;
115 return page; !! 109 return false;
116 } 110 }
117 111
118 static struct page *__dma_direct_alloc_pages(s 112 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
119 gfp_t gfp, bool allow_highmem) !! 113 gfp_t gfp, unsigned long attrs)
120 { 114 {
121 int node = dev_to_node(dev); 115 int node = dev_to_node(dev);
122 struct page *page = NULL; 116 struct page *page = NULL;
123 u64 phys_limit; 117 u64 phys_limit;
124 118
125 WARN_ON_ONCE(!PAGE_ALIGNED(size)); 119 WARN_ON_ONCE(!PAGE_ALIGNED(size));
126 120
127 if (is_swiotlb_for_alloc(dev)) !! 121 if (attrs & DMA_ATTR_NO_WARN)
128 return dma_direct_alloc_swiotl !! 122 gfp |= __GFP_NOWARN;
129 123
130 gfp |= dma_direct_optimal_gfp_mask(dev !! 124 /* we always manually zero the memory once we are done: */
>> 125 gfp &= ~__GFP_ZERO;
>> 126 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
>> 127 &phys_limit);
131 page = dma_alloc_contiguous(dev, size, 128 page = dma_alloc_contiguous(dev, size, gfp);
132 if (page) { !! 129 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
133 if (!dma_coherent_ok(dev, page !! 130 dma_free_contiguous(dev, page, size);
134 (!allow_highmem && PageHig !! 131 page = NULL;
135 dma_free_contiguous(de <<
136 page = NULL; <<
137 } <<
138 } 132 }
139 again: 133 again:
140 if (!page) 134 if (!page)
141 page = alloc_pages_node(node, 135 page = alloc_pages_node(node, gfp, get_order(size));
142 if (page && !dma_coherent_ok(dev, page 136 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
143 dma_free_contiguous(dev, page, 137 dma_free_contiguous(dev, page, size);
144 page = NULL; 138 page = NULL;
145 139
146 if (IS_ENABLED(CONFIG_ZONE_DMA 140 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
147 phys_limit < DMA_BIT_MASK( 141 phys_limit < DMA_BIT_MASK(64) &&
148 !(gfp & (GFP_DMA32 | GFP_D 142 !(gfp & (GFP_DMA32 | GFP_DMA))) {
149 gfp |= GFP_DMA32; 143 gfp |= GFP_DMA32;
150 goto again; 144 goto again;
151 } 145 }
152 146
153 if (IS_ENABLED(CONFIG_ZONE_DMA 147 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
154 gfp = (gfp & ~GFP_DMA3 148 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
155 goto again; 149 goto again;
156 } 150 }
157 } 151 }
158 152
159 return page; 153 return page;
160 } 154 }
161 155
162 /* !! 156 void *dma_direct_alloc_pages(struct device *dev, size_t size,
163 * Check if a potentially blocking operations <<
164 * pools for the given device/gfp. <<
165 */ <<
166 static bool dma_direct_use_pool(struct device <<
167 { <<
168 return !gfpflags_allow_blocking(gfp) & <<
169 } <<
170 <<
171 static void *dma_direct_alloc_from_pool(struct <<
172 dma_addr_t *dma_handle, gfp_t <<
173 { <<
174 struct page *page; <<
175 u64 phys_limit; <<
176 void *ret; <<
177 <<
178 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DM <<
179 return NULL; <<
180 <<
181 gfp |= dma_direct_optimal_gfp_mask(dev <<
182 page = dma_alloc_from_pool(dev, size, <<
183 if (!page) <<
184 return NULL; <<
185 *dma_handle = phys_to_dma_direct(dev, <<
186 return ret; <<
187 } <<
188 <<
189 static void *dma_direct_alloc_no_mapping(struc <<
190 dma_addr_t *dma_handle, gfp_t <<
191 { <<
192 struct page *page; <<
193 <<
194 page = __dma_direct_alloc_pages(dev, s <<
195 if (!page) <<
196 return NULL; <<
197 <<
198 /* remove any dirty cache lines on the <<
199 if (!PageHighMem(page)) <<
200 arch_dma_prep_coherent(page, s <<
201 <<
202 /* return the page pointer as the opaq <<
203 *dma_handle = phys_to_dma_direct(dev, <<
204 return page; <<
205 } <<
206 <<
207 void *dma_direct_alloc(struct device *dev, siz <<
208 dma_addr_t *dma_handle, gfp_t 157 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
209 { 158 {
210 bool remap = false, set_uncached = fal <<
211 struct page *page; 159 struct page *page;
212 void *ret; 160 void *ret;
>> 161 int err;
213 162
214 size = PAGE_ALIGN(size); 163 size = PAGE_ALIGN(size);
215 if (attrs & DMA_ATTR_NO_WARN) <<
216 gfp |= __GFP_NOWARN; <<
217 164
218 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN !! 165 if (dma_should_alloc_from_pool(dev, gfp, attrs)) {
219 !force_dma_unencrypted(dev) && !is !! 166 u64 phys_mask;
220 return dma_direct_alloc_no_map <<
221 167
222 if (!dev_is_dma_coherent(dev)) { !! 168 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
223 if (IS_ENABLED(CONFIG_ARCH_HAS !! 169 &phys_mask);
224 !is_swiotlb_for_alloc(dev) !! 170 page = dma_alloc_from_pool(dev, size, &ret, gfp,
225 return arch_dma_alloc( !! 171 dma_coherent_ok);
226 !! 172 if (!page)
227 <<
228 /* <<
229 * If there is a global pool, <<
230 * non-coherent devices. <<
231 */ <<
232 if (IS_ENABLED(CONFIG_DMA_GLOB <<
233 return dma_alloc_from_ <<
234 dma_ha <<
235 <<
236 /* <<
237 * Otherwise we require the ar <<
238 * mark arbitrary parts of the <<
239 * or remapped it uncached. <<
240 */ <<
241 set_uncached = IS_ENABLED(CONF <<
242 remap = IS_ENABLED(CONFIG_DMA_ <<
243 if (!set_uncached && !remap) { <<
244 pr_warn_once("coherent <<
245 return NULL; 173 return NULL;
246 } !! 174 goto done;
247 } 175 }
248 176
249 /* !! 177 page = __dma_direct_alloc_pages(dev, size, gfp, attrs);
250 * Remapping or decrypting memory may <<
251 * the atomic pools instead if we aren <<
252 */ <<
253 if ((remap || force_dma_unencrypted(de <<
254 dma_direct_use_pool(dev, gfp)) <<
255 return dma_direct_alloc_from_p <<
256 <<
257 /* we always manually zero the memory <<
258 page = __dma_direct_alloc_pages(dev, s <<
259 if (!page) 178 if (!page)
260 return NULL; 179 return NULL;
261 180
262 /* !! 181 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
263 * dma_alloc_contiguous can return hig !! 182 !force_dma_unencrypted(dev)) {
264 * combination the cma= arguments and !! 183 /* remove any dirty cache lines on the kernel alias */
265 * remapped to return a kernel virtual !! 184 if (!PageHighMem(page))
266 */ !! 185 arch_dma_prep_coherent(page, size);
267 if (PageHighMem(page)) { !! 186 /* return the page pointer as the opaque cookie */
268 remap = true; !! 187 ret = page;
269 set_uncached = false; !! 188 goto done;
270 } 189 }
271 190
272 if (remap) { !! 191 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
273 pgprot_t prot = dma_pgprot(dev !! 192 dma_alloc_need_uncached(dev, attrs)) ||
274 !! 193 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
275 if (force_dma_unencrypted(dev) <<
276 prot = pgprot_decrypte <<
277 <<
278 /* remove any dirty cache line 194 /* remove any dirty cache lines on the kernel alias */
279 arch_dma_prep_coherent(page, s 195 arch_dma_prep_coherent(page, size);
280 196
281 /* create a coherent mapping * 197 /* create a coherent mapping */
282 ret = dma_common_contiguous_re !! 198 ret = dma_common_contiguous_remap(page, size,
>> 199 dma_pgprot(dev, PAGE_KERNEL, attrs),
283 __builtin_retu 200 __builtin_return_address(0));
284 if (!ret) 201 if (!ret)
285 goto out_free_pages; 202 goto out_free_pages;
286 } else { !! 203 if (force_dma_unencrypted(dev)) {
287 ret = page_address(page); !! 204 err = set_memory_decrypted((unsigned long)ret,
288 if (dma_set_decrypted(dev, ret !! 205 1 << get_order(size));
289 goto out_leak_pages; !! 206 if (err)
>> 207 goto out_free_pages;
>> 208 }
>> 209 memset(ret, 0, size);
>> 210 goto done;
>> 211 }
>> 212
>> 213 if (PageHighMem(page)) {
>> 214 /*
>> 215 * Depending on the cma= arguments and per-arch setup
>> 216 * dma_alloc_contiguous could return highmem pages.
>> 217 * Without remapping there is no way to return them here,
>> 218 * so log an error and fail.
>> 219 */
>> 220 dev_info(dev, "Rejecting highmem page from CMA.\n");
>> 221 goto out_free_pages;
>> 222 }
>> 223
>> 224 ret = page_address(page);
>> 225 if (force_dma_unencrypted(dev)) {
>> 226 err = set_memory_decrypted((unsigned long)ret,
>> 227 1 << get_order(size));
>> 228 if (err)
>> 229 goto out_free_pages;
290 } 230 }
291 231
292 memset(ret, 0, size); 232 memset(ret, 0, size);
293 233
294 if (set_uncached) { !! 234 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
>> 235 dma_alloc_need_uncached(dev, attrs)) {
295 arch_dma_prep_coherent(page, s 236 arch_dma_prep_coherent(page, size);
296 ret = arch_dma_set_uncached(re 237 ret = arch_dma_set_uncached(ret, size);
297 if (IS_ERR(ret)) 238 if (IS_ERR(ret))
298 goto out_encrypt_pages 239 goto out_encrypt_pages;
299 } 240 }
300 !! 241 done:
301 *dma_handle = phys_to_dma_direct(dev, !! 242 if (force_dma_unencrypted(dev))
>> 243 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
>> 244 else
>> 245 *dma_handle = phys_to_dma(dev, page_to_phys(page));
302 return ret; 246 return ret;
303 247
304 out_encrypt_pages: 248 out_encrypt_pages:
305 if (dma_set_encrypted(dev, page_addres !! 249 if (force_dma_unencrypted(dev)) {
306 return NULL; !! 250 err = set_memory_encrypted((unsigned long)page_address(page),
>> 251 1 << get_order(size));
>> 252 /* If memory cannot be re-encrypted, it must be leaked */
>> 253 if (err)
>> 254 return NULL;
>> 255 }
307 out_free_pages: 256 out_free_pages:
308 __dma_direct_free_pages(dev, page, siz !! 257 dma_free_contiguous(dev, page, size);
309 return NULL; <<
310 out_leak_pages: <<
311 return NULL; 258 return NULL;
312 } 259 }
313 260
314 void dma_direct_free(struct device *dev, size_ !! 261 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
315 void *cpu_addr, dma_addr_t dma !! 262 dma_addr_t dma_addr, unsigned long attrs)
316 { 263 {
317 unsigned int page_order = get_order(si 264 unsigned int page_order = get_order(size);
318 265
>> 266 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
>> 267 if (dma_should_free_from_pool(dev, attrs) &&
>> 268 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
>> 269 return;
>> 270
319 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPIN 271 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
320 !force_dma_unencrypted(dev) && !is !! 272 !force_dma_unencrypted(dev)) {
321 /* cpu_addr is a struct page c 273 /* cpu_addr is a struct page cookie, not a kernel address */
322 dma_free_contiguous(dev, cpu_a 274 dma_free_contiguous(dev, cpu_addr, size);
323 return; 275 return;
324 } 276 }
325 277
326 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALL !! 278 if (force_dma_unencrypted(dev))
327 !dev_is_dma_coherent(dev) && !! 279 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
328 !is_swiotlb_for_alloc(dev)) { <<
329 arch_dma_free(dev, size, cpu_a <<
330 return; <<
331 } <<
332 <<
333 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) <<
334 !dev_is_dma_coherent(dev)) { <<
335 if (!dma_release_from_global_c <<
336 WARN_ON_ONCE(1); <<
337 return; <<
338 } <<
339 <<
340 /* If cpu_addr is not from an atomic p <<
341 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO <<
342 dma_free_from_pool(dev, cpu_addr, <<
343 return; <<
344 280
345 if (is_vmalloc_addr(cpu_addr)) { !! 281 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
346 vunmap(cpu_addr); 282 vunmap(cpu_addr);
347 } else { !! 283 else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
348 if (IS_ENABLED(CONFIG_ARCH_HAS !! 284 arch_dma_clear_uncached(cpu_addr, size);
349 arch_dma_clear_uncache <<
350 if (dma_set_encrypted(dev, cpu <<
351 return; <<
352 } <<
353 285
354 __dma_direct_free_pages(dev, dma_direc !! 286 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
355 } 287 }
356 288
357 struct page *dma_direct_alloc_pages(struct dev !! 289 void *dma_direct_alloc(struct device *dev, size_t size,
358 dma_addr_t *dma_handle, enum d !! 290 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
359 { 291 {
360 struct page *page; !! 292 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
361 void *ret; !! 293 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
362 !! 294 dma_alloc_need_uncached(dev, attrs))
363 if (force_dma_unencrypted(dev) && dma_ !! 295 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
364 return dma_direct_alloc_from_p !! 296 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
365 !! 297 }
366 page = __dma_direct_alloc_pages(dev, s <<
367 if (!page) <<
368 return NULL; <<
369 298
370 ret = page_address(page); !! 299 void dma_direct_free(struct device *dev, size_t size,
371 if (dma_set_decrypted(dev, ret, size)) !! 300 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
372 goto out_leak_pages; !! 301 {
373 memset(ret, 0, size); !! 302 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
374 *dma_handle = phys_to_dma_direct(dev, !! 303 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
375 return page; !! 304 dma_alloc_need_uncached(dev, attrs))
376 out_leak_pages: !! 305 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
377 return NULL; !! 306 else
>> 307 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
378 } 308 }
379 309
380 void dma_direct_free_pages(struct device *dev, !! 310 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
381 struct page *page, dma_addr_t !! 311 defined(CONFIG_SWIOTLB)
382 enum dma_data_direction dir) !! 312 void dma_direct_sync_single_for_device(struct device *dev,
>> 313 dma_addr_t addr, size_t size, enum dma_data_direction dir)
383 { 314 {
384 void *vaddr = page_address(page); !! 315 phys_addr_t paddr = dma_to_phys(dev, addr);
385 316
386 /* If cpu_addr is not from an atomic p !! 317 if (unlikely(is_swiotlb_buffer(paddr)))
387 if (IS_ENABLED(CONFIG_DMA_COHERENT_POO !! 318 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
388 dma_free_from_pool(dev, vaddr, siz <<
389 return; <<
390 319
391 if (dma_set_encrypted(dev, vaddr, size !! 320 if (!dev_is_dma_coherent(dev))
392 return; !! 321 arch_sync_dma_for_device(paddr, size, dir);
393 __dma_direct_free_pages(dev, page, siz <<
394 } 322 }
>> 323 EXPORT_SYMBOL(dma_direct_sync_single_for_device);
395 324
396 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVIC <<
397 defined(CONFIG_SWIOTLB) <<
398 void dma_direct_sync_sg_for_device(struct devi 325 void dma_direct_sync_sg_for_device(struct device *dev,
399 struct scatterlist *sgl, int n 326 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
400 { 327 {
401 struct scatterlist *sg; 328 struct scatterlist *sg;
402 int i; 329 int i;
403 330
404 for_each_sg(sgl, sg, nents, i) { 331 for_each_sg(sgl, sg, nents, i) {
405 phys_addr_t paddr = dma_to_phy 332 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
406 333
407 swiotlb_sync_single_for_device !! 334 if (unlikely(is_swiotlb_buffer(paddr)))
>> 335 swiotlb_tbl_sync_single(dev, paddr, sg->length,
>> 336 dir, SYNC_FOR_DEVICE);
408 337
409 if (!dev_is_dma_coherent(dev)) 338 if (!dev_is_dma_coherent(dev))
410 arch_sync_dma_for_devi 339 arch_sync_dma_for_device(paddr, sg->length,
411 dir); 340 dir);
412 } 341 }
413 } 342 }
>> 343 EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
414 #endif 344 #endif
415 345
416 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) 346 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
417 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_A 347 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
418 defined(CONFIG_SWIOTLB) 348 defined(CONFIG_SWIOTLB)
>> 349 void dma_direct_sync_single_for_cpu(struct device *dev,
>> 350 dma_addr_t addr, size_t size, enum dma_data_direction dir)
>> 351 {
>> 352 phys_addr_t paddr = dma_to_phys(dev, addr);
>> 353
>> 354 if (!dev_is_dma_coherent(dev)) {
>> 355 arch_sync_dma_for_cpu(paddr, size, dir);
>> 356 arch_sync_dma_for_cpu_all();
>> 357 }
>> 358
>> 359 if (unlikely(is_swiotlb_buffer(paddr)))
>> 360 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
>> 361 }
>> 362 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
>> 363
419 void dma_direct_sync_sg_for_cpu(struct device 364 void dma_direct_sync_sg_for_cpu(struct device *dev,
420 struct scatterlist *sgl, int n 365 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
421 { 366 {
422 struct scatterlist *sg; 367 struct scatterlist *sg;
423 int i; 368 int i;
424 369
425 for_each_sg(sgl, sg, nents, i) { 370 for_each_sg(sgl, sg, nents, i) {
426 phys_addr_t paddr = dma_to_phy 371 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
427 372
428 if (!dev_is_dma_coherent(dev)) 373 if (!dev_is_dma_coherent(dev))
429 arch_sync_dma_for_cpu( 374 arch_sync_dma_for_cpu(paddr, sg->length, dir);
430 375
431 swiotlb_sync_single_for_cpu(de !! 376 if (unlikely(is_swiotlb_buffer(paddr)))
432 !! 377 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
433 if (dir == DMA_FROM_DEVICE) !! 378 SYNC_FOR_CPU);
434 arch_dma_mark_clean(pa <<
435 } 379 }
436 380
437 if (!dev_is_dma_coherent(dev)) 381 if (!dev_is_dma_coherent(dev))
438 arch_sync_dma_for_cpu_all(); 382 arch_sync_dma_for_cpu_all();
439 } 383 }
>> 384 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
>> 385
>> 386 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
>> 387 size_t size, enum dma_data_direction dir, unsigned long attrs)
>> 388 {
>> 389 phys_addr_t phys = dma_to_phys(dev, addr);
>> 390
>> 391 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
>> 392 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
>> 393
>> 394 if (unlikely(is_swiotlb_buffer(phys)))
>> 395 swiotlb_tbl_unmap_single(dev, phys, size, size, dir, attrs);
>> 396 }
>> 397 EXPORT_SYMBOL(dma_direct_unmap_page);
440 398
441 /* <<
442 * Unmaps segments, except for ones marked as <<
443 * require any further action as they contain <<
444 */ <<
445 void dma_direct_unmap_sg(struct device *dev, s 399 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
446 int nents, enum dma_data_direc 400 int nents, enum dma_data_direction dir, unsigned long attrs)
447 { 401 {
448 struct scatterlist *sg; 402 struct scatterlist *sg;
449 int i; 403 int i;
450 404
451 for_each_sg(sgl, sg, nents, i) { !! 405 for_each_sg(sgl, sg, nents, i)
452 if (sg_dma_is_bus_address(sg)) !! 406 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
453 sg_dma_unmark_bus_addr !! 407 attrs);
454 else <<
455 dma_direct_unmap_page( <<
456 <<
457 } <<
458 } 408 }
>> 409 EXPORT_SYMBOL(dma_direct_unmap_sg);
459 #endif 410 #endif
460 411
>> 412 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
>> 413 unsigned long offset, size_t size, enum dma_data_direction dir,
>> 414 unsigned long attrs)
>> 415 {
>> 416 phys_addr_t phys = page_to_phys(page) + offset;
>> 417 dma_addr_t dma_addr = phys_to_dma(dev, phys);
>> 418
>> 419 if (unlikely(swiotlb_force == SWIOTLB_FORCE))
>> 420 return swiotlb_map(dev, phys, size, dir, attrs);
>> 421
>> 422 if (unlikely(!dma_capable(dev, dma_addr, size, true))) {
>> 423 if (swiotlb_force != SWIOTLB_NO_FORCE)
>> 424 return swiotlb_map(dev, phys, size, dir, attrs);
>> 425
>> 426 dev_WARN_ONCE(dev, 1,
>> 427 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
>> 428 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
>> 429 return DMA_MAPPING_ERROR;
>> 430 }
>> 431
>> 432 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
>> 433 arch_sync_dma_for_device(phys, size, dir);
>> 434 return dma_addr;
>> 435 }
>> 436 EXPORT_SYMBOL(dma_direct_map_page);
>> 437
461 int dma_direct_map_sg(struct device *dev, stru 438 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
462 enum dma_data_direction dir, u 439 enum dma_data_direction dir, unsigned long attrs)
463 { 440 {
464 struct pci_p2pdma_map_state p2pdma_sta !! 441 int i;
465 enum pci_p2pdma_map_type map; <<
466 struct scatterlist *sg; 442 struct scatterlist *sg;
467 int i, ret; <<
468 443
469 for_each_sg(sgl, sg, nents, i) { 444 for_each_sg(sgl, sg, nents, i) {
470 if (is_pci_p2pdma_page(sg_page <<
471 map = pci_p2pdma_map_s <<
472 switch (map) { <<
473 case PCI_P2PDMA_MAP_BU <<
474 continue; <<
475 case PCI_P2PDMA_MAP_TH <<
476 /* <<
477 * Any P2P map <<
478 * host bridge <<
479 * address and <<
480 * done with d <<
481 */ <<
482 break; <<
483 default: <<
484 ret = -EREMOTE <<
485 goto out_unmap <<
486 } <<
487 } <<
488 <<
489 sg->dma_address = dma_direct_m 445 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
490 sg->offset, sg 446 sg->offset, sg->length, dir, attrs);
491 if (sg->dma_address == DMA_MAP !! 447 if (sg->dma_address == DMA_MAPPING_ERROR)
492 ret = -EIO; <<
493 goto out_unmap; 448 goto out_unmap;
494 } <<
495 sg_dma_len(sg) = sg->length; 449 sg_dma_len(sg) = sg->length;
496 } 450 }
497 451
498 return nents; 452 return nents;
499 453
500 out_unmap: 454 out_unmap:
501 dma_direct_unmap_sg(dev, sgl, i, dir, 455 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
502 return ret; !! 456 return 0;
503 } 457 }
>> 458 EXPORT_SYMBOL(dma_direct_map_sg);
504 459
505 dma_addr_t dma_direct_map_resource(struct devi 460 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
506 size_t size, enum dma_data_dir 461 size_t size, enum dma_data_direction dir, unsigned long attrs)
507 { 462 {
508 dma_addr_t dma_addr = paddr; 463 dma_addr_t dma_addr = paddr;
509 464
510 if (unlikely(!dma_capable(dev, dma_add 465 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
511 dev_err_once(dev, 466 dev_err_once(dev,
512 "DMA addr %pad+%z 467 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
513 &dma_addr, size, 468 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
514 WARN_ON_ONCE(1); 469 WARN_ON_ONCE(1);
515 return DMA_MAPPING_ERROR; 470 return DMA_MAPPING_ERROR;
516 } 471 }
517 472
518 return dma_addr; 473 return dma_addr;
519 } 474 }
>> 475 EXPORT_SYMBOL(dma_direct_map_resource);
520 476
521 int dma_direct_get_sgtable(struct device *dev, 477 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
522 void *cpu_addr, dma_addr_t dma 478 void *cpu_addr, dma_addr_t dma_addr, size_t size,
523 unsigned long attrs) 479 unsigned long attrs)
524 { 480 {
525 struct page *page = dma_direct_to_page 481 struct page *page = dma_direct_to_page(dev, dma_addr);
526 int ret; 482 int ret;
527 483
528 ret = sg_alloc_table(sgt, 1, GFP_KERNE 484 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
529 if (!ret) 485 if (!ret)
530 sg_set_page(sgt->sgl, page, PA 486 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
531 return ret; 487 return ret;
532 } 488 }
533 489
534 bool dma_direct_can_mmap(struct device *dev) 490 bool dma_direct_can_mmap(struct device *dev)
535 { 491 {
536 return dev_is_dma_coherent(dev) || 492 return dev_is_dma_coherent(dev) ||
537 IS_ENABLED(CONFIG_DMA_NONCOHER 493 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
538 } 494 }
539 495
540 int dma_direct_mmap(struct device *dev, struct 496 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
541 void *cpu_addr, dma_addr_t dma 497 void *cpu_addr, dma_addr_t dma_addr, size_t size,
542 unsigned long attrs) 498 unsigned long attrs)
543 { 499 {
544 unsigned long user_count = vma_pages(v 500 unsigned long user_count = vma_pages(vma);
545 unsigned long count = PAGE_ALIGN(size) 501 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
546 unsigned long pfn = PHYS_PFN(dma_to_ph 502 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
547 int ret = -ENXIO; 503 int ret = -ENXIO;
548 504
549 vma->vm_page_prot = dma_pgprot(dev, vm 505 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
550 if (force_dma_unencrypted(dev)) <<
551 vma->vm_page_prot = pgprot_dec <<
552 506
553 if (dma_mmap_from_dev_coherent(dev, vm 507 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
554 return ret; 508 return ret;
555 if (dma_mmap_from_global_coherent(vma, <<
556 return ret; <<
557 509
558 if (vma->vm_pgoff >= count || user_cou 510 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
559 return -ENXIO; 511 return -ENXIO;
560 return remap_pfn_range(vma, vma->vm_st 512 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
561 user_count << PAGE_SHI 513 user_count << PAGE_SHIFT, vma->vm_page_prot);
562 } 514 }
563 515
564 int dma_direct_supported(struct device *dev, u 516 int dma_direct_supported(struct device *dev, u64 mask)
565 { 517 {
566 u64 min_mask = (max_pfn - 1) << PAGE_S 518 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
567 519
568 /* 520 /*
569 * Because 32-bit DMA masks are so com 521 * Because 32-bit DMA masks are so common we expect every architecture
570 * to be able to satisfy them - either 522 * to be able to satisfy them - either by not supporting more physical
571 * memory, or by providing a ZONE_DMA3 523 * memory, or by providing a ZONE_DMA32. If neither is the case, the
572 * architecture needs to use an IOMMU 524 * architecture needs to use an IOMMU instead of the direct mapping.
573 */ 525 */
574 if (mask >= DMA_BIT_MASK(32)) 526 if (mask >= DMA_BIT_MASK(32))
575 return 1; 527 return 1;
576 528
577 /* 529 /*
578 * This check needs to be against the !! 530 * This check needs to be against the actual bit mask value, so
579 * phys_to_dma_unencrypted() here so t !! 531 * use __phys_to_dma() here so that the SME encryption mask isn't
580 * part of the check. 532 * part of the check.
581 */ 533 */
582 if (IS_ENABLED(CONFIG_ZONE_DMA)) 534 if (IS_ENABLED(CONFIG_ZONE_DMA))
583 min_mask = min_t(u64, min_mask 535 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
584 return mask >= phys_to_dma_unencrypted !! 536 return mask >= __phys_to_dma(dev, min_mask);
585 } <<
586 <<
587 /* <<
588 * To check whether all ram resource ranges ar <<
589 * Returns 0 when further check is needed <<
590 * Returns 1 if there is some RAM range can't <<
591 */ <<
592 static int check_ram_in_range_map(unsigned lon <<
593 unsigned lon <<
594 { <<
595 unsigned long end_pfn = start_pfn + nr <<
596 const struct bus_dma_region *bdr = NUL <<
597 const struct bus_dma_region *m; <<
598 struct device *dev = data; <<
599 <<
600 while (start_pfn < end_pfn) { <<
601 for (m = dev->dma_range_map; P <<
602 unsigned long cpu_star <<
603 <<
604 if (start_pfn >= cpu_s <<
605 start_pfn - cpu_st <<
606 bdr = m; <<
607 break; <<
608 } <<
609 } <<
610 if (!bdr) <<
611 return 1; <<
612 <<
613 start_pfn = PFN_DOWN(bdr->cpu_ <<
614 } <<
615 <<
616 return 0; <<
617 } <<
618 <<
619 bool dma_direct_all_ram_mapped(struct device * <<
620 { <<
621 if (!dev->dma_range_map) <<
622 return true; <<
623 return !walk_system_ram_range(0, PFN_D <<
624 check_ra <<
625 } 537 }
626 538
627 size_t dma_direct_max_mapping_size(struct devi 539 size_t dma_direct_max_mapping_size(struct device *dev)
628 { 540 {
629 /* If SWIOTLB is active, use its maxim 541 /* If SWIOTLB is active, use its maximum mapping size */
630 if (is_swiotlb_active(dev) && !! 542 if (is_swiotlb_active() &&
631 (dma_addressing_limited(dev) || is !! 543 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
632 return swiotlb_max_mapping_siz 544 return swiotlb_max_mapping_size(dev);
633 return SIZE_MAX; 545 return SIZE_MAX;
634 } 546 }
635 547
636 bool dma_direct_need_sync(struct device *dev, 548 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
637 { 549 {
638 return !dev_is_dma_coherent(dev) || 550 return !dev_is_dma_coherent(dev) ||
639 swiotlb_find_pool(dev, dma_to_p !! 551 is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
640 } <<
641 <<
642 /** <<
643 * dma_direct_set_offset - Assign scalar offse <<
644 * @dev: device pointer; needed to "own <<
645 * @cpu_start: beginning of memory region cov <<
646 * @dma_start: beginning of DMA/PCI region co <<
647 * @size: size of the region. <<
648 * <<
649 * This is for the simple case of a uniform of <<
650 * be discovered by "dma-ranges". <<
651 * <<
652 * It returns -ENOMEM if out of memory, -EINVA <<
653 * already exists, 0 otherwise. <<
654 * <<
655 * Note: any call to this from a driver is a b <<
656 * to be described by the device tree or other <<
657 */ <<
658 int dma_direct_set_offset(struct device *dev, <<
659 dma_addr_t dma_start, <<
660 { <<
661 struct bus_dma_region *map; <<
662 u64 offset = (u64)cpu_start - (u64)dma <<
663 <<
664 if (dev->dma_range_map) { <<
665 dev_err(dev, "attempt to add D <<
666 return -EINVAL; <<
667 } <<
668 <<
669 if (!offset) <<
670 return 0; <<
671 <<
672 map = kcalloc(2, sizeof(*map), GFP_KER <<
673 if (!map) <<
674 return -ENOMEM; <<
675 map[0].cpu_start = cpu_start; <<
676 map[0].dma_start = dma_start; <<
677 map[0].size = size; <<
678 dev->dma_range_map = map; <<
679 return 0; <<
680 } 552 }
681 553
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