1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* -*- linux-c -*- --------------------------- 1 /* -*- linux-c -*- ------------------------------------------------------- *
3 * 2 *
4 * Copyright 2002 H. Peter Anvin - All Right 3 * Copyright 2002 H. Peter Anvin - All Rights Reserved
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation, Inc., 53 Temple Place Ste 330,
>> 8 * Boston MA 02111-1307, USA; either version 2 of the License, or
>> 9 * (at your option) any later version; incorporated herein by reference.
5 * 10 *
6 * ------------------------------------------- 11 * ----------------------------------------------------------------------- */
7 12
8 /* 13 /*
9 * raid6/mmx.c 14 * raid6/mmx.c
10 * 15 *
11 * MMX implementation of RAID-6 syndrome funct 16 * MMX implementation of RAID-6 syndrome functions
12 */ 17 */
13 18
14 #ifdef CONFIG_X86_32 19 #ifdef CONFIG_X86_32
15 20
16 #include <linux/raid/pq.h> 21 #include <linux/raid/pq.h>
17 #include "x86.h" 22 #include "x86.h"
18 23
19 /* Shared with raid6/sse1.c */ 24 /* Shared with raid6/sse1.c */
20 const struct raid6_mmx_constants { 25 const struct raid6_mmx_constants {
21 u64 x1d; 26 u64 x1d;
22 } raid6_mmx_constants = { 27 } raid6_mmx_constants = {
23 0x1d1d1d1d1d1d1d1dULL, 28 0x1d1d1d1d1d1d1d1dULL,
24 }; 29 };
25 30
26 static int raid6_have_mmx(void) 31 static int raid6_have_mmx(void)
27 { 32 {
28 /* Not really "boot_cpu" but "all_cpus 33 /* Not really "boot_cpu" but "all_cpus" */
29 return boot_cpu_has(X86_FEATURE_MMX); 34 return boot_cpu_has(X86_FEATURE_MMX);
30 } 35 }
31 36
32 /* 37 /*
33 * Plain MMX implementation 38 * Plain MMX implementation
34 */ 39 */
35 static void raid6_mmx1_gen_syndrome(int disks, 40 static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs)
36 { 41 {
37 u8 **dptr = (u8 **)ptrs; 42 u8 **dptr = (u8 **)ptrs;
38 u8 *p, *q; 43 u8 *p, *q;
39 int d, z, z0; 44 int d, z, z0;
40 45
41 z0 = disks - 3; /* Highest dat 46 z0 = disks - 3; /* Highest data disk */
42 p = dptr[z0+1]; /* XOR parity 47 p = dptr[z0+1]; /* XOR parity */
43 q = dptr[z0+2]; /* RS syndrome 48 q = dptr[z0+2]; /* RS syndrome */
44 49
45 kernel_fpu_begin(); 50 kernel_fpu_begin();
46 51
47 asm volatile("movq %0,%%mm0" : : "m" ( 52 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
48 asm volatile("pxor %mm5,%mm5"); /* Zer 53 asm volatile("pxor %mm5,%mm5"); /* Zero temp */
49 54
50 for ( d = 0 ; d < bytes ; d += 8 ) { 55 for ( d = 0 ; d < bytes ; d += 8 ) {
51 asm volatile("movq %0,%%mm2" : 56 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */
52 asm volatile("movq %mm2,%mm4") 57 asm volatile("movq %mm2,%mm4"); /* Q[0] */
53 for ( z = z0-1 ; z >= 0 ; z-- 58 for ( z = z0-1 ; z >= 0 ; z-- ) {
54 asm volatile("movq %0, 59 asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d]));
55 asm volatile("pcmpgtb 60 asm volatile("pcmpgtb %mm4,%mm5");
56 asm volatile("paddb %m 61 asm volatile("paddb %mm4,%mm4");
57 asm volatile("pand %mm 62 asm volatile("pand %mm0,%mm5");
58 asm volatile("pxor %mm 63 asm volatile("pxor %mm5,%mm4");
59 asm volatile("pxor %mm 64 asm volatile("pxor %mm5,%mm5");
60 asm volatile("pxor %mm 65 asm volatile("pxor %mm6,%mm2");
61 asm volatile("pxor %mm 66 asm volatile("pxor %mm6,%mm4");
62 } 67 }
63 asm volatile("movq %%mm2,%0" : 68 asm volatile("movq %%mm2,%0" : "=m" (p[d]));
64 asm volatile("pxor %mm2,%mm2") 69 asm volatile("pxor %mm2,%mm2");
65 asm volatile("movq %%mm4,%0" : 70 asm volatile("movq %%mm4,%0" : "=m" (q[d]));
66 asm volatile("pxor %mm4,%mm4") 71 asm volatile("pxor %mm4,%mm4");
67 } 72 }
68 73
69 kernel_fpu_end(); 74 kernel_fpu_end();
70 } 75 }
71 76
72 const struct raid6_calls raid6_mmxx1 = { 77 const struct raid6_calls raid6_mmxx1 = {
73 raid6_mmx1_gen_syndrome, 78 raid6_mmx1_gen_syndrome,
74 NULL, /* XOR not yet 79 NULL, /* XOR not yet implemented */
75 raid6_have_mmx, 80 raid6_have_mmx,
76 "mmxx1", 81 "mmxx1",
77 0 82 0
78 }; 83 };
79 84
80 /* 85 /*
81 * Unrolled-by-2 MMX implementation 86 * Unrolled-by-2 MMX implementation
82 */ 87 */
83 static void raid6_mmx2_gen_syndrome(int disks, 88 static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs)
84 { 89 {
85 u8 **dptr = (u8 **)ptrs; 90 u8 **dptr = (u8 **)ptrs;
86 u8 *p, *q; 91 u8 *p, *q;
87 int d, z, z0; 92 int d, z, z0;
88 93
89 z0 = disks - 3; /* Highest dat 94 z0 = disks - 3; /* Highest data disk */
90 p = dptr[z0+1]; /* XOR parity 95 p = dptr[z0+1]; /* XOR parity */
91 q = dptr[z0+2]; /* RS syndrome 96 q = dptr[z0+2]; /* RS syndrome */
92 97
93 kernel_fpu_begin(); 98 kernel_fpu_begin();
94 99
95 asm volatile("movq %0,%%mm0" : : "m" ( 100 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
96 asm volatile("pxor %mm5,%mm5"); /* Zer 101 asm volatile("pxor %mm5,%mm5"); /* Zero temp */
97 asm volatile("pxor %mm7,%mm7"); /* Zer 102 asm volatile("pxor %mm7,%mm7"); /* Zero temp */
98 103
99 for ( d = 0 ; d < bytes ; d += 16 ) { 104 for ( d = 0 ; d < bytes ; d += 16 ) {
100 asm volatile("movq %0,%%mm2" : 105 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */
101 asm volatile("movq %0,%%mm3" : 106 asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8]));
102 asm volatile("movq %mm2,%mm4") 107 asm volatile("movq %mm2,%mm4"); /* Q[0] */
103 asm volatile("movq %mm3,%mm6") 108 asm volatile("movq %mm3,%mm6"); /* Q[1] */
104 for ( z = z0-1 ; z >= 0 ; z-- 109 for ( z = z0-1 ; z >= 0 ; z-- ) {
105 asm volatile("pcmpgtb 110 asm volatile("pcmpgtb %mm4,%mm5");
106 asm volatile("pcmpgtb 111 asm volatile("pcmpgtb %mm6,%mm7");
107 asm volatile("paddb %m 112 asm volatile("paddb %mm4,%mm4");
108 asm volatile("paddb %m 113 asm volatile("paddb %mm6,%mm6");
109 asm volatile("pand %mm 114 asm volatile("pand %mm0,%mm5");
110 asm volatile("pand %mm 115 asm volatile("pand %mm0,%mm7");
111 asm volatile("pxor %mm 116 asm volatile("pxor %mm5,%mm4");
112 asm volatile("pxor %mm 117 asm volatile("pxor %mm7,%mm6");
113 asm volatile("movq %0, 118 asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d]));
114 asm volatile("movq %0, 119 asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8]));
115 asm volatile("pxor %mm 120 asm volatile("pxor %mm5,%mm2");
116 asm volatile("pxor %mm 121 asm volatile("pxor %mm7,%mm3");
117 asm volatile("pxor %mm 122 asm volatile("pxor %mm5,%mm4");
118 asm volatile("pxor %mm 123 asm volatile("pxor %mm7,%mm6");
119 asm volatile("pxor %mm 124 asm volatile("pxor %mm5,%mm5");
120 asm volatile("pxor %mm 125 asm volatile("pxor %mm7,%mm7");
121 } 126 }
122 asm volatile("movq %%mm2,%0" : 127 asm volatile("movq %%mm2,%0" : "=m" (p[d]));
123 asm volatile("movq %%mm3,%0" : 128 asm volatile("movq %%mm3,%0" : "=m" (p[d+8]));
124 asm volatile("movq %%mm4,%0" : 129 asm volatile("movq %%mm4,%0" : "=m" (q[d]));
125 asm volatile("movq %%mm6,%0" : 130 asm volatile("movq %%mm6,%0" : "=m" (q[d+8]));
126 } 131 }
127 132
128 kernel_fpu_end(); 133 kernel_fpu_end();
129 } 134 }
130 135
131 const struct raid6_calls raid6_mmxx2 = { 136 const struct raid6_calls raid6_mmxx2 = {
132 raid6_mmx2_gen_syndrome, 137 raid6_mmx2_gen_syndrome,
133 NULL, /* XOR not yet 138 NULL, /* XOR not yet implemented */
134 raid6_have_mmx, 139 raid6_have_mmx,
135 "mmxx2", 140 "mmxx2",
136 0 141 0
137 }; 142 };
138 143
139 #endif 144 #endif
140 145
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