1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2012 Intel Corporation 2 * Copyright (C) 2012 Intel Corporation
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or
>> 5 * modify it under the terms of the GNU General Public License
>> 6 * as published by the Free Software Foundation; version 2
>> 7 * of the License.
4 */ 8 */
5 9
>> 10 #ifdef CONFIG_AS_SSSE3
>> 11
6 #include <linux/raid/pq.h> 12 #include <linux/raid/pq.h>
7 #include "x86.h" 13 #include "x86.h"
8 14
9 static int raid6_has_ssse3(void) 15 static int raid6_has_ssse3(void)
10 { 16 {
11 return boot_cpu_has(X86_FEATURE_XMM) & 17 return boot_cpu_has(X86_FEATURE_XMM) &&
12 boot_cpu_has(X86_FEATURE_XMM2) 18 boot_cpu_has(X86_FEATURE_XMM2) &&
13 boot_cpu_has(X86_FEATURE_SSSE3 19 boot_cpu_has(X86_FEATURE_SSSE3);
14 } 20 }
15 21
16 static void raid6_2data_recov_ssse3(int disks, 22 static void raid6_2data_recov_ssse3(int disks, size_t bytes, int faila,
17 int failb, void **ptrs) 23 int failb, void **ptrs)
18 { 24 {
19 u8 *p, *q, *dp, *dq; 25 u8 *p, *q, *dp, *dq;
20 const u8 *pbmul; /* P multiplie 26 const u8 *pbmul; /* P multiplier table for B data */
21 const u8 *qmul; /* Q multiplie 27 const u8 *qmul; /* Q multiplier table (for both) */
22 static const u8 __aligned(16) x0f[16] 28 static const u8 __aligned(16) x0f[16] = {
23 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 29 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
24 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 30 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f};
25 31
26 p = (u8 *)ptrs[disks-2]; 32 p = (u8 *)ptrs[disks-2];
27 q = (u8 *)ptrs[disks-1]; 33 q = (u8 *)ptrs[disks-1];
28 34
29 /* Compute syndrome with zero for the 35 /* Compute syndrome with zero for the missing data pages
30 Use the dead data pages as temporar 36 Use the dead data pages as temporary storage for
31 delta p and delta q */ 37 delta p and delta q */
32 dp = (u8 *)ptrs[faila]; 38 dp = (u8 *)ptrs[faila];
33 ptrs[faila] = (void *)raid6_empty_zero 39 ptrs[faila] = (void *)raid6_empty_zero_page;
34 ptrs[disks-2] = dp; 40 ptrs[disks-2] = dp;
35 dq = (u8 *)ptrs[failb]; 41 dq = (u8 *)ptrs[failb];
36 ptrs[failb] = (void *)raid6_empty_zero 42 ptrs[failb] = (void *)raid6_empty_zero_page;
37 ptrs[disks-1] = dq; 43 ptrs[disks-1] = dq;
38 44
39 raid6_call.gen_syndrome(disks, bytes, 45 raid6_call.gen_syndrome(disks, bytes, ptrs);
40 46
41 /* Restore pointer table */ 47 /* Restore pointer table */
42 ptrs[faila] = dp; 48 ptrs[faila] = dp;
43 ptrs[failb] = dq; 49 ptrs[failb] = dq;
44 ptrs[disks-2] = p; 50 ptrs[disks-2] = p;
45 ptrs[disks-1] = q; 51 ptrs[disks-1] = q;
46 52
47 /* Now, pick the proper data tables */ 53 /* Now, pick the proper data tables */
48 pbmul = raid6_vgfmul[raid6_gfexi[failb 54 pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]];
49 qmul = raid6_vgfmul[raid6_gfinv[raid6 55 qmul = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila] ^
50 raid6_gfexp[failb]]]; 56 raid6_gfexp[failb]]];
51 57
52 kernel_fpu_begin(); 58 kernel_fpu_begin();
53 59
54 asm volatile("movdqa %0,%%xmm7" : : "m 60 asm volatile("movdqa %0,%%xmm7" : : "m" (x0f[0]));
55 61
56 #ifdef CONFIG_X86_64 62 #ifdef CONFIG_X86_64
57 asm volatile("movdqa %0,%%xmm6" : : "m 63 asm volatile("movdqa %0,%%xmm6" : : "m" (qmul[0]));
58 asm volatile("movdqa %0,%%xmm14" : : " 64 asm volatile("movdqa %0,%%xmm14" : : "m" (pbmul[0]));
59 asm volatile("movdqa %0,%%xmm15" : : " 65 asm volatile("movdqa %0,%%xmm15" : : "m" (pbmul[16]));
60 #endif 66 #endif
61 67
62 /* Now do it... */ 68 /* Now do it... */
63 while (bytes) { 69 while (bytes) {
64 #ifdef CONFIG_X86_64 70 #ifdef CONFIG_X86_64
65 /* xmm6, xmm14, xmm15 */ 71 /* xmm6, xmm14, xmm15 */
66 72
67 asm volatile("movdqa %0,%%xmm1 73 asm volatile("movdqa %0,%%xmm1" : : "m" (q[0]));
68 asm volatile("movdqa %0,%%xmm9 74 asm volatile("movdqa %0,%%xmm9" : : "m" (q[16]));
69 asm volatile("movdqa %0,%%xmm0 75 asm volatile("movdqa %0,%%xmm0" : : "m" (p[0]));
70 asm volatile("movdqa %0,%%xmm8 76 asm volatile("movdqa %0,%%xmm8" : : "m" (p[16]));
71 asm volatile("pxor %0,%%xmm1 77 asm volatile("pxor %0,%%xmm1" : : "m" (dq[0]));
72 asm volatile("pxor %0,%%xmm9 78 asm volatile("pxor %0,%%xmm9" : : "m" (dq[16]));
73 asm volatile("pxor %0,%%xmm0 79 asm volatile("pxor %0,%%xmm0" : : "m" (dp[0]));
74 asm volatile("pxor %0,%%xmm8 80 asm volatile("pxor %0,%%xmm8" : : "m" (dp[16]));
75 81
76 /* xmm0/8 = px */ 82 /* xmm0/8 = px */
77 83
78 asm volatile("movdqa %xmm6,%xm 84 asm volatile("movdqa %xmm6,%xmm4");
79 asm volatile("movdqa %0,%%xmm5 85 asm volatile("movdqa %0,%%xmm5" : : "m" (qmul[16]));
80 asm volatile("movdqa %xmm6,%xm 86 asm volatile("movdqa %xmm6,%xmm12");
81 asm volatile("movdqa %xmm5,%xm 87 asm volatile("movdqa %xmm5,%xmm13");
82 asm volatile("movdqa %xmm1,%xm 88 asm volatile("movdqa %xmm1,%xmm3");
83 asm volatile("movdqa %xmm9,%xm 89 asm volatile("movdqa %xmm9,%xmm11");
84 asm volatile("movdqa %xmm0,%xm 90 asm volatile("movdqa %xmm0,%xmm2"); /* xmm2/10 = px */
85 asm volatile("movdqa %xmm8,%xm 91 asm volatile("movdqa %xmm8,%xmm10");
86 asm volatile("psraw $4,%xmm1" 92 asm volatile("psraw $4,%xmm1");
87 asm volatile("psraw $4,%xmm9" 93 asm volatile("psraw $4,%xmm9");
88 asm volatile("pand %xmm7,%xm 94 asm volatile("pand %xmm7,%xmm3");
89 asm volatile("pand %xmm7,%xm 95 asm volatile("pand %xmm7,%xmm11");
90 asm volatile("pand %xmm7,%xm 96 asm volatile("pand %xmm7,%xmm1");
91 asm volatile("pand %xmm7,%xm 97 asm volatile("pand %xmm7,%xmm9");
92 asm volatile("pshufb %xmm3,%xm 98 asm volatile("pshufb %xmm3,%xmm4");
93 asm volatile("pshufb %xmm11,%x 99 asm volatile("pshufb %xmm11,%xmm12");
94 asm volatile("pshufb %xmm1,%xm 100 asm volatile("pshufb %xmm1,%xmm5");
95 asm volatile("pshufb %xmm9,%xm 101 asm volatile("pshufb %xmm9,%xmm13");
96 asm volatile("pxor %xmm4,%xm 102 asm volatile("pxor %xmm4,%xmm5");
97 asm volatile("pxor %xmm12,%x 103 asm volatile("pxor %xmm12,%xmm13");
98 104
99 /* xmm5/13 = qx */ 105 /* xmm5/13 = qx */
100 106
101 asm volatile("movdqa %xmm14,%x 107 asm volatile("movdqa %xmm14,%xmm4");
102 asm volatile("movdqa %xmm15,%x 108 asm volatile("movdqa %xmm15,%xmm1");
103 asm volatile("movdqa %xmm14,%x 109 asm volatile("movdqa %xmm14,%xmm12");
104 asm volatile("movdqa %xmm15,%x 110 asm volatile("movdqa %xmm15,%xmm9");
105 asm volatile("movdqa %xmm2,%xm 111 asm volatile("movdqa %xmm2,%xmm3");
106 asm volatile("movdqa %xmm10,%x 112 asm volatile("movdqa %xmm10,%xmm11");
107 asm volatile("psraw $4,%xmm2" 113 asm volatile("psraw $4,%xmm2");
108 asm volatile("psraw $4,%xmm10 114 asm volatile("psraw $4,%xmm10");
109 asm volatile("pand %xmm7,%xm 115 asm volatile("pand %xmm7,%xmm3");
110 asm volatile("pand %xmm7,%xm 116 asm volatile("pand %xmm7,%xmm11");
111 asm volatile("pand %xmm7,%xm 117 asm volatile("pand %xmm7,%xmm2");
112 asm volatile("pand %xmm7,%xm 118 asm volatile("pand %xmm7,%xmm10");
113 asm volatile("pshufb %xmm3,%xm 119 asm volatile("pshufb %xmm3,%xmm4");
114 asm volatile("pshufb %xmm11,%x 120 asm volatile("pshufb %xmm11,%xmm12");
115 asm volatile("pshufb %xmm2,%xm 121 asm volatile("pshufb %xmm2,%xmm1");
116 asm volatile("pshufb %xmm10,%x 122 asm volatile("pshufb %xmm10,%xmm9");
117 asm volatile("pxor %xmm4,%xm 123 asm volatile("pxor %xmm4,%xmm1");
118 asm volatile("pxor %xmm12,%x 124 asm volatile("pxor %xmm12,%xmm9");
119 125
120 /* xmm1/9 = pbmul[px] */ 126 /* xmm1/9 = pbmul[px] */
121 asm volatile("pxor %xmm5,%xm 127 asm volatile("pxor %xmm5,%xmm1");
122 asm volatile("pxor %xmm13,%x 128 asm volatile("pxor %xmm13,%xmm9");
123 /* xmm1/9 = db = DQ */ 129 /* xmm1/9 = db = DQ */
124 asm volatile("movdqa %%xmm1,%0 130 asm volatile("movdqa %%xmm1,%0" : "=m" (dq[0]));
125 asm volatile("movdqa %%xmm9,%0 131 asm volatile("movdqa %%xmm9,%0" : "=m" (dq[16]));
126 132
127 asm volatile("pxor %xmm1,%xm 133 asm volatile("pxor %xmm1,%xmm0");
128 asm volatile("pxor %xmm9,%xm 134 asm volatile("pxor %xmm9,%xmm8");
129 asm volatile("movdqa %%xmm0,%0 135 asm volatile("movdqa %%xmm0,%0" : "=m" (dp[0]));
130 asm volatile("movdqa %%xmm8,%0 136 asm volatile("movdqa %%xmm8,%0" : "=m" (dp[16]));
131 137
132 bytes -= 32; 138 bytes -= 32;
133 p += 32; 139 p += 32;
134 q += 32; 140 q += 32;
135 dp += 32; 141 dp += 32;
136 dq += 32; 142 dq += 32;
137 #else 143 #else
138 asm volatile("movdqa %0,%%xmm1 144 asm volatile("movdqa %0,%%xmm1" : : "m" (*q));
139 asm volatile("movdqa %0,%%xmm0 145 asm volatile("movdqa %0,%%xmm0" : : "m" (*p));
140 asm volatile("pxor %0,%%xmm1 146 asm volatile("pxor %0,%%xmm1" : : "m" (*dq));
141 asm volatile("pxor %0,%%xmm0 147 asm volatile("pxor %0,%%xmm0" : : "m" (*dp));
142 148
143 /* 1 = dq ^ q 149 /* 1 = dq ^ q
144 * 0 = dp ^ p 150 * 0 = dp ^ p
145 */ 151 */
146 asm volatile("movdqa %0,%%xmm4 152 asm volatile("movdqa %0,%%xmm4" : : "m" (qmul[0]));
147 asm volatile("movdqa %0,%%xmm5 153 asm volatile("movdqa %0,%%xmm5" : : "m" (qmul[16]));
148 154
149 asm volatile("movdqa %xmm1,%xm 155 asm volatile("movdqa %xmm1,%xmm3");
150 asm volatile("psraw $4,%xmm1" 156 asm volatile("psraw $4,%xmm1");
151 asm volatile("pand %xmm7,%xm 157 asm volatile("pand %xmm7,%xmm3");
152 asm volatile("pand %xmm7,%xm 158 asm volatile("pand %xmm7,%xmm1");
153 asm volatile("pshufb %xmm3,%xm 159 asm volatile("pshufb %xmm3,%xmm4");
154 asm volatile("pshufb %xmm1,%xm 160 asm volatile("pshufb %xmm1,%xmm5");
155 asm volatile("pxor %xmm4,%xm 161 asm volatile("pxor %xmm4,%xmm5");
156 162
157 asm volatile("movdqa %xmm0,%xm 163 asm volatile("movdqa %xmm0,%xmm2"); /* xmm2 = px */
158 164
159 /* xmm5 = qx */ 165 /* xmm5 = qx */
160 166
161 asm volatile("movdqa %0,%%xmm4 167 asm volatile("movdqa %0,%%xmm4" : : "m" (pbmul[0]));
162 asm volatile("movdqa %0,%%xmm1 168 asm volatile("movdqa %0,%%xmm1" : : "m" (pbmul[16]));
163 asm volatile("movdqa %xmm2,%xm 169 asm volatile("movdqa %xmm2,%xmm3");
164 asm volatile("psraw $4,%xmm2" 170 asm volatile("psraw $4,%xmm2");
165 asm volatile("pand %xmm7,%xm 171 asm volatile("pand %xmm7,%xmm3");
166 asm volatile("pand %xmm7,%xm 172 asm volatile("pand %xmm7,%xmm2");
167 asm volatile("pshufb %xmm3,%xm 173 asm volatile("pshufb %xmm3,%xmm4");
168 asm volatile("pshufb %xmm2,%xm 174 asm volatile("pshufb %xmm2,%xmm1");
169 asm volatile("pxor %xmm4,%xm 175 asm volatile("pxor %xmm4,%xmm1");
170 176
171 /* xmm1 = pbmul[px] */ 177 /* xmm1 = pbmul[px] */
172 asm volatile("pxor %xmm5,%xm 178 asm volatile("pxor %xmm5,%xmm1");
173 /* xmm1 = db = DQ */ 179 /* xmm1 = db = DQ */
174 asm volatile("movdqa %%xmm1,%0 180 asm volatile("movdqa %%xmm1,%0" : "=m" (*dq));
175 181
176 asm volatile("pxor %xmm1,%xm 182 asm volatile("pxor %xmm1,%xmm0");
177 asm volatile("movdqa %%xmm0,%0 183 asm volatile("movdqa %%xmm0,%0" : "=m" (*dp));
178 184
179 bytes -= 16; 185 bytes -= 16;
180 p += 16; 186 p += 16;
181 q += 16; 187 q += 16;
182 dp += 16; 188 dp += 16;
183 dq += 16; 189 dq += 16;
184 #endif 190 #endif
185 } 191 }
186 192
187 kernel_fpu_end(); 193 kernel_fpu_end();
188 } 194 }
189 195
190 196
191 static void raid6_datap_recov_ssse3(int disks, 197 static void raid6_datap_recov_ssse3(int disks, size_t bytes, int faila,
192 void **ptrs) 198 void **ptrs)
193 { 199 {
194 u8 *p, *q, *dq; 200 u8 *p, *q, *dq;
195 const u8 *qmul; /* Q multiplie 201 const u8 *qmul; /* Q multiplier table */
196 static const u8 __aligned(16) x0f[16] 202 static const u8 __aligned(16) x0f[16] = {
197 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 203 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
198 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 204 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f};
199 205
200 p = (u8 *)ptrs[disks-2]; 206 p = (u8 *)ptrs[disks-2];
201 q = (u8 *)ptrs[disks-1]; 207 q = (u8 *)ptrs[disks-1];
202 208
203 /* Compute syndrome with zero for the 209 /* Compute syndrome with zero for the missing data page
204 Use the dead data page as temporary 210 Use the dead data page as temporary storage for delta q */
205 dq = (u8 *)ptrs[faila]; 211 dq = (u8 *)ptrs[faila];
206 ptrs[faila] = (void *)raid6_empty_zero 212 ptrs[faila] = (void *)raid6_empty_zero_page;
207 ptrs[disks-1] = dq; 213 ptrs[disks-1] = dq;
208 214
209 raid6_call.gen_syndrome(disks, bytes, 215 raid6_call.gen_syndrome(disks, bytes, ptrs);
210 216
211 /* Restore pointer table */ 217 /* Restore pointer table */
212 ptrs[faila] = dq; 218 ptrs[faila] = dq;
213 ptrs[disks-1] = q; 219 ptrs[disks-1] = q;
214 220
215 /* Now, pick the proper data tables */ 221 /* Now, pick the proper data tables */
216 qmul = raid6_vgfmul[raid6_gfinv[raid6 222 qmul = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila]]];
217 223
218 kernel_fpu_begin(); 224 kernel_fpu_begin();
219 225
220 asm volatile("movdqa %0, %%xmm7" : : " 226 asm volatile("movdqa %0, %%xmm7" : : "m" (x0f[0]));
221 227
222 while (bytes) { 228 while (bytes) {
223 #ifdef CONFIG_X86_64 229 #ifdef CONFIG_X86_64
224 asm volatile("movdqa %0, %%xmm 230 asm volatile("movdqa %0, %%xmm3" : : "m" (dq[0]));
225 asm volatile("movdqa %0, %%xmm 231 asm volatile("movdqa %0, %%xmm4" : : "m" (dq[16]));
226 asm volatile("pxor %0, %%xmm3" 232 asm volatile("pxor %0, %%xmm3" : : "m" (q[0]));
227 asm volatile("movdqa %0, %%xmm 233 asm volatile("movdqa %0, %%xmm0" : : "m" (qmul[0]));
228 234
229 /* xmm3 = q[0] ^ dq[0] */ 235 /* xmm3 = q[0] ^ dq[0] */
230 236
231 asm volatile("pxor %0, %%xmm4" 237 asm volatile("pxor %0, %%xmm4" : : "m" (q[16]));
232 asm volatile("movdqa %0, %%xmm 238 asm volatile("movdqa %0, %%xmm1" : : "m" (qmul[16]));
233 239
234 /* xmm4 = q[16] ^ dq[16] */ 240 /* xmm4 = q[16] ^ dq[16] */
235 241
236 asm volatile("movdqa %xmm3, %x 242 asm volatile("movdqa %xmm3, %xmm6");
237 asm volatile("movdqa %xmm4, %x 243 asm volatile("movdqa %xmm4, %xmm8");
238 244
239 /* xmm4 = xmm8 = q[16] ^ dq[16 245 /* xmm4 = xmm8 = q[16] ^ dq[16] */
240 246
241 asm volatile("psraw $4, %xmm3" 247 asm volatile("psraw $4, %xmm3");
242 asm volatile("pand %xmm7, %xmm 248 asm volatile("pand %xmm7, %xmm6");
243 asm volatile("pand %xmm7, %xmm 249 asm volatile("pand %xmm7, %xmm3");
244 asm volatile("pshufb %xmm6, %x 250 asm volatile("pshufb %xmm6, %xmm0");
245 asm volatile("pshufb %xmm3, %x 251 asm volatile("pshufb %xmm3, %xmm1");
246 asm volatile("movdqa %0, %%xmm 252 asm volatile("movdqa %0, %%xmm10" : : "m" (qmul[0]));
247 asm volatile("pxor %xmm0, %xmm 253 asm volatile("pxor %xmm0, %xmm1");
248 asm volatile("movdqa %0, %%xmm 254 asm volatile("movdqa %0, %%xmm11" : : "m" (qmul[16]));
249 255
250 /* xmm1 = qmul[q[0] ^ dq[0]] * 256 /* xmm1 = qmul[q[0] ^ dq[0]] */
251 257
252 asm volatile("psraw $4, %xmm4" 258 asm volatile("psraw $4, %xmm4");
253 asm volatile("pand %xmm7, %xmm 259 asm volatile("pand %xmm7, %xmm8");
254 asm volatile("pand %xmm7, %xmm 260 asm volatile("pand %xmm7, %xmm4");
255 asm volatile("pshufb %xmm8, %x 261 asm volatile("pshufb %xmm8, %xmm10");
256 asm volatile("pshufb %xmm4, %x 262 asm volatile("pshufb %xmm4, %xmm11");
257 asm volatile("movdqa %0, %%xmm 263 asm volatile("movdqa %0, %%xmm2" : : "m" (p[0]));
258 asm volatile("pxor %xmm10, %xm 264 asm volatile("pxor %xmm10, %xmm11");
259 asm volatile("movdqa %0, %%xmm 265 asm volatile("movdqa %0, %%xmm12" : : "m" (p[16]));
260 266
261 /* xmm11 = qmul[q[16] ^ dq[16] 267 /* xmm11 = qmul[q[16] ^ dq[16]] */
262 268
263 asm volatile("pxor %xmm1, %xmm 269 asm volatile("pxor %xmm1, %xmm2");
264 270
265 /* xmm2 = p[0] ^ qmul[q[0] ^ d 271 /* xmm2 = p[0] ^ qmul[q[0] ^ dq[0]] */
266 272
267 asm volatile("pxor %xmm11, %xm 273 asm volatile("pxor %xmm11, %xmm12");
268 274
269 /* xmm12 = p[16] ^ qmul[q[16] 275 /* xmm12 = p[16] ^ qmul[q[16] ^ dq[16]] */
270 276
271 asm volatile("movdqa %%xmm1, % 277 asm volatile("movdqa %%xmm1, %0" : "=m" (dq[0]));
272 asm volatile("movdqa %%xmm11, 278 asm volatile("movdqa %%xmm11, %0" : "=m" (dq[16]));
273 279
274 asm volatile("movdqa %%xmm2, % 280 asm volatile("movdqa %%xmm2, %0" : "=m" (p[0]));
275 asm volatile("movdqa %%xmm12, 281 asm volatile("movdqa %%xmm12, %0" : "=m" (p[16]));
276 282
277 bytes -= 32; 283 bytes -= 32;
278 p += 32; 284 p += 32;
279 q += 32; 285 q += 32;
280 dq += 32; 286 dq += 32;
281 287
282 #else 288 #else
283 asm volatile("movdqa %0, %%xmm 289 asm volatile("movdqa %0, %%xmm3" : : "m" (dq[0]));
284 asm volatile("movdqa %0, %%xmm 290 asm volatile("movdqa %0, %%xmm0" : : "m" (qmul[0]));
285 asm volatile("pxor %0, %%xmm3" 291 asm volatile("pxor %0, %%xmm3" : : "m" (q[0]));
286 asm volatile("movdqa %0, %%xmm 292 asm volatile("movdqa %0, %%xmm1" : : "m" (qmul[16]));
287 293
288 /* xmm3 = *q ^ *dq */ 294 /* xmm3 = *q ^ *dq */
289 295
290 asm volatile("movdqa %xmm3, %x 296 asm volatile("movdqa %xmm3, %xmm6");
291 asm volatile("movdqa %0, %%xmm 297 asm volatile("movdqa %0, %%xmm2" : : "m" (p[0]));
292 asm volatile("psraw $4, %xmm3" 298 asm volatile("psraw $4, %xmm3");
293 asm volatile("pand %xmm7, %xmm 299 asm volatile("pand %xmm7, %xmm6");
294 asm volatile("pand %xmm7, %xmm 300 asm volatile("pand %xmm7, %xmm3");
295 asm volatile("pshufb %xmm6, %x 301 asm volatile("pshufb %xmm6, %xmm0");
296 asm volatile("pshufb %xmm3, %x 302 asm volatile("pshufb %xmm3, %xmm1");
297 asm volatile("pxor %xmm0, %xmm 303 asm volatile("pxor %xmm0, %xmm1");
298 304
299 /* xmm1 = qmul[*q ^ *dq */ 305 /* xmm1 = qmul[*q ^ *dq */
300 306
301 asm volatile("pxor %xmm1, %xmm 307 asm volatile("pxor %xmm1, %xmm2");
302 308
303 /* xmm2 = *p ^ qmul[*q ^ *dq] 309 /* xmm2 = *p ^ qmul[*q ^ *dq] */
304 310
305 asm volatile("movdqa %%xmm1, % 311 asm volatile("movdqa %%xmm1, %0" : "=m" (dq[0]));
306 asm volatile("movdqa %%xmm2, % 312 asm volatile("movdqa %%xmm2, %0" : "=m" (p[0]));
307 313
308 bytes -= 16; 314 bytes -= 16;
309 p += 16; 315 p += 16;
310 q += 16; 316 q += 16;
311 dq += 16; 317 dq += 16;
312 #endif 318 #endif
313 } 319 }
314 320
315 kernel_fpu_end(); 321 kernel_fpu_end();
316 } 322 }
317 323
318 const struct raid6_recov_calls raid6_recov_sss 324 const struct raid6_recov_calls raid6_recov_ssse3 = {
319 .data2 = raid6_2data_recov_ssse3, 325 .data2 = raid6_2data_recov_ssse3,
320 .datap = raid6_datap_recov_ssse3, 326 .datap = raid6_datap_recov_ssse3,
321 .valid = raid6_has_ssse3, 327 .valid = raid6_has_ssse3,
322 #ifdef CONFIG_X86_64 328 #ifdef CONFIG_X86_64
323 .name = "ssse3x2", 329 .name = "ssse3x2",
324 #else 330 #else
325 .name = "ssse3x1", 331 .name = "ssse3x1",
326 #endif 332 #endif
327 .priority = 1, 333 .priority = 1,
328 }; 334 };
>> 335
>> 336 #else
>> 337 #warning "your version of binutils lacks SSSE3 support"
>> 338 #endif
329 339
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