1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Abilis Systems TB10X SOC device tree 2 * Abilis Systems TB10X SOC device tree
4 * 3 *
5 * Copyright (C) Abilis Systems 2013 4 * Copyright (C) Abilis Systems 2013
6 * 5 *
7 * Author: Christian Ruppert <christian.ruppert 6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License version 2 as
>> 10 * published by the Free Software Foundation.
>> 11 *
>> 12 * This program is distributed in the hope that it will be useful,
>> 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 15 * GNU General Public License for more details.
>> 16 *
>> 17 * You should have received a copy of the GNU General Public License
>> 18 * along with this program; if not, write to the Free Software
>> 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8 */ 20 */
9 21
10 22
11 / { 23 / {
12 compatible = "abilis,arc- 24 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>; 25 #address-cells = <1>;
14 #size-cells = <1>; 26 #size-cells = <1>;
15 27
16 cpus { 28 cpus {
17 #address-cells = <1>; 29 #address-cells = <1>;
18 #size-cells = <0>; 30 #size-cells = <0>;
19 cpu@0 { 31 cpu@0 {
20 device_type = "cpu"; 32 device_type = "cpu";
21 compatible = "snps,arc 33 compatible = "snps,arc770d";
22 reg = <0>; 34 reg = <0>;
23 }; 35 };
24 }; 36 };
25 37
26 /* TIMER0 with interrupt for clockeven 38 /* TIMER0 with interrupt for clockevent */
27 timer0 { 39 timer0 {
28 compatible = "snps,arc-timer"; 40 compatible = "snps,arc-timer";
29 interrupts = <3>; 41 interrupts = <3>;
30 interrupt-parent = <&intc>; 42 interrupt-parent = <&intc>;
31 clocks = <&cpu_clk>; 43 clocks = <&cpu_clk>;
32 }; 44 };
33 45
34 /* TIMER1 for free running clocksource 46 /* TIMER1 for free running clocksource */
35 timer1 { 47 timer1 {
36 compatible = "snps,arc-timer"; 48 compatible = "snps,arc-timer";
37 clocks = <&cpu_clk>; 49 clocks = <&cpu_clk>;
38 }; 50 };
39 51
40 soc100 { 52 soc100 {
41 #address-cells = <1>; 53 #address-cells = <1>;
42 #size-cells = <1>; 54 #size-cells = <1>;
43 device_type = "soc"; 55 device_type = "soc";
44 ranges = <0xfe000000 56 ranges = <0xfe000000 0xfe000000 0x02000000
45 0x000f0000 0x0 !! 57 0x000F0000 0x000F0000 0x00010000>;
46 compatible = "abilis,tb10 58 compatible = "abilis,tb10x", "simple-bus";
47 59
48 pll0: oscillator { 60 pll0: oscillator {
49 compatible = "fixed-cl 61 compatible = "fixed-clock";
50 #clock-cells = <0>; 62 #clock-cells = <0>;
51 clock-output-names = " 63 clock-output-names = "pll0";
52 }; 64 };
53 cpu_clk: clkdiv_cpu { 65 cpu_clk: clkdiv_cpu {
54 compatible = "fixed-fa 66 compatible = "fixed-factor-clock";
55 #clock-cells = <0>; 67 #clock-cells = <0>;
56 clocks = <&pll0>; 68 clocks = <&pll0>;
57 clock-output-names = " 69 clock-output-names = "cpu_clk";
58 }; 70 };
59 ahb_clk: clkdiv_ahb { 71 ahb_clk: clkdiv_ahb {
60 compatible = "fixed-fa 72 compatible = "fixed-factor-clock";
61 #clock-cells = <0>; 73 #clock-cells = <0>;
62 clocks = <&pll0>; 74 clocks = <&pll0>;
63 clock-output-names = " 75 clock-output-names = "ahb_clk";
64 }; 76 };
65 77
66 iomux: iomux@ff10601c { !! 78 iomux: iomux@FF10601c {
67 compatible = "abilis,t 79 compatible = "abilis,tb10x-iomux";
68 #gpio-range-cells = <3 80 #gpio-range-cells = <3>;
69 reg = <0xff10601c 0x4> !! 81 reg = <0xFF10601c 0x4>;
70 }; 82 };
71 83
72 intc: interrupt-controller { 84 intc: interrupt-controller {
73 compatible = "snps,arc 85 compatible = "snps,arc700-intc";
74 interrupt-controller; 86 interrupt-controller;
75 #interrupt-cells = <1> 87 #interrupt-cells = <1>;
76 }; 88 };
77 tb10x_ictl: pic@fe002000 { 89 tb10x_ictl: pic@fe002000 {
78 compatible = "abilis,t 90 compatible = "abilis,tb10x-ictl";
79 reg = <0xfe002000 0x20 !! 91 reg = <0xFE002000 0x20>;
80 interrupt-controller; 92 interrupt-controller;
81 #interrupt-cells = <2> 93 #interrupt-cells = <2>;
82 interrupt-parent = <&i 94 interrupt-parent = <&intc>;
83 interrupts = <5 6 7 8 95 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
84 20 21 96 20 21 22 23 24 25 26 27 28 29 30 31>;
85 }; 97 };
86 98
87 uart@ff100000 { !! 99 uart@FF100000 {
88 compatible = "snps,dw- 100 compatible = "snps,dw-apb-uart";
89 reg = <0xff100000 0x10 !! 101 reg = <0xFF100000 0x100>;
90 clock-frequency = <166 102 clock-frequency = <166666666>;
91 interrupts = <25 8>; 103 interrupts = <25 8>;
92 reg-shift = <2>; 104 reg-shift = <2>;
93 reg-io-width = <4>; 105 reg-io-width = <4>;
94 interrupt-parent = <&t 106 interrupt-parent = <&tb10x_ictl>;
95 }; 107 };
96 ethernet@fe100000 { !! 108 ethernet@FE100000 {
97 compatible = "snps,dwm 109 compatible = "snps,dwmac-3.70a","snps,dwmac";
98 reg = <0xfe100000 0x10 !! 110 reg = <0xFE100000 0x1058>;
99 interrupt-parent = <&t 111 interrupt-parent = <&tb10x_ictl>;
100 interrupts = <6 8>; 112 interrupts = <6 8>;
101 interrupt-names = "mac 113 interrupt-names = "macirq";
102 clocks = <&ahb_clk>; 114 clocks = <&ahb_clk>;
103 clock-names = "stmmace 115 clock-names = "stmmaceth";
104 }; 116 };
105 dma@fe000000 { !! 117 dma@FE000000 {
106 compatible = "snps,dma 118 compatible = "snps,dma-spear1340";
107 reg = <0xfe000000 0x40 !! 119 reg = <0xFE000000 0x400>;
108 interrupt-parent = <&t 120 interrupt-parent = <&tb10x_ictl>;
109 interrupts = <14 8>; 121 interrupts = <14 8>;
110 dma-channels = <6>; 122 dma-channels = <6>;
111 dma-requests = <0>; 123 dma-requests = <0>;
112 dma-masters = <1>; 124 dma-masters = <1>;
113 #dma-cells = <3>; 125 #dma-cells = <3>;
114 chan_allocation_order 126 chan_allocation_order = <0>;
115 chan_priority = <1>; 127 chan_priority = <1>;
116 block_size = <0x7ff>; 128 block_size = <0x7ff>;
117 data-width = <4>; 129 data-width = <4>;
118 clocks = <&ahb_clk>; 130 clocks = <&ahb_clk>;
119 clock-names = "hclk"; 131 clock-names = "hclk";
120 multi-block = <1 1 1 1 132 multi-block = <1 1 1 1 1 1>;
121 }; 133 };
122 134
123 i2c0: i2c@ff120000 { !! 135 i2c0: i2c@FF120000 {
124 #address-cells = <1>; 136 #address-cells = <1>;
125 #size-cells = <0>; 137 #size-cells = <0>;
126 compatible = "snps,des 138 compatible = "snps,designware-i2c";
127 reg = <0xff120000 0x10 !! 139 reg = <0xFF120000 0x1000>;
128 interrupt-parent = <&t 140 interrupt-parent = <&tb10x_ictl>;
129 interrupts = <12 8>; 141 interrupts = <12 8>;
130 clocks = <&ahb_clk>; 142 clocks = <&ahb_clk>;
131 }; 143 };
132 i2c1: i2c@ff121000 { !! 144 i2c1: i2c@FF121000 {
133 #address-cells = <1>; 145 #address-cells = <1>;
134 #size-cells = <0>; 146 #size-cells = <0>;
135 compatible = "snps,des 147 compatible = "snps,designware-i2c";
136 reg = <0xff121000 0x10 !! 148 reg = <0xFF121000 0x1000>;
137 interrupt-parent = <&t 149 interrupt-parent = <&tb10x_ictl>;
138 interrupts = <12 8>; 150 interrupts = <12 8>;
139 clocks = <&ahb_clk>; 151 clocks = <&ahb_clk>;
140 }; 152 };
141 i2c2: i2c@ff122000 { !! 153 i2c2: i2c@FF122000 {
142 #address-cells = <1>; 154 #address-cells = <1>;
143 #size-cells = <0>; 155 #size-cells = <0>;
144 compatible = "snps,des 156 compatible = "snps,designware-i2c";
145 reg = <0xff122000 0x10 !! 157 reg = <0xFF122000 0x1000>;
146 interrupt-parent = <&t 158 interrupt-parent = <&tb10x_ictl>;
147 interrupts = <12 8>; 159 interrupts = <12 8>;
148 clocks = <&ahb_clk>; 160 clocks = <&ahb_clk>;
149 }; 161 };
150 i2c3: i2c@ff123000 { !! 162 i2c3: i2c@FF123000 {
151 #address-cells = <1>; 163 #address-cells = <1>;
152 #size-cells = <0>; 164 #size-cells = <0>;
153 compatible = "snps,des 165 compatible = "snps,designware-i2c";
154 reg = <0xff123000 0x10 !! 166 reg = <0xFF123000 0x1000>;
155 interrupt-parent = <&t 167 interrupt-parent = <&tb10x_ictl>;
156 interrupts = <12 8>; 168 interrupts = <12 8>;
157 clocks = <&ahb_clk>; 169 clocks = <&ahb_clk>;
158 }; 170 };
159 i2c4: i2c@ff124000 { !! 171 i2c4: i2c@FF124000 {
160 #address-cells = <1>; 172 #address-cells = <1>;
161 #size-cells = <0>; 173 #size-cells = <0>;
162 compatible = "snps,des 174 compatible = "snps,designware-i2c";
163 reg = <0xff124000 0x10 !! 175 reg = <0xFF124000 0x1000>;
164 interrupt-parent = <&t 176 interrupt-parent = <&tb10x_ictl>;
165 interrupts = <12 8>; 177 interrupts = <12 8>;
166 clocks = <&ahb_clk>; 178 clocks = <&ahb_clk>;
167 }; 179 };
168 180
169 spi0: spi@fe010000 { !! 181 spi0: spi@0xFE010000 {
170 #address-cells = <1>; 182 #address-cells = <1>;
171 #size-cells = <0>; 183 #size-cells = <0>;
172 cell-index = <0>; 184 cell-index = <0>;
173 compatible = "abilis,t 185 compatible = "abilis,tb100-spi";
174 num-cs = <1>; 186 num-cs = <1>;
175 reg = <0xfe010000 0x20 !! 187 reg = <0xFE010000 0x20>;
176 interrupt-parent = <&t 188 interrupt-parent = <&tb10x_ictl>;
177 interrupts = <26 8>; 189 interrupts = <26 8>;
178 clocks = <&ahb_clk>; 190 clocks = <&ahb_clk>;
179 }; 191 };
180 spi1: spi@fe011000 { !! 192 spi1: spi@0xFE011000 {
181 #address-cells = <1>; 193 #address-cells = <1>;
182 #size-cells = <0>; 194 #size-cells = <0>;
183 cell-index = <1>; 195 cell-index = <1>;
184 compatible = "abilis,t 196 compatible = "abilis,tb100-spi";
185 num-cs = <2>; 197 num-cs = <2>;
186 reg = <0xfe011000 0x20 !! 198 reg = <0xFE011000 0x20>;
187 interrupt-parent = <&t 199 interrupt-parent = <&tb10x_ictl>;
188 interrupts = <10 8>; 200 interrupts = <10 8>;
189 clocks = <&ahb_clk>; 201 clocks = <&ahb_clk>;
190 }; 202 };
191 203
192 tb10x_tsm: tb10x-tsm@ff316000 204 tb10x_tsm: tb10x-tsm@ff316000 {
193 compatible = "abilis,t 205 compatible = "abilis,tb100-tsm";
194 reg = <0xff316000 0x40 206 reg = <0xff316000 0x400>;
195 interrupt-parent = <&t 207 interrupt-parent = <&tb10x_ictl>;
196 interrupts = <17 8>; 208 interrupts = <17 8>;
197 output-clkdiv = <4>; 209 output-clkdiv = <4>;
198 global-packet-delay = 210 global-packet-delay = <0x21>;
199 port-packet-delay = <0 211 port-packet-delay = <0>;
200 }; 212 };
201 tb10x_stream_proc: tb10x-strea 213 tb10x_stream_proc: tb10x-stream-proc {
202 compatible = "abilis,t 214 compatible = "abilis,tb100-streamproc";
203 reg = <0xfff00000 0x 215 reg = <0xfff00000 0x200>,
204 <0x000f0000 0x 216 <0x000f0000 0x10000>,
205 <0xfff00200 0x 217 <0xfff00200 0x105>,
206 <0xff10600c 0x 218 <0xff10600c 0x1>,
207 <0xfe001018 0x 219 <0xfe001018 0x1>;
208 reg-names = "mbox" 220 reg-names = "mbox",
209 "sp_ic 221 "sp_iccm",
210 "mbox_ 222 "mbox_irq",
211 "cpuct 223 "cpuctrl",
212 "a6it_ 224 "a6it_int_force";
213 interrupt-parent = <&t 225 interrupt-parent = <&tb10x_ictl>;
214 interrupts = <20 2>, < 226 interrupts = <20 2>, <19 2>;
215 interrupt-names = "cmd 227 interrupt-names = "cmd_irq", "event_irq";
216 }; 228 };
217 tb10x_mdsc0: tb10x-mdscr@ff300 !! 229 tb10x_mdsc0: tb10x-mdscr@FF300000 {
218 compatible = "abilis,t 230 compatible = "abilis,tb100-mdscr";
219 reg = <0xff300000 0x70 !! 231 reg = <0xFF300000 0x7000>;
220 tb100-mdscr-manage-tsi 232 tb100-mdscr-manage-tsin;
221 }; 233 };
222 tb10x_mscr0: tb10x-mdscr@ff307 !! 234 tb10x_mscr0: tb10x-mdscr@FF307000 {
223 compatible = "abilis,t 235 compatible = "abilis,tb100-mdscr";
224 reg = <0xff307000 0x70 !! 236 reg = <0xFF307000 0x7000>;
225 }; 237 };
226 tb10x_scr0: tb10x-mdscr@ff30e0 238 tb10x_scr0: tb10x-mdscr@ff30e000 {
227 compatible = "abilis,t 239 compatible = "abilis,tb100-mdscr";
228 reg = <0xff30e000 0x40 !! 240 reg = <0xFF30e000 0x4000>;
229 tb100-mdscr-manage-tsi 241 tb100-mdscr-manage-tsin;
230 }; 242 };
231 tb10x_scr1: tb10x-mdscr@ff3120 243 tb10x_scr1: tb10x-mdscr@ff312000 {
232 compatible = "abilis,t 244 compatible = "abilis,tb100-mdscr";
233 reg = <0xff312000 0x40 !! 245 reg = <0xFF312000 0x4000>;
234 tb100-mdscr-manage-tsi 246 tb100-mdscr-manage-tsin;
235 }; 247 };
236 tb10x_wfb: tb10x-wfb@ff319000 248 tb10x_wfb: tb10x-wfb@ff319000 {
237 compatible = "abilis,t 249 compatible = "abilis,tb100-wfb";
238 reg = <0xff319000 0x10 250 reg = <0xff319000 0x1000>;
239 interrupt-parent = <&t 251 interrupt-parent = <&tb10x_ictl>;
240 interrupts = <16 8>; 252 interrupts = <16 8>;
241 }; 253 };
242 }; 254 };
243 }; 255 };
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