1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.s 2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 8
6 /* 9 /*
7 * Device tree for AXC001 770D/EM6/AS221 CPU c 10 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D 11 * Note that this file only supports the 770D CPU
9 */ 12 */
10 13
11 /include/ "skeleton.dtsi" 14 /include/ "skeleton.dtsi"
12 15
13 / { 16 / {
14 compatible = "snps,arc"; 17 compatible = "snps,arc";
15 #address-cells = <2>; 18 #address-cells = <2>;
16 #size-cells = <2>; 19 #size-cells = <2>;
17 20
18 cpu_card { 21 cpu_card {
19 compatible = "simple-bus"; 22 compatible = "simple-bus";
20 #address-cells = <1>; 23 #address-cells = <1>;
21 #size-cells = <1>; 24 #size-cells = <1>;
22 25
23 ranges = <0x00000000 0x0 0xf00 26 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
24 27
25 core_clk: core_clk { 28 core_clk: core_clk {
26 #clock-cells = <0>; 29 #clock-cells = <0>;
27 compatible = "fixed-cl 30 compatible = "fixed-clock";
28 clock-frequency = <750 31 clock-frequency = <750000000>;
29 }; 32 };
30 33
31 input_clk: input-clk { <<
32 #clock-cells = <0>; <<
33 compatible = "fixed-cl <<
34 clock-frequency = <333 <<
35 }; <<
36 <<
37 core_intc: arc700-intc@cpu { 34 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc 35 compatible = "snps,arc700-intc";
39 interrupt-controller; 36 interrupt-controller;
40 #interrupt-cells = <1> 37 #interrupt-cells = <1>;
41 }; 38 };
42 39
43 /* 40 /*
44 * this GPIO block ORs all int 41 * this GPIO block ORs all interrupts on CPU card (creg,..)
45 * to uplink only 1 IRQ to ARC 42 * to uplink only 1 IRQ to ARC core intc
46 */ 43 */
47 dw-apb-gpio@2000 { !! 44 dw-apb-gpio@0x2000 {
48 compatible = "snps,dw- 45 compatible = "snps,dw-apb-gpio";
49 reg = < 0x2000 0x80 >; 46 reg = < 0x2000 0x80 >;
50 #address-cells = <1>; 47 #address-cells = <1>;
51 #size-cells = <0>; 48 #size-cells = <0>;
52 49
53 ictl_intc: gpio-contro 50 ictl_intc: gpio-controller@0 {
54 compatible = " 51 compatible = "snps,dw-apb-gpio-port";
55 gpio-controlle 52 gpio-controller;
56 #gpio-cells = 53 #gpio-cells = <2>;
57 snps,nr-gpios 54 snps,nr-gpios = <30>;
58 reg = <0>; 55 reg = <0>;
59 interrupt-cont 56 interrupt-controller;
60 #interrupt-cel 57 #interrupt-cells = <2>;
61 interrupt-pare 58 interrupt-parent = <&core_intc>;
62 interrupts = < 59 interrupts = <15>;
63 }; 60 };
64 }; 61 };
65 62
66 debug_uart: dw-apb-uart@5000 { !! 63 debug_uart: dw-apb-uart@0x5000 {
67 compatible = "snps,dw- 64 compatible = "snps,dw-apb-uart";
68 reg = <0x5000 0x100>; 65 reg = <0x5000 0x100>;
69 clock-frequency = <333 66 clock-frequency = <33333000>;
70 interrupt-parent = <&i 67 interrupt-parent = <&ictl_intc>;
71 interrupts = <19 4>; 68 interrupts = <19 4>;
72 baud = <115200>; 69 baud = <115200>;
73 reg-shift = <2>; 70 reg-shift = <2>;
74 reg-io-width = <4>; 71 reg-io-width = <4>;
75 }; 72 };
76 73
77 arcpct0: pct { 74 arcpct0: pct {
78 compatible = "snps,arc 75 compatible = "snps,arc700-pct";
79 }; 76 };
80 }; 77 };
81 78
82 /* 79 /*
83 * This INTC is actually connected to 80 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INT 81 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform 82 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection 83 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = 84 * CPU INTC, thus we set "interrupts = <7>" instead of
88 * "interrupts = <12>" 85 * "interrupts = <12>"
89 * 86 *
90 * This intc actually resides on MB, b 87 * This intc actually resides on MB, but we move it here to
91 * avoid duplicating the MB dtsi file 88 * avoid duplicating the MB dtsi file given that IRQ from
92 * this intc to cpu intc are different 89 * this intc to cpu intc are different for axs101 and axs103
93 */ 90 */
94 mb_intc: interrupt-controller@e0012000 !! 91 mb_intc: dw-apb-ictl@0xe0012000 {
95 #interrupt-cells = <1>; 92 #interrupt-cells = <1>;
96 compatible = "snps,dw-apb-ictl 93 compatible = "snps,dw-apb-ictl";
97 reg = < 0x0 0xe0012000 0x0 0x2 94 reg = < 0x0 0xe0012000 0x0 0x200 >;
98 interrupt-controller; 95 interrupt-controller;
99 interrupt-parent = <&core_intc 96 interrupt-parent = <&core_intc>;
100 interrupts = < 7 >; 97 interrupts = < 7 >;
101 }; 98 };
102 99
103 memory { 100 memory {
104 device_type = "memory"; 101 device_type = "memory";
105 /* CONFIG_LINUX_RAM_BASE needs 102 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
106 reg = <0x0 0x80000000 0x0 0x1b 103 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
107 }; 104 };
108 105
109 reserved-memory { 106 reserved-memory {
110 #address-cells = <2>; 107 #address-cells = <2>;
111 #size-cells = <2>; 108 #size-cells = <2>;
112 ranges; 109 ranges;
113 /* 110 /*
114 * We just move frame buffer a 111 * We just move frame buffer area to the very end of
115 * available DDR. And even tho 112 * available DDR. And even though in case of ARC770 there's
116 * no strict requirement for a 113 * no strict requirement for a frame-buffer to be in any
117 * particular location it allo 114 * particular location it allows us to use the same
118 * base board's DT node for AR 115 * base board's DT node for ARC PGU as for ARc HS38.
119 */ 116 */
120 frame_buffer: frame_buffer@9e0 117 frame_buffer: frame_buffer@9e000000 {
121 compatible = "shared-d 118 compatible = "shared-dma-pool";
122 reg = <0x0 0x9e000000 119 reg = <0x0 0x9e000000 0x0 0x2000000>;
123 no-map; 120 no-map;
124 }; 121 };
125 }; 122 };
126 }; 123 };
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