1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.s 3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
4 */ 4 */
5 5
6 /* 6 /*
7 * Device tree for AXC001 770D/EM6/AS221 CPU c 7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D 8 * Note that this file only supports the 770D CPU
9 */ 9 */
10 10
11 /include/ "skeleton.dtsi" 11 /include/ "skeleton.dtsi"
12 12
13 / { 13 / {
14 compatible = "snps,arc"; 14 compatible = "snps,arc";
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 cpu_card { 18 cpu_card {
19 compatible = "simple-bus"; 19 compatible = "simple-bus";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 22
23 ranges = <0x00000000 0x0 0xf00 23 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
24 24
25 core_clk: core_clk { 25 core_clk: core_clk {
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 compatible = "fixed-cl 27 compatible = "fixed-clock";
28 clock-frequency = <750 28 clock-frequency = <750000000>;
29 }; 29 };
30 30
31 input_clk: input-clk { <<
32 #clock-cells = <0>; <<
33 compatible = "fixed-cl <<
34 clock-frequency = <333 <<
35 }; <<
36 <<
37 core_intc: arc700-intc@cpu { 31 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc 32 compatible = "snps,arc700-intc";
39 interrupt-controller; 33 interrupt-controller;
40 #interrupt-cells = <1> 34 #interrupt-cells = <1>;
41 }; 35 };
42 36
43 /* 37 /*
44 * this GPIO block ORs all int 38 * this GPIO block ORs all interrupts on CPU card (creg,..)
45 * to uplink only 1 IRQ to ARC 39 * to uplink only 1 IRQ to ARC core intc
46 */ 40 */
47 dw-apb-gpio@2000 { 41 dw-apb-gpio@2000 {
48 compatible = "snps,dw- 42 compatible = "snps,dw-apb-gpio";
49 reg = < 0x2000 0x80 >; 43 reg = < 0x2000 0x80 >;
50 #address-cells = <1>; 44 #address-cells = <1>;
51 #size-cells = <0>; 45 #size-cells = <0>;
52 46
53 ictl_intc: gpio-contro 47 ictl_intc: gpio-controller@0 {
54 compatible = " 48 compatible = "snps,dw-apb-gpio-port";
55 gpio-controlle 49 gpio-controller;
56 #gpio-cells = 50 #gpio-cells = <2>;
57 snps,nr-gpios 51 snps,nr-gpios = <30>;
58 reg = <0>; 52 reg = <0>;
59 interrupt-cont 53 interrupt-controller;
60 #interrupt-cel 54 #interrupt-cells = <2>;
61 interrupt-pare 55 interrupt-parent = <&core_intc>;
62 interrupts = < 56 interrupts = <15>;
63 }; 57 };
64 }; 58 };
65 59
66 debug_uart: dw-apb-uart@5000 { 60 debug_uart: dw-apb-uart@5000 {
67 compatible = "snps,dw- 61 compatible = "snps,dw-apb-uart";
68 reg = <0x5000 0x100>; 62 reg = <0x5000 0x100>;
69 clock-frequency = <333 63 clock-frequency = <33333000>;
70 interrupt-parent = <&i 64 interrupt-parent = <&ictl_intc>;
71 interrupts = <19 4>; 65 interrupts = <19 4>;
72 baud = <115200>; 66 baud = <115200>;
73 reg-shift = <2>; 67 reg-shift = <2>;
74 reg-io-width = <4>; 68 reg-io-width = <4>;
75 }; 69 };
76 70
77 arcpct0: pct { 71 arcpct0: pct {
78 compatible = "snps,arc 72 compatible = "snps,arc700-pct";
79 }; 73 };
80 }; 74 };
81 75
82 /* 76 /*
83 * This INTC is actually connected to 77 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INT 78 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform 79 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection 80 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = 81 * CPU INTC, thus we set "interrupts = <7>" instead of
88 * "interrupts = <12>" 82 * "interrupts = <12>"
89 * 83 *
90 * This intc actually resides on MB, b 84 * This intc actually resides on MB, but we move it here to
91 * avoid duplicating the MB dtsi file 85 * avoid duplicating the MB dtsi file given that IRQ from
92 * this intc to cpu intc are different 86 * this intc to cpu intc are different for axs101 and axs103
93 */ 87 */
94 mb_intc: interrupt-controller@e0012000 !! 88 mb_intc: dw-apb-ictl@e0012000 {
95 #interrupt-cells = <1>; 89 #interrupt-cells = <1>;
96 compatible = "snps,dw-apb-ictl 90 compatible = "snps,dw-apb-ictl";
97 reg = < 0x0 0xe0012000 0x0 0x2 91 reg = < 0x0 0xe0012000 0x0 0x200 >;
98 interrupt-controller; 92 interrupt-controller;
99 interrupt-parent = <&core_intc 93 interrupt-parent = <&core_intc>;
100 interrupts = < 7 >; 94 interrupts = < 7 >;
101 }; 95 };
102 96
103 memory { 97 memory {
104 device_type = "memory"; 98 device_type = "memory";
105 /* CONFIG_LINUX_RAM_BASE needs 99 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
106 reg = <0x0 0x80000000 0x0 0x1b 100 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
107 }; 101 };
108 102
109 reserved-memory { 103 reserved-memory {
110 #address-cells = <2>; 104 #address-cells = <2>;
111 #size-cells = <2>; 105 #size-cells = <2>;
112 ranges; 106 ranges;
113 /* 107 /*
114 * We just move frame buffer a 108 * We just move frame buffer area to the very end of
115 * available DDR. And even tho 109 * available DDR. And even though in case of ARC770 there's
116 * no strict requirement for a 110 * no strict requirement for a frame-buffer to be in any
117 * particular location it allo 111 * particular location it allows us to use the same
118 * base board's DT node for AR 112 * base board's DT node for ARC PGU as for ARc HS38.
119 */ 113 */
120 frame_buffer: frame_buffer@9e0 114 frame_buffer: frame_buffer@9e000000 {
121 compatible = "shared-d 115 compatible = "shared-dma-pool";
122 reg = <0x0 0x9e000000 116 reg = <0x0 0x9e000000 0x0 0x2000000>;
123 no-map; 117 no-map;
124 }; 118 };
125 }; 119 };
126 }; 120 };
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