1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www 3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
4 */ 4 */
5 /dts-v1/; 5 /dts-v1/;
6 6
7 /include/ "skeleton_hs_idu.dtsi" 7 /include/ "skeleton_hs_idu.dtsi"
8 8
9 / { 9 / {
10 model = "snps,zebu_hs-smp"; 10 model = "snps,zebu_hs-smp";
11 compatible = "snps,zebu_hs"; 11 compatible = "snps,zebu_hs";
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>; 14 interrupt-parent = <&core_intc>;
15 15
16 memory { 16 memory {
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x20000000>; 18 reg = <0x80000000 0x20000000>; /* 512 */
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 bootargs = "earlycon=uart8250, 22 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 }; 23 };
24 24
25 aliases { 25 aliases {
26 serial0 = &uart0; 26 serial0 = &uart0;
27 }; 27 };
28 28
29 fpga { 29 fpga {
30 compatible = "simple-bus"; 30 compatible = "simple-bus";
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <1>; 32 #size-cells = <1>;
33 33
34 /* child and parent address sp 34 /* child and parent address space 1:1 mapped */
35 ranges; 35 ranges;
36 36
37 core_clk: core_clk { 37 core_clk: core_clk {
38 #clock-cells = <0>; 38 #clock-cells = <0>;
39 compatible = "fixed-cl 39 compatible = "fixed-clock";
40 clock-frequency = <500 40 clock-frequency = <50000000>; /* 50 MHZ */
41 }; 41 };
42 42
43 core_intc: interrupt-controlle 43 core_intc: interrupt-controller {
44 compatible = "snps,arc 44 compatible = "snps,archs-intc";
45 interrupt-controller; 45 interrupt-controller;
46 #interrupt-cells = <1> 46 #interrupt-cells = <1>;
47 }; 47 };
48 48
49 idu_intc: idu-interrupt-contro 49 idu_intc: idu-interrupt-controller {
50 compatible = "snps,arc 50 compatible = "snps,archs-idu-intc";
51 interrupt-controller; 51 interrupt-controller;
52 interrupt-parent = <&c 52 interrupt-parent = <&core_intc>;
53 #interrupt-cells = <1> 53 #interrupt-cells = <1>;
54 }; 54 };
55 55
56 uart0: serial@f0000000 { 56 uart0: serial@f0000000 {
57 compatible = "ns16550a 57 compatible = "ns16550a";
58 reg = <0xf0000000 0x20 58 reg = <0xf0000000 0x2000>;
59 interrupt-parent = <&i 59 interrupt-parent = <&idu_intc>;
60 interrupts = <0>; 60 interrupts = <0>;
61 clock-frequency = <500 61 clock-frequency = <50000000>;
62 baud = <115200>; 62 baud = <115200>;
63 reg-shift = <2>; 63 reg-shift = <2>;
64 reg-io-width = <4>; 64 reg-io-width = <4>;
65 no-loopback-test = <1> 65 no-loopback-test = <1>;
66 }; 66 };
67 67
68 arcpct0: pct { 68 arcpct0: pct {
69 compatible = "snps,arc 69 compatible = "snps,archs-pct";
70 #interrupt-cells = <1> 70 #interrupt-cells = <1>;
71 interrupts = <20>; 71 interrupts = <20>;
72 }; 72 };
73 }; 73 };
74 }; 74 };
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