1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2017 Synopsys, Inc. (www.syno 2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 8
6 /* 9 /*
7 * Device Tree for ARC HS Development Kit 10 * Device Tree for ARC HS Development Kit
8 */ 11 */
9 /dts-v1/; 12 /dts-v1/;
10 13
11 #include <dt-bindings/gpio/gpio.h> !! 14 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h> 15 #include <dt-bindings/reset/snps,hsdk-reset.h>
13 16
14 / { 17 / {
15 model = "snps,hsdk"; 18 model = "snps,hsdk";
16 compatible = "snps,hsdk"; 19 compatible = "snps,hsdk";
17 20
18 #address-cells = <2>; !! 21 #address-cells = <1>;
19 #size-cells = <2>; !! 22 #size-cells = <1>;
20 23
21 chosen { 24 chosen {
22 bootargs = "earlycon=uart8250, 25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 }; 26 };
24 27
25 aliases { <<
26 ethernet = &gmac; <<
27 }; <<
28 <<
29 cpus { 28 cpus {
30 #address-cells = <1>; 29 #address-cells = <1>;
31 #size-cells = <0>; 30 #size-cells = <0>;
32 31
33 cpu@0 { 32 cpu@0 {
34 device_type = "cpu"; 33 device_type = "cpu";
35 compatible = "snps,arc 34 compatible = "snps,archs38";
36 reg = <0>; 35 reg = <0>;
37 clocks = <&core_clk>; 36 clocks = <&core_clk>;
38 }; 37 };
39 38
40 cpu@1 { 39 cpu@1 {
41 device_type = "cpu"; 40 device_type = "cpu";
42 compatible = "snps,arc 41 compatible = "snps,archs38";
43 reg = <1>; 42 reg = <1>;
44 clocks = <&core_clk>; 43 clocks = <&core_clk>;
45 }; 44 };
46 45
47 cpu@2 { 46 cpu@2 {
48 device_type = "cpu"; 47 device_type = "cpu";
49 compatible = "snps,arc 48 compatible = "snps,archs38";
50 reg = <2>; 49 reg = <2>;
51 clocks = <&core_clk>; 50 clocks = <&core_clk>;
52 }; 51 };
53 52
54 cpu@3 { 53 cpu@3 {
55 device_type = "cpu"; 54 device_type = "cpu";
56 compatible = "snps,arc 55 compatible = "snps,archs38";
57 reg = <3>; 56 reg = <3>;
58 clocks = <&core_clk>; 57 clocks = <&core_clk>;
59 }; 58 };
60 }; 59 };
61 60
62 input_clk: input-clk { 61 input_clk: input-clk {
63 #clock-cells = <0>; 62 #clock-cells = <0>;
64 compatible = "fixed-clock"; 63 compatible = "fixed-clock";
65 clock-frequency = <33333333>; 64 clock-frequency = <33333333>;
66 }; 65 };
67 66
68 reg_5v0: regulator-5v0 { <<
69 compatible = "regulator-fixed" <<
70 <<
71 regulator-name = "5v0-supply"; <<
72 regulator-min-microvolt = <500 <<
73 regulator-max-microvolt = <500 <<
74 }; <<
75 <<
76 cpu_intc: cpu-interrupt-controller { 67 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc" 68 compatible = "snps,archs-intc";
78 interrupt-controller; 69 interrupt-controller;
79 #interrupt-cells = <1>; 70 #interrupt-cells = <1>;
80 }; 71 };
81 72
82 idu_intc: idu-interrupt-controller { 73 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-i 74 compatible = "snps,archs-idu-intc";
84 interrupt-controller; 75 interrupt-controller;
85 #interrupt-cells = <1>; 76 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc> 77 interrupt-parent = <&cpu_intc>;
87 }; 78 };
88 79
89 arcpct: pct { 80 arcpct: pct {
90 compatible = "snps,archs-pct"; 81 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc> <<
92 interrupts = <20>; <<
93 }; 82 };
94 83
95 /* TIMER0 with interrupt for clockeven 84 /* TIMER0 with interrupt for clockevent */
96 timer { 85 timer {
97 compatible = "snps,arc-timer"; 86 compatible = "snps,arc-timer";
98 interrupts = <16>; 87 interrupts = <16>;
99 interrupt-parent = <&cpu_intc> 88 interrupt-parent = <&cpu_intc>;
100 clocks = <&core_clk>; 89 clocks = <&core_clk>;
101 }; 90 };
102 91
103 /* 64-bit Global Free Running Counter 92 /* 64-bit Global Free Running Counter */
104 gfrc { 93 gfrc {
105 compatible = "snps,archs-timer 94 compatible = "snps,archs-timer-gfrc";
106 clocks = <&core_clk>; 95 clocks = <&core_clk>;
107 }; 96 };
108 97
109 soc { 98 soc {
110 compatible = "simple-bus"; 99 compatible = "simple-bus";
111 #address-cells = <1>; 100 #address-cells = <1>;
112 #size-cells = <1>; 101 #size-cells = <1>;
113 interrupt-parent = <&idu_intc> 102 interrupt-parent = <&idu_intc>;
114 103
115 ranges = <0x00000000 0x0 0xf00 !! 104 ranges = <0x00000000 0xf0000000 0x10000000>;
116 105
117 cgu_rst: reset-controller@8a0 106 cgu_rst: reset-controller@8a0 {
118 compatible = "snps,hsd 107 compatible = "snps,hsdk-reset";
119 #reset-cells = <1>; 108 #reset-cells = <1>;
120 reg = <0x8a0 0x4>, <0x !! 109 reg = <0x8A0 0x4>, <0xFF0 0x4>;
121 }; 110 };
122 111
123 core_clk: core-clk@0 { 112 core_clk: core-clk@0 {
124 compatible = "snps,hsd 113 compatible = "snps,hsdk-core-pll-clock";
125 reg = <0x00 0x10>, <0x !! 114 reg = <0x00 0x10>, <0x14B8 0x4>;
126 #clock-cells = <0>; 115 #clock-cells = <0>;
127 clocks = <&input_clk>; 116 clocks = <&input_clk>;
128 117
129 /* 118 /*
130 * Set initial core pl 119 * Set initial core pll output frequency to 1GHz.
131 * It will be applied 120 * It will be applied at the core pll driver probing
132 * on early boot. 121 * on early boot.
133 */ 122 */
134 assigned-clocks = <&co 123 assigned-clocks = <&core_clk>;
135 assigned-clock-rates = 124 assigned-clock-rates = <1000000000>;
136 }; 125 };
137 126
138 serial: serial@5000 { 127 serial: serial@5000 {
139 compatible = "snps,dw- 128 compatible = "snps,dw-apb-uart";
140 reg = <0x5000 0x100>; 129 reg = <0x5000 0x100>;
141 clock-frequency = <333 130 clock-frequency = <33330000>;
142 interrupts = <6>; 131 interrupts = <6>;
143 baud = <115200>; 132 baud = <115200>;
144 reg-shift = <2>; 133 reg-shift = <2>;
145 reg-io-width = <4>; 134 reg-io-width = <4>;
146 }; 135 };
147 136
148 gmacclk: gmacclk { 137 gmacclk: gmacclk {
149 compatible = "fixed-cl 138 compatible = "fixed-clock";
150 clock-frequency = <400 139 clock-frequency = <400000000>;
151 #clock-cells = <0>; 140 #clock-cells = <0>;
152 }; 141 };
153 142
154 mmcclk_ciu: mmcclk-ciu { 143 mmcclk_ciu: mmcclk-ciu {
155 compatible = "fixed-cl 144 compatible = "fixed-clock";
156 /* 145 /*
157 * DW sdio controller 146 * DW sdio controller has external ciu clock divider
158 * controlled via regi 147 * controlled via register in SDIO IP. Due to its
159 * unexpected default 148 * unexpected default value (it should divide by 1
160 * but it divides by 8 149 * but it divides by 8) SDIO IP uses wrong clock and
161 * works unstable (see 150 * works unstable (see STAR 9001204800)
162 * We switched to the 151 * We switched to the minimum possible value of the
163 * divisor (div-by-2) 152 * divisor (div-by-2) in HSDK platform code.
164 * So add temporary fi 153 * So add temporary fix and change clock frequency
165 * to 50000000 Hz unti 154 * to 50000000 Hz until we fix dw sdio driver itself.
166 */ 155 */
167 clock-frequency = <500 156 clock-frequency = <50000000>;
168 #clock-cells = <0>; 157 #clock-cells = <0>;
169 }; 158 };
170 159
171 mmcclk_biu: mmcclk-biu { 160 mmcclk_biu: mmcclk-biu {
172 compatible = "fixed-cl 161 compatible = "fixed-clock";
173 clock-frequency = <400 162 clock-frequency = <400000000>;
174 #clock-cells = <0>; 163 #clock-cells = <0>;
175 }; 164 };
176 165
177 gpu_core_clk: gpu-core-clk { !! 166 ethernet@8000 {
178 compatible = "fixed-cl !! 167 #interrupt-cells = <1>;
179 clock-frequency = <400 <<
180 #clock-cells = <0>; <<
181 }; <<
182 <<
183 gpu_dma_clk: gpu-dma-clk { <<
184 compatible = "fixed-cl <<
185 clock-frequency = <400 <<
186 #clock-cells = <0>; <<
187 }; <<
188 <<
189 gpu_cfg_clk: gpu-cfg-clk { <<
190 compatible = "fixed-cl <<
191 clock-frequency = <200 <<
192 #clock-cells = <0>; <<
193 }; <<
194 <<
195 dmac_core_clk: dmac-core-clk { <<
196 compatible = "fixed-cl <<
197 clock-frequency = <400 <<
198 #clock-cells = <0>; <<
199 }; <<
200 <<
201 dmac_cfg_clk: dmac-gpu-cfg-clk <<
202 compatible = "fixed-cl <<
203 clock-frequency = <200 <<
204 #clock-cells = <0>; <<
205 }; <<
206 <<
207 gmac: ethernet@8000 { <<
208 compatible = "snps,dwm 168 compatible = "snps,dwmac";
209 reg = <0x8000 0x2000>; 169 reg = <0x8000 0x2000>;
210 interrupts = <10>; 170 interrupts = <10>;
211 interrupt-names = "mac 171 interrupt-names = "macirq";
212 phy-mode = "rgmii-id"; !! 172 phy-mode = "rgmii";
213 snps,pbl = <32>; 173 snps,pbl = <32>;
214 snps,multicast-filter- <<
215 clocks = <&gmacclk>; 174 clocks = <&gmacclk>;
216 clock-names = "stmmace 175 clock-names = "stmmaceth";
217 phy-handle = <&phy0>; 176 phy-handle = <&phy0>;
218 resets = <&cgu_rst HSD 177 resets = <&cgu_rst HSDK_ETH_RESET>;
219 reset-names = "stmmace 178 reset-names = "stmmaceth";
220 mac-address = [00 00 0 <<
221 dma-coherent; <<
222 <<
223 tx-fifo-depth = <4096> <<
224 rx-fifo-depth = <4096> <<
225 179
226 mdio { 180 mdio {
227 #address-cells 181 #address-cells = <1>;
228 #size-cells = 182 #size-cells = <0>;
229 compatible = " 183 compatible = "snps,dwmac-mdio";
230 phy0: ethernet !! 184 phy0: ethernet-phy@0 {
231 reg = 185 reg = <0>;
>> 186 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> 187 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> 188 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
232 }; 189 };
233 }; 190 };
234 }; 191 };
235 192
236 usb@60000 { !! 193 ohci@60000 {
237 compatible = "snps,hsd 194 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
238 reg = <0x60000 0x100>; 195 reg = <0x60000 0x100>;
239 interrupts = <15>; 196 interrupts = <15>;
240 resets = <&cgu_rst HSD <<
241 dma-coherent; <<
242 }; 197 };
243 198
244 usb@40000 { !! 199 ehci@40000 {
245 compatible = "snps,hsd 200 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
246 reg = <0x40000 0x100>; 201 reg = <0x40000 0x100>;
247 interrupts = <15>; 202 interrupts = <15>;
248 resets = <&cgu_rst HSD <<
249 dma-coherent; <<
250 }; 203 };
251 204
252 mmc@a000 { 205 mmc@a000 {
253 compatible = "altr,soc 206 compatible = "altr,socfpga-dw-mshc";
254 reg = <0xa000 0x400>; 207 reg = <0xa000 0x400>;
255 num-slots = <1>; 208 num-slots = <1>;
256 fifo-depth = <16>; 209 fifo-depth = <16>;
257 card-detect-delay = <2 210 card-detect-delay = <200>;
258 clocks = <&mmcclk_biu> 211 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
259 clock-names = "biu", " 212 clock-names = "biu", "ciu";
260 interrupts = <12>; 213 interrupts = <12>;
261 bus-width = <4>; 214 bus-width = <4>;
262 dma-coherent; <<
263 }; <<
264 <<
265 spi0: spi@20000 { <<
266 compatible = "snps,dw- <<
267 reg = <0x20000 0x100>; <<
268 #address-cells = <1>; <<
269 #size-cells = <0>; <<
270 interrupts = <16>; <<
271 num-cs = <2>; <<
272 reg-io-width = <4>; <<
273 clocks = <&input_clk>; <<
274 cs-gpios = <&creg_gpio <<
275 <&creg_gpio <<
276 <<
277 flash@0 { <<
278 compatible = " <<
279 reg = <0>; <<
280 #address-cells <<
281 #size-cells = <<
282 spi-max-freque <<
283 }; <<
284 <<
285 adc@1 { <<
286 compatible = " <<
287 reg = <1>; <<
288 vref-supply = <<
289 spi-max-freque <<
290 }; <<
291 }; <<
292 <<
293 creg_gpio: gpio@14b0 { <<
294 compatible = "snps,cre <<
295 reg = <0x14b0 0x4>; <<
296 gpio-controller; <<
297 #gpio-cells = <2>; <<
298 ngpios = <2>; <<
299 }; <<
300 <<
301 gpio: gpio@3000 { <<
302 compatible = "snps,dw- <<
303 reg = <0x3000 0x20>; <<
304 #address-cells = <1>; <<
305 #size-cells = <0>; <<
306 <<
307 gpio_port_a: gpio-cont <<
308 compatible = " <<
309 gpio-controlle <<
310 #gpio-cells = <<
311 snps,nr-gpios <<
312 reg = <0>; <<
313 }; <<
314 }; <<
315 <<
316 gpu_3d: gpu@90000 { <<
317 compatible = "vivante, <<
318 reg = <0x90000 0x4000> <<
319 clocks = <&gpu_dma_clk <<
320 <&gpu_cfg_clk <<
321 <&gpu_core_cl <<
322 <&gpu_core_cl <<
323 clock-names = "bus", " <<
324 interrupts = <28>; <<
325 }; <<
326 <<
327 dmac: dmac@80000 { <<
328 compatible = "snps,axi <<
329 reg = <0x80000 0x400>; <<
330 interrupts = <27>; <<
331 clocks = <&dmac_core_c <<
332 clock-names = "core-cl <<
333 <<
334 dma-channels = <4>; <<
335 snps,dma-masters = <2> <<
336 snps,data-width = <3>; <<
337 snps,block-size = <409 <<
338 snps,priority = <0 1 2 <<
339 snps,axi-max-burst-len <<
340 }; 215 };
341 }; 216 };
342 217
343 memory@80000000 { 218 memory@80000000 {
344 #address-cells = <2>; !! 219 #address-cells = <1>;
345 #size-cells = <2>; !! 220 #size-cells = <1>;
346 device_type = "memory"; 221 device_type = "memory";
347 reg = <0x0 0x80000000 0x0 0x40 !! 222 reg = <0x80000000 0x40000000>; /* 1 GiB */
348 /* 0x1 0x00000000 0x0 0x40 <<
349 }; 223 };
350 }; 224 };
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