1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2017 Synopsys, Inc. (www.syno 2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 8
6 /* 9 /*
7 * Device Tree for ARC HS Development Kit 10 * Device Tree for ARC HS Development Kit
8 */ 11 */
9 /dts-v1/; 12 /dts-v1/;
10 13
11 #include <dt-bindings/gpio/gpio.h> !! 14 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h> 15 #include <dt-bindings/reset/snps,hsdk-reset.h>
13 16
14 / { 17 / {
15 model = "snps,hsdk"; 18 model = "snps,hsdk";
16 compatible = "snps,hsdk"; 19 compatible = "snps,hsdk";
17 20
18 #address-cells = <2>; 21 #address-cells = <2>;
19 #size-cells = <2>; 22 #size-cells = <2>;
20 23
21 chosen { 24 chosen {
22 bootargs = "earlycon=uart8250, 25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 }; 26 };
24 27
25 aliases { 28 aliases {
26 ethernet = &gmac; 29 ethernet = &gmac;
27 }; 30 };
28 31
29 cpus { 32 cpus {
30 #address-cells = <1>; 33 #address-cells = <1>;
31 #size-cells = <0>; 34 #size-cells = <0>;
32 35
33 cpu@0 { 36 cpu@0 {
34 device_type = "cpu"; 37 device_type = "cpu";
35 compatible = "snps,arc 38 compatible = "snps,archs38";
36 reg = <0>; 39 reg = <0>;
37 clocks = <&core_clk>; 40 clocks = <&core_clk>;
38 }; 41 };
39 42
40 cpu@1 { 43 cpu@1 {
41 device_type = "cpu"; 44 device_type = "cpu";
42 compatible = "snps,arc 45 compatible = "snps,archs38";
43 reg = <1>; 46 reg = <1>;
44 clocks = <&core_clk>; 47 clocks = <&core_clk>;
45 }; 48 };
46 49
47 cpu@2 { 50 cpu@2 {
48 device_type = "cpu"; 51 device_type = "cpu";
49 compatible = "snps,arc 52 compatible = "snps,archs38";
50 reg = <2>; 53 reg = <2>;
51 clocks = <&core_clk>; 54 clocks = <&core_clk>;
52 }; 55 };
53 56
54 cpu@3 { 57 cpu@3 {
55 device_type = "cpu"; 58 device_type = "cpu";
56 compatible = "snps,arc 59 compatible = "snps,archs38";
57 reg = <3>; 60 reg = <3>;
58 clocks = <&core_clk>; 61 clocks = <&core_clk>;
59 }; 62 };
60 }; 63 };
61 64
62 input_clk: input-clk { 65 input_clk: input-clk {
63 #clock-cells = <0>; 66 #clock-cells = <0>;
64 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
65 clock-frequency = <33333333>; 68 clock-frequency = <33333333>;
66 }; 69 };
67 70
68 reg_5v0: regulator-5v0 { <<
69 compatible = "regulator-fixed" <<
70 <<
71 regulator-name = "5v0-supply"; <<
72 regulator-min-microvolt = <500 <<
73 regulator-max-microvolt = <500 <<
74 }; <<
75 <<
76 cpu_intc: cpu-interrupt-controller { 71 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc" 72 compatible = "snps,archs-intc";
78 interrupt-controller; 73 interrupt-controller;
79 #interrupt-cells = <1>; 74 #interrupt-cells = <1>;
80 }; 75 };
81 76
82 idu_intc: idu-interrupt-controller { 77 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-i 78 compatible = "snps,archs-idu-intc";
84 interrupt-controller; 79 interrupt-controller;
85 #interrupt-cells = <1>; 80 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc> 81 interrupt-parent = <&cpu_intc>;
87 }; 82 };
88 83
89 arcpct: pct { 84 arcpct: pct {
90 compatible = "snps,archs-pct"; 85 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc> <<
92 interrupts = <20>; <<
93 }; 86 };
94 87
95 /* TIMER0 with interrupt for clockeven 88 /* TIMER0 with interrupt for clockevent */
96 timer { 89 timer {
97 compatible = "snps,arc-timer"; 90 compatible = "snps,arc-timer";
98 interrupts = <16>; 91 interrupts = <16>;
99 interrupt-parent = <&cpu_intc> 92 interrupt-parent = <&cpu_intc>;
100 clocks = <&core_clk>; 93 clocks = <&core_clk>;
101 }; 94 };
102 95
103 /* 64-bit Global Free Running Counter 96 /* 64-bit Global Free Running Counter */
104 gfrc { 97 gfrc {
105 compatible = "snps,archs-timer 98 compatible = "snps,archs-timer-gfrc";
106 clocks = <&core_clk>; 99 clocks = <&core_clk>;
107 }; 100 };
108 101
109 soc { 102 soc {
110 compatible = "simple-bus"; 103 compatible = "simple-bus";
111 #address-cells = <1>; 104 #address-cells = <1>;
112 #size-cells = <1>; 105 #size-cells = <1>;
113 interrupt-parent = <&idu_intc> 106 interrupt-parent = <&idu_intc>;
114 107
115 ranges = <0x00000000 0x0 0xf00 108 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
116 109
117 cgu_rst: reset-controller@8a0 110 cgu_rst: reset-controller@8a0 {
118 compatible = "snps,hsd 111 compatible = "snps,hsdk-reset";
119 #reset-cells = <1>; 112 #reset-cells = <1>;
120 reg = <0x8a0 0x4>, <0x 113 reg = <0x8a0 0x4>, <0xff0 0x4>;
121 }; 114 };
122 115
123 core_clk: core-clk@0 { 116 core_clk: core-clk@0 {
124 compatible = "snps,hsd 117 compatible = "snps,hsdk-core-pll-clock";
125 reg = <0x00 0x10>, <0x 118 reg = <0x00 0x10>, <0x14b8 0x4>;
126 #clock-cells = <0>; 119 #clock-cells = <0>;
127 clocks = <&input_clk>; 120 clocks = <&input_clk>;
128 121
129 /* 122 /*
130 * Set initial core pl 123 * Set initial core pll output frequency to 1GHz.
131 * It will be applied 124 * It will be applied at the core pll driver probing
132 * on early boot. 125 * on early boot.
133 */ 126 */
134 assigned-clocks = <&co 127 assigned-clocks = <&core_clk>;
135 assigned-clock-rates = 128 assigned-clock-rates = <1000000000>;
136 }; 129 };
137 130
138 serial: serial@5000 { 131 serial: serial@5000 {
139 compatible = "snps,dw- 132 compatible = "snps,dw-apb-uart";
140 reg = <0x5000 0x100>; 133 reg = <0x5000 0x100>;
141 clock-frequency = <333 134 clock-frequency = <33330000>;
142 interrupts = <6>; 135 interrupts = <6>;
143 baud = <115200>; 136 baud = <115200>;
144 reg-shift = <2>; 137 reg-shift = <2>;
145 reg-io-width = <4>; 138 reg-io-width = <4>;
146 }; 139 };
147 140
148 gmacclk: gmacclk { 141 gmacclk: gmacclk {
149 compatible = "fixed-cl 142 compatible = "fixed-clock";
150 clock-frequency = <400 143 clock-frequency = <400000000>;
151 #clock-cells = <0>; 144 #clock-cells = <0>;
152 }; 145 };
153 146
154 mmcclk_ciu: mmcclk-ciu { 147 mmcclk_ciu: mmcclk-ciu {
155 compatible = "fixed-cl 148 compatible = "fixed-clock";
156 /* 149 /*
157 * DW sdio controller 150 * DW sdio controller has external ciu clock divider
158 * controlled via regi 151 * controlled via register in SDIO IP. Due to its
159 * unexpected default 152 * unexpected default value (it should divide by 1
160 * but it divides by 8 153 * but it divides by 8) SDIO IP uses wrong clock and
161 * works unstable (see 154 * works unstable (see STAR 9001204800)
162 * We switched to the 155 * We switched to the minimum possible value of the
163 * divisor (div-by-2) 156 * divisor (div-by-2) in HSDK platform code.
164 * So add temporary fi 157 * So add temporary fix and change clock frequency
165 * to 50000000 Hz unti 158 * to 50000000 Hz until we fix dw sdio driver itself.
166 */ 159 */
167 clock-frequency = <500 160 clock-frequency = <50000000>;
168 #clock-cells = <0>; 161 #clock-cells = <0>;
169 }; 162 };
170 163
171 mmcclk_biu: mmcclk-biu { 164 mmcclk_biu: mmcclk-biu {
172 compatible = "fixed-cl 165 compatible = "fixed-clock";
173 clock-frequency = <400 166 clock-frequency = <400000000>;
174 #clock-cells = <0>; 167 #clock-cells = <0>;
175 }; 168 };
176 169
177 gpu_core_clk: gpu-core-clk { <<
178 compatible = "fixed-cl <<
179 clock-frequency = <400 <<
180 #clock-cells = <0>; <<
181 }; <<
182 <<
183 gpu_dma_clk: gpu-dma-clk { <<
184 compatible = "fixed-cl <<
185 clock-frequency = <400 <<
186 #clock-cells = <0>; <<
187 }; <<
188 <<
189 gpu_cfg_clk: gpu-cfg-clk { <<
190 compatible = "fixed-cl <<
191 clock-frequency = <200 <<
192 #clock-cells = <0>; <<
193 }; <<
194 <<
195 dmac_core_clk: dmac-core-clk { 170 dmac_core_clk: dmac-core-clk {
196 compatible = "fixed-cl 171 compatible = "fixed-clock";
197 clock-frequency = <400 172 clock-frequency = <400000000>;
198 #clock-cells = <0>; 173 #clock-cells = <0>;
199 }; 174 };
200 175
201 dmac_cfg_clk: dmac-gpu-cfg-clk 176 dmac_cfg_clk: dmac-gpu-cfg-clk {
202 compatible = "fixed-cl 177 compatible = "fixed-clock";
203 clock-frequency = <200 178 clock-frequency = <200000000>;
204 #clock-cells = <0>; 179 #clock-cells = <0>;
205 }; 180 };
206 181
207 gmac: ethernet@8000 { 182 gmac: ethernet@8000 {
>> 183 #interrupt-cells = <1>;
208 compatible = "snps,dwm 184 compatible = "snps,dwmac";
209 reg = <0x8000 0x2000>; 185 reg = <0x8000 0x2000>;
210 interrupts = <10>; 186 interrupts = <10>;
211 interrupt-names = "mac 187 interrupt-names = "macirq";
212 phy-mode = "rgmii-id"; !! 188 phy-mode = "rgmii";
213 snps,pbl = <32>; 189 snps,pbl = <32>;
214 snps,multicast-filter- 190 snps,multicast-filter-bins = <256>;
215 clocks = <&gmacclk>; 191 clocks = <&gmacclk>;
216 clock-names = "stmmace 192 clock-names = "stmmaceth";
217 phy-handle = <&phy0>; 193 phy-handle = <&phy0>;
218 resets = <&cgu_rst HSD 194 resets = <&cgu_rst HSDK_ETH_RESET>;
219 reset-names = "stmmace 195 reset-names = "stmmaceth";
220 mac-address = [00 00 0 196 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
221 dma-coherent; 197 dma-coherent;
222 198
223 tx-fifo-depth = <4096> 199 tx-fifo-depth = <4096>;
224 rx-fifo-depth = <4096> 200 rx-fifo-depth = <4096>;
225 201
226 mdio { 202 mdio {
227 #address-cells 203 #address-cells = <1>;
228 #size-cells = 204 #size-cells = <0>;
229 compatible = " 205 compatible = "snps,dwmac-mdio";
230 phy0: ethernet !! 206 phy0: ethernet-phy@0 {
231 reg = 207 reg = <0>;
>> 208 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> 209 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> 210 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
232 }; 211 };
233 }; 212 };
234 }; 213 };
235 214
236 usb@60000 { !! 215 ohci@60000 {
237 compatible = "snps,hsd 216 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
238 reg = <0x60000 0x100>; 217 reg = <0x60000 0x100>;
239 interrupts = <15>; 218 interrupts = <15>;
240 resets = <&cgu_rst HSD 219 resets = <&cgu_rst HSDK_USB_RESET>;
241 dma-coherent; 220 dma-coherent;
242 }; 221 };
243 222
244 usb@40000 { !! 223 ehci@40000 {
245 compatible = "snps,hsd 224 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
246 reg = <0x40000 0x100>; 225 reg = <0x40000 0x100>;
247 interrupts = <15>; 226 interrupts = <15>;
248 resets = <&cgu_rst HSD 227 resets = <&cgu_rst HSDK_USB_RESET>;
249 dma-coherent; 228 dma-coherent;
250 }; 229 };
251 230
252 mmc@a000 { 231 mmc@a000 {
253 compatible = "altr,soc 232 compatible = "altr,socfpga-dw-mshc";
254 reg = <0xa000 0x400>; 233 reg = <0xa000 0x400>;
255 num-slots = <1>; 234 num-slots = <1>;
256 fifo-depth = <16>; 235 fifo-depth = <16>;
257 card-detect-delay = <2 236 card-detect-delay = <200>;
258 clocks = <&mmcclk_biu> 237 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
259 clock-names = "biu", " 238 clock-names = "biu", "ciu";
260 interrupts = <12>; 239 interrupts = <12>;
261 bus-width = <4>; 240 bus-width = <4>;
262 dma-coherent; 241 dma-coherent;
263 }; 242 };
264 243
265 spi0: spi@20000 { <<
266 compatible = "snps,dw- <<
267 reg = <0x20000 0x100>; <<
268 #address-cells = <1>; <<
269 #size-cells = <0>; <<
270 interrupts = <16>; <<
271 num-cs = <2>; <<
272 reg-io-width = <4>; <<
273 clocks = <&input_clk>; <<
274 cs-gpios = <&creg_gpio <<
275 <&creg_gpio <<
276 <<
277 flash@0 { <<
278 compatible = " <<
279 reg = <0>; <<
280 #address-cells <<
281 #size-cells = <<
282 spi-max-freque <<
283 }; <<
284 <<
285 adc@1 { <<
286 compatible = " <<
287 reg = <1>; <<
288 vref-supply = <<
289 spi-max-freque <<
290 }; <<
291 }; <<
292 <<
293 creg_gpio: gpio@14b0 { <<
294 compatible = "snps,cre <<
295 reg = <0x14b0 0x4>; <<
296 gpio-controller; <<
297 #gpio-cells = <2>; <<
298 ngpios = <2>; <<
299 }; <<
300 <<
301 gpio: gpio@3000 { 244 gpio: gpio@3000 {
302 compatible = "snps,dw- 245 compatible = "snps,dw-apb-gpio";
303 reg = <0x3000 0x20>; 246 reg = <0x3000 0x20>;
304 #address-cells = <1>; 247 #address-cells = <1>;
305 #size-cells = <0>; 248 #size-cells = <0>;
306 249
307 gpio_port_a: gpio-cont 250 gpio_port_a: gpio-controller@0 {
308 compatible = " 251 compatible = "snps,dw-apb-gpio-port";
309 gpio-controlle 252 gpio-controller;
310 #gpio-cells = 253 #gpio-cells = <2>;
311 snps,nr-gpios 254 snps,nr-gpios = <24>;
312 reg = <0>; 255 reg = <0>;
313 }; 256 };
314 }; <<
315 <<
316 gpu_3d: gpu@90000 { <<
317 compatible = "vivante, <<
318 reg = <0x90000 0x4000> <<
319 clocks = <&gpu_dma_clk <<
320 <&gpu_cfg_clk <<
321 <&gpu_core_cl <<
322 <&gpu_core_cl <<
323 clock-names = "bus", " <<
324 interrupts = <28>; <<
325 }; 257 };
326 258
327 dmac: dmac@80000 { 259 dmac: dmac@80000 {
328 compatible = "snps,axi 260 compatible = "snps,axi-dma-1.01a";
329 reg = <0x80000 0x400>; 261 reg = <0x80000 0x400>;
330 interrupts = <27>; 262 interrupts = <27>;
331 clocks = <&dmac_core_c 263 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
332 clock-names = "core-cl 264 clock-names = "core-clk", "cfgr-clk";
333 265
334 dma-channels = <4>; 266 dma-channels = <4>;
335 snps,dma-masters = <2> 267 snps,dma-masters = <2>;
336 snps,data-width = <3>; 268 snps,data-width = <3>;
337 snps,block-size = <409 269 snps,block-size = <4096 4096 4096 4096>;
338 snps,priority = <0 1 2 270 snps,priority = <0 1 2 3>;
339 snps,axi-max-burst-len 271 snps,axi-max-burst-len = <16>;
340 }; 272 };
341 }; 273 };
342 274
343 memory@80000000 { 275 memory@80000000 {
344 #address-cells = <2>; 276 #address-cells = <2>;
345 #size-cells = <2>; 277 #size-cells = <2>;
346 device_type = "memory"; 278 device_type = "memory";
347 reg = <0x0 0x80000000 0x0 0x40 279 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
348 /* 0x1 0x00000000 0x0 0x40 280 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
349 }; 281 };
350 }; 282 };
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