1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2017 Synopsys, Inc. (www.syno 3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 */ 4 */
5 5
6 /* 6 /*
7 * Device Tree for ARC HS Development Kit 7 * Device Tree for ARC HS Development Kit
8 */ 8 */
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h> 12 #include <dt-bindings/reset/snps,hsdk-reset.h>
13 13
14 / { 14 / {
15 model = "snps,hsdk"; 15 model = "snps,hsdk";
16 compatible = "snps,hsdk"; 16 compatible = "snps,hsdk";
17 17
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 chosen { 21 chosen {
22 bootargs = "earlycon=uart8250, 22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 }; 23 };
24 24
25 aliases { 25 aliases {
26 ethernet = &gmac; 26 ethernet = &gmac;
27 }; 27 };
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu@0 { 33 cpu@0 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 compatible = "snps,arc 35 compatible = "snps,archs38";
36 reg = <0>; 36 reg = <0>;
37 clocks = <&core_clk>; 37 clocks = <&core_clk>;
38 }; 38 };
39 39
40 cpu@1 { 40 cpu@1 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "snps,arc 42 compatible = "snps,archs38";
43 reg = <1>; 43 reg = <1>;
44 clocks = <&core_clk>; 44 clocks = <&core_clk>;
45 }; 45 };
46 46
47 cpu@2 { 47 cpu@2 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "snps,arc 49 compatible = "snps,archs38";
50 reg = <2>; 50 reg = <2>;
51 clocks = <&core_clk>; 51 clocks = <&core_clk>;
52 }; 52 };
53 53
54 cpu@3 { 54 cpu@3 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "snps,arc 56 compatible = "snps,archs38";
57 reg = <3>; 57 reg = <3>;
58 clocks = <&core_clk>; 58 clocks = <&core_clk>;
59 }; 59 };
60 }; 60 };
61 61
62 input_clk: input-clk { 62 input_clk: input-clk {
63 #clock-cells = <0>; 63 #clock-cells = <0>;
64 compatible = "fixed-clock"; 64 compatible = "fixed-clock";
65 clock-frequency = <33333333>; 65 clock-frequency = <33333333>;
66 }; 66 };
67 67
68 reg_5v0: regulator-5v0 { 68 reg_5v0: regulator-5v0 {
69 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
70 70
71 regulator-name = "5v0-supply"; 71 regulator-name = "5v0-supply";
72 regulator-min-microvolt = <500 72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <500 73 regulator-max-microvolt = <5000000>;
74 }; 74 };
75 75
76 cpu_intc: cpu-interrupt-controller { 76 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc" 77 compatible = "snps,archs-intc";
78 interrupt-controller; 78 interrupt-controller;
79 #interrupt-cells = <1>; 79 #interrupt-cells = <1>;
80 }; 80 };
81 81
82 idu_intc: idu-interrupt-controller { 82 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-i 83 compatible = "snps,archs-idu-intc";
84 interrupt-controller; 84 interrupt-controller;
85 #interrupt-cells = <1>; 85 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc> 86 interrupt-parent = <&cpu_intc>;
87 }; 87 };
88 88
89 arcpct: pct { 89 arcpct: pct {
90 compatible = "snps,archs-pct"; 90 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc> 91 interrupt-parent = <&cpu_intc>;
92 interrupts = <20>; 92 interrupts = <20>;
93 }; 93 };
94 94
95 /* TIMER0 with interrupt for clockeven 95 /* TIMER0 with interrupt for clockevent */
96 timer { 96 timer {
97 compatible = "snps,arc-timer"; 97 compatible = "snps,arc-timer";
98 interrupts = <16>; 98 interrupts = <16>;
99 interrupt-parent = <&cpu_intc> 99 interrupt-parent = <&cpu_intc>;
100 clocks = <&core_clk>; 100 clocks = <&core_clk>;
101 }; 101 };
102 102
103 /* 64-bit Global Free Running Counter 103 /* 64-bit Global Free Running Counter */
104 gfrc { 104 gfrc {
105 compatible = "snps,archs-timer 105 compatible = "snps,archs-timer-gfrc";
106 clocks = <&core_clk>; 106 clocks = <&core_clk>;
107 }; 107 };
108 108
109 soc { 109 soc {
110 compatible = "simple-bus"; 110 compatible = "simple-bus";
111 #address-cells = <1>; 111 #address-cells = <1>;
112 #size-cells = <1>; 112 #size-cells = <1>;
113 interrupt-parent = <&idu_intc> 113 interrupt-parent = <&idu_intc>;
114 114
115 ranges = <0x00000000 0x0 0xf00 115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
116 116
117 cgu_rst: reset-controller@8a0 117 cgu_rst: reset-controller@8a0 {
118 compatible = "snps,hsd 118 compatible = "snps,hsdk-reset";
119 #reset-cells = <1>; 119 #reset-cells = <1>;
120 reg = <0x8a0 0x4>, <0x 120 reg = <0x8a0 0x4>, <0xff0 0x4>;
121 }; 121 };
122 122
123 core_clk: core-clk@0 { 123 core_clk: core-clk@0 {
124 compatible = "snps,hsd 124 compatible = "snps,hsdk-core-pll-clock";
125 reg = <0x00 0x10>, <0x 125 reg = <0x00 0x10>, <0x14b8 0x4>;
126 #clock-cells = <0>; 126 #clock-cells = <0>;
127 clocks = <&input_clk>; 127 clocks = <&input_clk>;
128 128
129 /* 129 /*
130 * Set initial core pl 130 * Set initial core pll output frequency to 1GHz.
131 * It will be applied 131 * It will be applied at the core pll driver probing
132 * on early boot. 132 * on early boot.
133 */ 133 */
134 assigned-clocks = <&co 134 assigned-clocks = <&core_clk>;
135 assigned-clock-rates = 135 assigned-clock-rates = <1000000000>;
136 }; 136 };
137 137
138 serial: serial@5000 { 138 serial: serial@5000 {
139 compatible = "snps,dw- 139 compatible = "snps,dw-apb-uart";
140 reg = <0x5000 0x100>; 140 reg = <0x5000 0x100>;
141 clock-frequency = <333 141 clock-frequency = <33330000>;
142 interrupts = <6>; 142 interrupts = <6>;
143 baud = <115200>; 143 baud = <115200>;
144 reg-shift = <2>; 144 reg-shift = <2>;
145 reg-io-width = <4>; 145 reg-io-width = <4>;
146 }; 146 };
147 147
148 gmacclk: gmacclk { 148 gmacclk: gmacclk {
149 compatible = "fixed-cl 149 compatible = "fixed-clock";
150 clock-frequency = <400 150 clock-frequency = <400000000>;
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 }; 152 };
153 153
154 mmcclk_ciu: mmcclk-ciu { 154 mmcclk_ciu: mmcclk-ciu {
155 compatible = "fixed-cl 155 compatible = "fixed-clock";
156 /* 156 /*
157 * DW sdio controller 157 * DW sdio controller has external ciu clock divider
158 * controlled via regi 158 * controlled via register in SDIO IP. Due to its
159 * unexpected default 159 * unexpected default value (it should divide by 1
160 * but it divides by 8 160 * but it divides by 8) SDIO IP uses wrong clock and
161 * works unstable (see 161 * works unstable (see STAR 9001204800)
162 * We switched to the 162 * We switched to the minimum possible value of the
163 * divisor (div-by-2) 163 * divisor (div-by-2) in HSDK platform code.
164 * So add temporary fi 164 * So add temporary fix and change clock frequency
165 * to 50000000 Hz unti 165 * to 50000000 Hz until we fix dw sdio driver itself.
166 */ 166 */
167 clock-frequency = <500 167 clock-frequency = <50000000>;
168 #clock-cells = <0>; 168 #clock-cells = <0>;
169 }; 169 };
170 170
171 mmcclk_biu: mmcclk-biu { 171 mmcclk_biu: mmcclk-biu {
172 compatible = "fixed-cl 172 compatible = "fixed-clock";
173 clock-frequency = <400 173 clock-frequency = <400000000>;
174 #clock-cells = <0>; 174 #clock-cells = <0>;
175 }; 175 };
176 176
177 gpu_core_clk: gpu-core-clk { 177 gpu_core_clk: gpu-core-clk {
178 compatible = "fixed-cl 178 compatible = "fixed-clock";
179 clock-frequency = <400 179 clock-frequency = <400000000>;
180 #clock-cells = <0>; 180 #clock-cells = <0>;
181 }; 181 };
182 182
183 gpu_dma_clk: gpu-dma-clk { 183 gpu_dma_clk: gpu-dma-clk {
184 compatible = "fixed-cl 184 compatible = "fixed-clock";
185 clock-frequency = <400 185 clock-frequency = <400000000>;
186 #clock-cells = <0>; 186 #clock-cells = <0>;
187 }; 187 };
188 188
189 gpu_cfg_clk: gpu-cfg-clk { 189 gpu_cfg_clk: gpu-cfg-clk {
190 compatible = "fixed-cl 190 compatible = "fixed-clock";
191 clock-frequency = <200 191 clock-frequency = <200000000>;
192 #clock-cells = <0>; 192 #clock-cells = <0>;
193 }; 193 };
194 194
195 dmac_core_clk: dmac-core-clk { 195 dmac_core_clk: dmac-core-clk {
196 compatible = "fixed-cl 196 compatible = "fixed-clock";
197 clock-frequency = <400 197 clock-frequency = <400000000>;
198 #clock-cells = <0>; 198 #clock-cells = <0>;
199 }; 199 };
200 200
201 dmac_cfg_clk: dmac-gpu-cfg-clk 201 dmac_cfg_clk: dmac-gpu-cfg-clk {
202 compatible = "fixed-cl 202 compatible = "fixed-clock";
203 clock-frequency = <200 203 clock-frequency = <200000000>;
204 #clock-cells = <0>; 204 #clock-cells = <0>;
205 }; 205 };
206 206
207 gmac: ethernet@8000 { 207 gmac: ethernet@8000 {
>> 208 #interrupt-cells = <1>;
208 compatible = "snps,dwm 209 compatible = "snps,dwmac";
209 reg = <0x8000 0x2000>; 210 reg = <0x8000 0x2000>;
210 interrupts = <10>; 211 interrupts = <10>;
211 interrupt-names = "mac 212 interrupt-names = "macirq";
212 phy-mode = "rgmii-id"; 213 phy-mode = "rgmii-id";
213 snps,pbl = <32>; 214 snps,pbl = <32>;
214 snps,multicast-filter- 215 snps,multicast-filter-bins = <256>;
215 clocks = <&gmacclk>; 216 clocks = <&gmacclk>;
216 clock-names = "stmmace 217 clock-names = "stmmaceth";
217 phy-handle = <&phy0>; 218 phy-handle = <&phy0>;
218 resets = <&cgu_rst HSD 219 resets = <&cgu_rst HSDK_ETH_RESET>;
219 reset-names = "stmmace 220 reset-names = "stmmaceth";
220 mac-address = [00 00 0 221 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
221 dma-coherent; 222 dma-coherent;
222 223
223 tx-fifo-depth = <4096> 224 tx-fifo-depth = <4096>;
224 rx-fifo-depth = <4096> 225 rx-fifo-depth = <4096>;
225 226
226 mdio { 227 mdio {
227 #address-cells 228 #address-cells = <1>;
228 #size-cells = 229 #size-cells = <0>;
229 compatible = " 230 compatible = "snps,dwmac-mdio";
230 phy0: ethernet 231 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
231 reg = 232 reg = <0>;
232 }; 233 };
233 }; 234 };
234 }; 235 };
235 236
236 usb@60000 { !! 237 ohci@60000 {
237 compatible = "snps,hsd 238 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
238 reg = <0x60000 0x100>; 239 reg = <0x60000 0x100>;
239 interrupts = <15>; 240 interrupts = <15>;
240 resets = <&cgu_rst HSD 241 resets = <&cgu_rst HSDK_USB_RESET>;
241 dma-coherent; 242 dma-coherent;
242 }; 243 };
243 244
244 usb@40000 { !! 245 ehci@40000 {
245 compatible = "snps,hsd 246 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
246 reg = <0x40000 0x100>; 247 reg = <0x40000 0x100>;
247 interrupts = <15>; 248 interrupts = <15>;
248 resets = <&cgu_rst HSD 249 resets = <&cgu_rst HSDK_USB_RESET>;
249 dma-coherent; 250 dma-coherent;
250 }; 251 };
251 252
252 mmc@a000 { 253 mmc@a000 {
253 compatible = "altr,soc 254 compatible = "altr,socfpga-dw-mshc";
254 reg = <0xa000 0x400>; 255 reg = <0xa000 0x400>;
255 num-slots = <1>; 256 num-slots = <1>;
256 fifo-depth = <16>; 257 fifo-depth = <16>;
257 card-detect-delay = <2 258 card-detect-delay = <200>;
258 clocks = <&mmcclk_biu> 259 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
259 clock-names = "biu", " 260 clock-names = "biu", "ciu";
260 interrupts = <12>; 261 interrupts = <12>;
261 bus-width = <4>; 262 bus-width = <4>;
262 dma-coherent; 263 dma-coherent;
263 }; 264 };
264 265
265 spi0: spi@20000 { 266 spi0: spi@20000 {
266 compatible = "snps,dw- 267 compatible = "snps,dw-apb-ssi";
267 reg = <0x20000 0x100>; 268 reg = <0x20000 0x100>;
268 #address-cells = <1>; 269 #address-cells = <1>;
269 #size-cells = <0>; 270 #size-cells = <0>;
270 interrupts = <16>; 271 interrupts = <16>;
271 num-cs = <2>; 272 num-cs = <2>;
272 reg-io-width = <4>; 273 reg-io-width = <4>;
273 clocks = <&input_clk>; 274 clocks = <&input_clk>;
274 cs-gpios = <&creg_gpio 275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
275 <&creg_gpio 276 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
276 277
277 flash@0 { !! 278 spi-flash@0 {
278 compatible = " 279 compatible = "sst26wf016b", "jedec,spi-nor";
279 reg = <0>; 280 reg = <0>;
280 #address-cells 281 #address-cells = <1>;
281 #size-cells = 282 #size-cells = <1>;
282 spi-max-freque 283 spi-max-frequency = <4000000>;
283 }; 284 };
284 285
285 adc@1 { 286 adc@1 {
286 compatible = " 287 compatible = "ti,adc108s102";
287 reg = <1>; 288 reg = <1>;
288 vref-supply = 289 vref-supply = <®_5v0>;
289 spi-max-freque 290 spi-max-frequency = <1000000>;
290 }; 291 };
291 }; 292 };
292 293
293 creg_gpio: gpio@14b0 { 294 creg_gpio: gpio@14b0 {
294 compatible = "snps,cre 295 compatible = "snps,creg-gpio-hsdk";
295 reg = <0x14b0 0x4>; 296 reg = <0x14b0 0x4>;
296 gpio-controller; 297 gpio-controller;
297 #gpio-cells = <2>; 298 #gpio-cells = <2>;
298 ngpios = <2>; 299 ngpios = <2>;
299 }; 300 };
300 301
301 gpio: gpio@3000 { 302 gpio: gpio@3000 {
302 compatible = "snps,dw- 303 compatible = "snps,dw-apb-gpio";
303 reg = <0x3000 0x20>; 304 reg = <0x3000 0x20>;
304 #address-cells = <1>; 305 #address-cells = <1>;
305 #size-cells = <0>; 306 #size-cells = <0>;
306 307
307 gpio_port_a: gpio-cont 308 gpio_port_a: gpio-controller@0 {
308 compatible = " 309 compatible = "snps,dw-apb-gpio-port";
309 gpio-controlle 310 gpio-controller;
310 #gpio-cells = 311 #gpio-cells = <2>;
311 snps,nr-gpios 312 snps,nr-gpios = <24>;
312 reg = <0>; 313 reg = <0>;
313 }; 314 };
314 }; 315 };
315 316
316 gpu_3d: gpu@90000 { 317 gpu_3d: gpu@90000 {
317 compatible = "vivante, 318 compatible = "vivante,gc";
318 reg = <0x90000 0x4000> 319 reg = <0x90000 0x4000>;
319 clocks = <&gpu_dma_clk 320 clocks = <&gpu_dma_clk>,
320 <&gpu_cfg_clk 321 <&gpu_cfg_clk>,
321 <&gpu_core_cl 322 <&gpu_core_clk>,
322 <&gpu_core_cl 323 <&gpu_core_clk>;
323 clock-names = "bus", " 324 clock-names = "bus", "reg", "core", "shader";
324 interrupts = <28>; 325 interrupts = <28>;
325 }; 326 };
326 327
327 dmac: dmac@80000 { 328 dmac: dmac@80000 {
328 compatible = "snps,axi 329 compatible = "snps,axi-dma-1.01a";
329 reg = <0x80000 0x400>; 330 reg = <0x80000 0x400>;
330 interrupts = <27>; 331 interrupts = <27>;
331 clocks = <&dmac_core_c 332 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
332 clock-names = "core-cl 333 clock-names = "core-clk", "cfgr-clk";
333 334
334 dma-channels = <4>; 335 dma-channels = <4>;
335 snps,dma-masters = <2> 336 snps,dma-masters = <2>;
336 snps,data-width = <3>; 337 snps,data-width = <3>;
337 snps,block-size = <409 338 snps,block-size = <4096 4096 4096 4096>;
338 snps,priority = <0 1 2 339 snps,priority = <0 1 2 3>;
339 snps,axi-max-burst-len 340 snps,axi-max-burst-len = <16>;
340 }; 341 };
341 }; 342 };
342 343
343 memory@80000000 { 344 memory@80000000 {
344 #address-cells = <2>; 345 #address-cells = <2>;
345 #size-cells = <2>; 346 #size-cells = <2>;
346 device_type = "memory"; 347 device_type = "memory";
347 reg = <0x0 0x80000000 0x0 0x40 348 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
348 /* 0x1 0x00000000 0x0 0x40 349 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
349 }; 350 };
350 }; 351 };
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