1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.s
4 */
5 /dts-v1/;
6
7 /include/ "skeleton_hs.dtsi"
8
9 / {
10 model = "snps,nsimosci_hs";
11 compatible = "snps,nsimosci_hs";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
15
16 chosen {
17 /* this is for console on PGU
18 /* bootargs = "console=tty0 co
19 /* this is for console on seri
20 bootargs = "earlycon=uart8250,
21 };
22
23 aliases {
24 serial0 = &uart0;
25 };
26
27 fpga {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 /* child and parent address sp
33 ranges;
34
35 core_clk: core_clk {
36 #clock-cells = <0>;
37 compatible = "fixed-cl
38 clock-frequency = <200
39 };
40
41 core_intc: core-interrupt-cont
42 compatible = "snps,arc
43 interrupt-controller;
44 #interrupt-cells = <1>
45 };
46
47 uart0: serial@f0000000 {
48 compatible = "ns8250";
49 reg = <0xf0000000 0x20
50 interrupts = <24>;
51 clock-frequency = <368
52 baud = <115200>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 no-loopback-test = <1>
56 };
57
58 pguclk: pguclk {
59 #clock-cells = <0>;
60 compatible = "fixed-cl
61 clock-frequency = <251
62 };
63
64 pgu@f9000000 {
65 compatible = "snps,arc
66 reg = <0xf9000000 0x40
67 clocks = <&pguclk>;
68 clock-names = "pxlclk"
69 };
70
71 ps2: ps2@f9001000 {
72 compatible = "snps,arc
73 reg = <0xf9000400 0x14
74 interrupts = <27>;
75 interrupt-names = "arc
76 };
77
78 eth0: ethernet@f0003000 {
79 compatible = "ezchip,n
80 reg = <0xf0003000 0x44
81 interrupts = <25>;
82 };
83
84 arcpct0: pct {
85 compatible = "snps,arc
86 #interrupt-cells = <1>
87 interrupts = <20>;
88 };
89 };
90 };
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