1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.s 2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 /dts-v1/; 8 /dts-v1/;
6 9
7 /include/ "skeleton_hs.dtsi" 10 /include/ "skeleton_hs.dtsi"
8 11
9 / { 12 / {
10 model = "snps,nsimosci_hs"; 13 model = "snps,nsimosci_hs";
11 compatible = "snps,nsimosci_hs"; 14 compatible = "snps,nsimosci_hs";
12 #address-cells = <1>; 15 #address-cells = <1>;
13 #size-cells = <1>; 16 #size-cells = <1>;
14 interrupt-parent = <&core_intc>; 17 interrupt-parent = <&core_intc>;
15 18
16 chosen { 19 chosen {
17 /* this is for console on PGU 20 /* this is for console on PGU */
18 /* bootargs = "console=tty0 co 21 /* bootargs = "console=tty0 consoleblank=0"; */
19 /* this is for console on seri 22 /* this is for console on serial */
20 bootargs = "earlycon=uart8250, 23 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
21 }; 24 };
22 25
23 aliases { 26 aliases {
24 serial0 = &uart0; 27 serial0 = &uart0;
25 }; 28 };
26 29
27 fpga { 30 fpga {
28 compatible = "simple-bus"; 31 compatible = "simple-bus";
29 #address-cells = <1>; 32 #address-cells = <1>;
30 #size-cells = <1>; 33 #size-cells = <1>;
31 34
32 /* child and parent address sp 35 /* child and parent address space 1:1 mapped */
33 ranges; 36 ranges;
34 37
35 core_clk: core_clk { 38 core_clk: core_clk {
36 #clock-cells = <0>; 39 #clock-cells = <0>;
37 compatible = "fixed-cl 40 compatible = "fixed-clock";
38 clock-frequency = <200 41 clock-frequency = <20000000>;
39 }; 42 };
40 43
41 core_intc: core-interrupt-cont 44 core_intc: core-interrupt-controller {
42 compatible = "snps,arc 45 compatible = "snps,archs-intc";
43 interrupt-controller; 46 interrupt-controller;
44 #interrupt-cells = <1> 47 #interrupt-cells = <1>;
45 }; 48 };
46 49
47 uart0: serial@f0000000 { 50 uart0: serial@f0000000 {
48 compatible = "ns8250"; 51 compatible = "ns8250";
49 reg = <0xf0000000 0x20 52 reg = <0xf0000000 0x2000>;
50 interrupts = <24>; 53 interrupts = <24>;
51 clock-frequency = <368 54 clock-frequency = <3686400>;
52 baud = <115200>; 55 baud = <115200>;
53 reg-shift = <2>; 56 reg-shift = <2>;
54 reg-io-width = <4>; 57 reg-io-width = <4>;
55 no-loopback-test = <1> 58 no-loopback-test = <1>;
56 }; 59 };
57 60
58 pguclk: pguclk { 61 pguclk: pguclk {
59 #clock-cells = <0>; 62 #clock-cells = <0>;
60 compatible = "fixed-cl 63 compatible = "fixed-clock";
61 clock-frequency = <251 64 clock-frequency = <25175000>;
62 }; 65 };
63 66
64 pgu@f9000000 { 67 pgu@f9000000 {
65 compatible = "snps,arc 68 compatible = "snps,arcpgu";
66 reg = <0xf9000000 0x40 69 reg = <0xf9000000 0x400>;
67 clocks = <&pguclk>; 70 clocks = <&pguclk>;
68 clock-names = "pxlclk" 71 clock-names = "pxlclk";
69 }; 72 };
70 73
71 ps2: ps2@f9001000 { 74 ps2: ps2@f9001000 {
72 compatible = "snps,arc 75 compatible = "snps,arc_ps2";
73 reg = <0xf9000400 0x14 76 reg = <0xf9000400 0x14>;
74 interrupts = <27>; 77 interrupts = <27>;
75 interrupt-names = "arc 78 interrupt-names = "arc_ps2_irq";
76 }; 79 };
77 80
78 eth0: ethernet@f0003000 { 81 eth0: ethernet@f0003000 {
79 compatible = "ezchip,n 82 compatible = "ezchip,nps-mgt-enet";
80 reg = <0xf0003000 0x44 83 reg = <0xf0003000 0x44>;
81 interrupts = <25>; 84 interrupts = <25>;
82 }; 85 };
83 86
84 arcpct0: pct { 87 arcpct0: pct {
85 compatible = "snps,arc 88 compatible = "snps,archs-pct";
86 #interrupt-cells = <1> 89 #interrupt-cells = <1>;
87 interrupts = <20>; 90 interrupts = <20>;
88 }; 91 };
89 }; 92 };
90 }; 93 };
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