1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2012 Synopsys, Inc. (www.syno 3 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
4 */ 4 */
5 5
6 /* 6 /*
7 * Skeleton device tree; the bare minimum need 7 * Skeleton device tree; the bare minimum needed to boot; just include and
8 * add a compatible value. 8 * add a compatible value.
9 */ 9 */
10 10
11 / { 11 / {
12 compatible = "snps,arc"; 12 compatible = "snps,arc";
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 chosen { }; 15 chosen { };
16 aliases { }; 16 aliases { };
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 21
22 cpu@0 { 22 cpu@0 {
23 device_type = "cpu"; 23 device_type = "cpu";
24 compatible = "snps,arc 24 compatible = "snps,arc770d";
25 reg = <0>; 25 reg = <0>;
26 clocks = <&core_clk>; 26 clocks = <&core_clk>;
27 }; 27 };
28 }; 28 };
29 29
30 /* TIMER0 with interrupt for clockeven 30 /* TIMER0 with interrupt for clockevent */
31 timer0 { 31 timer0 {
32 compatible = "snps,arc-timer"; 32 compatible = "snps,arc-timer";
33 interrupts = <3>; 33 interrupts = <3>;
34 interrupt-parent = <&core_intc 34 interrupt-parent = <&core_intc>;
35 clocks = <&core_clk>; 35 clocks = <&core_clk>;
36 }; 36 };
37 37
38 /* TIMER1 for free running clocksource 38 /* TIMER1 for free running clocksource */
39 timer1 { 39 timer1 {
40 compatible = "snps,arc-timer"; 40 compatible = "snps,arc-timer";
41 clocks = <&core_clk>; 41 clocks = <&core_clk>;
42 }; 42 };
43 43
44 memory { 44 memory {
45 device_type = "memory"; 45 device_type = "memory";
46 reg = <0x80000000 0x10000000>; 46 reg = <0x80000000 0x10000000>; /* 256M */
47 }; 47 };
48 }; 48 };
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