1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Actions Semi S500 SoC
4 *
5 * Copyright (c) 2016-2017 Andreas Färber
6 */
7
8 #include <dt-bindings/clock/actions,s500-cmu.h
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/power/owl-s500-powergate
12 #include <dt-bindings/reset/actions,s500-reset
13
14 / {
15 compatible = "actions,s500";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 };
22
23 chosen {
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu0: cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cort
33 reg = <0x0>;
34 enable-method = "actio
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cort
40 reg = <0x1>;
41 enable-method = "actio
42 };
43
44 cpu2: cpu@2 {
45 device_type = "cpu";
46 compatible = "arm,cort
47 reg = <0x2>;
48 enable-method = "actio
49 power-domains = <&sps
50 };
51
52 cpu3: cpu@3 {
53 device_type = "cpu";
54 compatible = "arm,cort
55 reg = <0x3>;
56 enable-method = "actio
57 power-domains = <&sps
58 };
59 };
60
61 arm-pmu {
62 compatible = "arm,cortex-a9-pm
63 interrupts = <GIC_SPI 4 IRQ_TY
64 <GIC_SPI 5 IRQ_TY
65 <GIC_SPI 6 IRQ_TY
66 <GIC_SPI 7 IRQ_TY
67 interrupt-affinity = <&cpu0>,
68 };
69
70 hosc: hosc {
71 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
73 #clock-cells = <0>;
74 };
75
76 losc: losc {
77 compatible = "fixed-clock";
78 clock-frequency = <32768>;
79 #clock-cells = <0>;
80 };
81
82 soc {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87
88 scu: scu@b0020000 {
89 compatible = "arm,cort
90 reg = <0xb0020000 0x10
91 };
92
93 global_timer: timer@b0020200 {
94 compatible = "arm,cort
95 reg = <0xb0020200 0x10
96 interrupts = <GIC_PPI
97 status = "disabled";
98 };
99
100 twd_timer: timer@b0020600 {
101 compatible = "arm,cort
102 reg = <0xb0020600 0x20
103 interrupts = <GIC_PPI
104 status = "disabled";
105 };
106
107 twd_wdt: wdt@b0020620 {
108 compatible = "arm,cort
109 reg = <0xb0020620 0xe0
110 interrupts = <GIC_PPI
111 status = "disabled";
112 };
113
114 gic: interrupt-controller@b002
115 compatible = "arm,cort
116 reg = <0xb0021000 0x10
117 <0xb0020100 0x01
118 interrupt-controller;
119 #interrupt-cells = <3>
120 };
121
122 l2: cache-controller@b0022000
123 compatible = "arm,pl31
124 reg = <0xb0022000 0x10
125 cache-unified;
126 cache-level = <2>;
127 interrupts = <GIC_SPI
128 arm,tag-latency = <3 3
129 arm,data-latency = <5
130 };
131
132 uart0: serial@b0120000 {
133 compatible = "actions,
134 reg = <0xb0120000 0x20
135 interrupts = <GIC_SPI
136 clocks = <&cmu CLK_UAR
137 status = "disabled";
138 };
139
140 uart1: serial@b0122000 {
141 compatible = "actions,
142 reg = <0xb0122000 0x20
143 interrupts = <GIC_SPI
144 clocks = <&cmu CLK_UAR
145 status = "disabled";
146 };
147
148 uart2: serial@b0124000 {
149 compatible = "actions,
150 reg = <0xb0124000 0x20
151 interrupts = <GIC_SPI
152 clocks = <&cmu CLK_UAR
153 status = "disabled";
154 };
155
156 uart3: serial@b0126000 {
157 compatible = "actions,
158 reg = <0xb0126000 0x20
159 interrupts = <GIC_SPI
160 clocks = <&cmu CLK_UAR
161 status = "disabled";
162 };
163
164 uart4: serial@b0128000 {
165 compatible = "actions,
166 reg = <0xb0128000 0x20
167 interrupts = <GIC_SPI
168 clocks = <&cmu CLK_UAR
169 status = "disabled";
170 };
171
172 uart5: serial@b012a000 {
173 compatible = "actions,
174 reg = <0xb012a000 0x20
175 interrupts = <GIC_SPI
176 clocks = <&cmu CLK_UAR
177 status = "disabled";
178 };
179
180 uart6: serial@b012c000 {
181 compatible = "actions,
182 reg = <0xb012c000 0x20
183 interrupts = <GIC_SPI
184 clocks = <&cmu CLK_UAR
185 status = "disabled";
186 };
187
188 cmu: clock-controller@b0160000
189 compatible = "actions,
190 reg = <0xb0160000 0x80
191 clocks = <&hosc>, <&lo
192 #clock-cells = <1>;
193 #reset-cells = <1>;
194 };
195
196 i2c0: i2c@b0170000 {
197 compatible = "actions,
198 reg = <0xb0170000 0x40
199 clocks = <&cmu CLK_I2C
200 interrupts = <GIC_SPI
201 #address-cells = <1>;
202 #size-cells = <0>;
203 status = "disabled";
204 };
205
206 i2c1: i2c@b0174000 {
207 compatible = "actions,
208 reg = <0xb0174000 0x40
209 clocks = <&cmu CLK_I2C
210 interrupts = <GIC_SPI
211 #address-cells = <1>;
212 #size-cells = <0>;
213 status = "disabled";
214 };
215
216 i2c2: i2c@b0178000 {
217 compatible = "actions,
218 reg = <0xb0178000 0x40
219 clocks = <&cmu CLK_I2C
220 interrupts = <GIC_SPI
221 #address-cells = <1>;
222 #size-cells = <0>;
223 status = "disabled";
224 };
225
226 i2c3: i2c@b017c000 {
227 compatible = "actions,
228 reg = <0xb017c000 0x40
229 clocks = <&cmu CLK_I2C
230 interrupts = <GIC_SPI
231 #address-cells = <1>;
232 #size-cells = <0>;
233 status = "disabled";
234 };
235
236 sirq: interrupt-controller@b01
237 compatible = "actions,
238 reg = <0xb01b0200 0x4>
239 interrupt-controller;
240 #interrupt-cells = <2>
241 interrupts = <GIC_SPI
242 <GIC_SPI
243 <GIC_SPI
244 };
245
246 timer: timer@b0168000 {
247 compatible = "actions,
248 reg = <0xb0168000 0x80
249 interrupts = <GIC_SPI
250 <GIC_SPI
251 <GIC_SPI
252 <GIC_SPI
253 interrupt-names = "2hz
254 };
255
256 sps: power-controller@b01b0100
257 compatible = "actions,
258 reg = <0xb01b0100 0x10
259 #power-domain-cells =
260 };
261
262 pinctrl: pinctrl@b01b0000 {
263 compatible = "actions,
264 reg = <0xb01b0000 0x40
265 <0xb01b0040 0x10
266 <0xb01b0060 0x18
267 <0xb01b0080 0xc>
268 clocks = <&cmu CLK_GPI
269 gpio-controller;
270 gpio-ranges = <&pinctr
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>
274 interrupts = <GIC_SPI
275 <GIC_SPI
276 <GIC_SPI
277 <GIC_SPI
278 <GIC_SPI
279 };
280
281 dma: dma-controller@b0260000 {
282 compatible = "actions,
283 reg = <0xb0260000 0xd0
284 interrupts = <GIC_SPI
285 <GIC_SPI
286 <GIC_SPI
287 <GIC_SPI
288 #dma-cells = <1>;
289 dma-channels = <12>;
290 dma-requests = <46>;
291 clocks = <&cmu CLK_DMA
292 power-domains = <&sps
293 };
294
295 mmc0: mmc@b0230000 {
296 compatible = "actions,
297 reg = <0xb0230000 0x38
298 interrupts = <GIC_SPI
299 clocks = <&cmu CLK_SD0
300 resets = <&cmu RESET_S
301 dmas = <&dma 2>;
302 dma-names = "mmc";
303 status = "disabled";
304 };
305
306 mmc1: mmc@b0234000 {
307 compatible = "actions,
308 reg = <0xb0234000 0x38
309 interrupts = <GIC_SPI
310 clocks = <&cmu CLK_SD1
311 resets = <&cmu RESET_S
312 dmas = <&dma 3>;
313 dma-names = "mmc";
314 status = "disabled";
315 };
316
317 mmc2: mmc@b0238000 {
318 compatible = "actions,
319 reg = <0xb0238000 0x38
320 interrupts = <GIC_SPI
321 clocks = <&cmu CLK_SD2
322 resets = <&cmu RESET_S
323 dmas = <&dma 4>;
324 dma-names = "mmc";
325 status = "disabled";
326 };
327
328 ethernet: ethernet@b0310000 {
329 compatible = "actions,
330 reg = <0xb0310000 0x10
331 interrupts = <GIC_SPI
332 clocks = <&cmu CLK_ETH
333 clock-names = "eth", "
334 resets = <&cmu RESET_E
335 status = "disabled";
336 };
337 };
338 };
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