1 // SPDX-License-Identifier: (GPL-2.0-only OR B
2
3 #include <dt-bindings/interrupt-controller/irq
4 #include <dt-bindings/interrupt-controller/arm
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
7
8 / {
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 npu_binary@84000000 {
19 no-map;
20 reg = <0x84000000 0xA0
21 };
22
23 npu_flag@84B0000 {
24 no-map;
25 reg = <0x84B00000 0x10
26 };
27
28 npu_pkt@85000000 {
29 no-map;
30 reg = <0x85000000 0x1A
31 };
32
33 npu_phyaddr@86B00000 {
34 no-map;
35 reg = <0x86B00000 0x10
36 };
37
38 npu_rxdesc@86D00000 {
39 no-map;
40 reg = <0x86D00000 0x10
41 };
42 };
43
44 psci {
45 compatible = "arm,psci-0.2";
46 method = "smc";
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu-map {
54 cluster0 {
55 core0 {
56 cpu =
57 };
58 core1 {
59 cpu =
60 };
61 };
62 };
63
64 cpu0: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cort
67 reg = <0x0>;
68 enable-method = "psci"
69 clock-frequency = <800
70 next-level-cache = <&L
71 };
72
73 cpu1: cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cort
76 reg = <0x1>;
77 enable-method = "psci"
78 clock-frequency = <800
79 next-level-cache = <&L
80 };
81
82 L2_0: l2-cache0 {
83 compatible = "cache";
84 cache-level = <2>;
85 cache-unified;
86 };
87 };
88
89 scu: system-controller@1fa20000 {
90 compatible = "airoha,en7523-sc
91 reg = <0x1fa20000 0x400>,
92 <0x1fb00000 0x1000>;
93 #clock-cells = <1>;
94 };
95
96 gic: interrupt-controller@9000000 {
97 compatible = "arm,gic-v3";
98 interrupt-controller;
99 #interrupt-cells = <3>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x09000000 0x20000>,
103 <0x09080000 0x80000>,
104 <0x09400000 0x2000>,
105 <0x09500000 0x2000>,
106 <0x09600000 0x20000>;
107 interrupts = <GIC_PPI 9 IRQ_TY
108 };
109
110 timer {
111 compatible = "arm,armv8-timer"
112 interrupt-parent = <&gic>;
113 interrupts = <GIC_PPI 13 IRQ_T
114 <GIC_PPI 14 IRQ_T
115 <GIC_PPI 11 IRQ_T
116 <GIC_PPI 10 IRQ_T
117 };
118
119 uart1: serial@1fbf0000 {
120 compatible = "ns16550";
121 reg = <0x1fbf0000 0x30>;
122 reg-io-width = <4>;
123 reg-shift = <2>;
124 interrupts = <GIC_SPI 18 IRQ_T
125 clock-frequency = <1843200>;
126 status = "okay";
127 };
128
129 gpio0: gpio@1fbf0200 {
130 compatible = "airoha,en7523-gp
131 reg = <0x1fbf0204 0x4>,
132 <0x1fbf0200 0x4>,
133 <0x1fbf0220 0x4>,
134 <0x1fbf0214 0x4>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 };
138
139 gpio1: gpio@1fbf0270 {
140 compatible = "airoha,en7523-gp
141 reg = <0x1fbf0270 0x4>,
142 <0x1fbf0260 0x4>,
143 <0x1fbf0264 0x4>,
144 <0x1fbf0278 0x4>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
148
149 pcie0: pcie@1fa91000 {
150 compatible = "airoha,en7523-pc
151 device_type = "pci";
152 reg = <0x1fa91000 0x1000>;
153 reg-names = "port0";
154 linux,pci-domain = <0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 interrupts = <GIC_SPI 39 IRQ_T
158 interrupt-names = "pcie_irq";
159 clocks = <&scu EN7523_CLK_PCIE
160 clock-names = "sys_ck0";
161 bus-range = <0x00 0xff>;
162 ranges = <0x82000000 0 0x20000
163 status = "disabled";
164
165 #interrupt-cells = <1>;
166 interrupt-map-mask = <0 0 0 7>
167 interrupt-map = <0 0 0 1 &pcie
168 <0 0 0 2 &pcie
169 <0 0 0 3 &pcie
170 <0 0 0 4 &pcie
171 pcie_intc0: interrupt-controll
172 interrupt-controller;
173 #address-cells = <0>;
174 #interrupt-cells = <1>
175 };
176 };
177
178 pcie1: pcie@1fa92000 {
179 compatible = "airoha,en7523-pc
180 device_type = "pci";
181 reg = <0x1fa92000 0x1000>;
182 reg-names = "port1";
183 linux,pci-domain = <1>;
184 #address-cells = <3>;
185 #size-cells = <2>;
186 interrupts = <GIC_SPI 40 IRQ_T
187 interrupt-names = "pcie_irq";
188 clocks = <&scu EN7523_CLK_PCIE
189 clock-names = "sys_ck1";
190 bus-range = <0x00 0xff>;
191 ranges = <0x82000000 0 0x28000
192 status = "disabled";
193
194 #interrupt-cells = <1>;
195 interrupt-map-mask = <0 0 0 7>
196 interrupt-map = <0 0 0 1 &pcie
197 <0 0 0 2 &pcie
198 <0 0 0 3 &pcie
199 <0 0 0 4 &pcie
200 pcie_intc1: interrupt-controll
201 interrupt-controller;
202 #address-cells = <0>;
203 #interrupt-cells = <1>
204 };
205 };
206 };
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