1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 2
3 #include <dt-bindings/interrupt-controller/irq 3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h> 6 #include <dt-bindings/clock/en7523-clk.h>
7 7
8 / { 8 / {
9 interrupt-parent = <&gic>; 9 interrupt-parent = <&gic>;
10 #address-cells = <1>; 10 #address-cells = <1>;
11 #size-cells = <1>; 11 #size-cells = <1>;
12 12
13 reserved-memory { 13 reserved-memory {
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 ranges; 16 ranges;
17 17
18 npu_binary@84000000 { 18 npu_binary@84000000 {
19 no-map; 19 no-map;
20 reg = <0x84000000 0xA0 20 reg = <0x84000000 0xA00000>;
21 }; 21 };
22 22
23 npu_flag@84B0000 { 23 npu_flag@84B0000 {
24 no-map; 24 no-map;
25 reg = <0x84B00000 0x10 25 reg = <0x84B00000 0x100000>;
26 }; 26 };
27 27
28 npu_pkt@85000000 { 28 npu_pkt@85000000 {
29 no-map; 29 no-map;
30 reg = <0x85000000 0x1A 30 reg = <0x85000000 0x1A00000>;
31 }; 31 };
32 32
33 npu_phyaddr@86B00000 { 33 npu_phyaddr@86B00000 {
34 no-map; 34 no-map;
35 reg = <0x86B00000 0x10 35 reg = <0x86B00000 0x100000>;
36 }; 36 };
37 37
38 npu_rxdesc@86D00000 { 38 npu_rxdesc@86D00000 {
39 no-map; 39 no-map;
40 reg = <0x86D00000 0x10 40 reg = <0x86D00000 0x100000>;
41 }; 41 };
42 }; 42 };
43 43
44 psci { 44 psci {
45 compatible = "arm,psci-0.2"; 45 compatible = "arm,psci-0.2";
46 method = "smc"; 46 method = "smc";
47 }; 47 };
48 48
49 cpus { 49 cpus {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 cpu-map { 53 cpu-map {
54 cluster0 { 54 cluster0 {
55 core0 { 55 core0 {
56 cpu = 56 cpu = <&cpu0>;
57 }; 57 };
58 core1 { 58 core1 {
59 cpu = 59 cpu = <&cpu1>;
60 }; 60 };
61 }; 61 };
62 }; 62 };
63 63
64 cpu0: cpu@0 { 64 cpu0: cpu@0 {
65 device_type = "cpu"; 65 device_type = "cpu";
66 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
67 reg = <0x0>; 67 reg = <0x0>;
68 enable-method = "psci" 68 enable-method = "psci";
69 clock-frequency = <800 69 clock-frequency = <80000000>;
70 next-level-cache = <&L 70 next-level-cache = <&L2_0>;
71 }; 71 };
72 72
73 cpu1: cpu@1 { 73 cpu1: cpu@1 {
74 device_type = "cpu"; 74 device_type = "cpu";
75 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
76 reg = <0x1>; 76 reg = <0x1>;
77 enable-method = "psci" 77 enable-method = "psci";
78 clock-frequency = <800 78 clock-frequency = <80000000>;
79 next-level-cache = <&L 79 next-level-cache = <&L2_0>;
80 }; 80 };
81 81
82 L2_0: l2-cache0 { 82 L2_0: l2-cache0 {
83 compatible = "cache"; 83 compatible = "cache";
84 cache-level = <2>; 84 cache-level = <2>;
85 cache-unified; 85 cache-unified;
86 }; 86 };
87 }; 87 };
88 88
89 scu: system-controller@1fa20000 { 89 scu: system-controller@1fa20000 {
90 compatible = "airoha,en7523-sc 90 compatible = "airoha,en7523-scu";
91 reg = <0x1fa20000 0x400>, 91 reg = <0x1fa20000 0x400>,
92 <0x1fb00000 0x1000>; 92 <0x1fb00000 0x1000>;
93 #clock-cells = <1>; 93 #clock-cells = <1>;
94 }; 94 };
95 95
96 gic: interrupt-controller@9000000 { 96 gic: interrupt-controller@9000000 {
97 compatible = "arm,gic-v3"; 97 compatible = "arm,gic-v3";
98 interrupt-controller; 98 interrupt-controller;
99 #interrupt-cells = <3>; 99 #interrupt-cells = <3>;
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <1>; 101 #size-cells = <1>;
102 reg = <0x09000000 0x20000>, 102 reg = <0x09000000 0x20000>,
103 <0x09080000 0x80000>, 103 <0x09080000 0x80000>,
104 <0x09400000 0x2000>, 104 <0x09400000 0x2000>,
105 <0x09500000 0x2000>, 105 <0x09500000 0x2000>,
106 <0x09600000 0x20000>; 106 <0x09600000 0x20000>;
107 interrupts = <GIC_PPI 9 IRQ_TY 107 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
108 }; 108 };
109 109
110 timer { 110 timer {
111 compatible = "arm,armv8-timer" 111 compatible = "arm,armv8-timer";
112 interrupt-parent = <&gic>; 112 interrupt-parent = <&gic>;
113 interrupts = <GIC_PPI 13 IRQ_T 113 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
114 <GIC_PPI 14 IRQ_T 114 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
115 <GIC_PPI 11 IRQ_T 115 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
116 <GIC_PPI 10 IRQ_T 116 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
117 }; 117 };
118 118
119 uart1: serial@1fbf0000 { 119 uart1: serial@1fbf0000 {
120 compatible = "ns16550"; 120 compatible = "ns16550";
121 reg = <0x1fbf0000 0x30>; 121 reg = <0x1fbf0000 0x30>;
122 reg-io-width = <4>; 122 reg-io-width = <4>;
123 reg-shift = <2>; 123 reg-shift = <2>;
124 interrupts = <GIC_SPI 18 IRQ_T 124 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
125 clock-frequency = <1843200>; 125 clock-frequency = <1843200>;
126 status = "okay"; 126 status = "okay";
127 }; 127 };
128 128
129 gpio0: gpio@1fbf0200 { 129 gpio0: gpio@1fbf0200 {
130 compatible = "airoha,en7523-gp 130 compatible = "airoha,en7523-gpio";
131 reg = <0x1fbf0204 0x4>, 131 reg = <0x1fbf0204 0x4>,
132 <0x1fbf0200 0x4>, 132 <0x1fbf0200 0x4>,
133 <0x1fbf0220 0x4>, 133 <0x1fbf0220 0x4>,
134 <0x1fbf0214 0x4>; 134 <0x1fbf0214 0x4>;
135 gpio-controller; 135 gpio-controller;
136 #gpio-cells = <2>; 136 #gpio-cells = <2>;
137 }; 137 };
138 138
139 gpio1: gpio@1fbf0270 { 139 gpio1: gpio@1fbf0270 {
140 compatible = "airoha,en7523-gp 140 compatible = "airoha,en7523-gpio";
141 reg = <0x1fbf0270 0x4>, 141 reg = <0x1fbf0270 0x4>,
142 <0x1fbf0260 0x4>, 142 <0x1fbf0260 0x4>,
143 <0x1fbf0264 0x4>, 143 <0x1fbf0264 0x4>,
144 <0x1fbf0278 0x4>; 144 <0x1fbf0278 0x4>;
145 gpio-controller; 145 gpio-controller;
146 #gpio-cells = <2>; 146 #gpio-cells = <2>;
147 }; 147 };
148 148
149 pcie0: pcie@1fa91000 { 149 pcie0: pcie@1fa91000 {
150 compatible = "airoha,en7523-pc 150 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
151 device_type = "pci"; 151 device_type = "pci";
152 reg = <0x1fa91000 0x1000>; 152 reg = <0x1fa91000 0x1000>;
153 reg-names = "port0"; 153 reg-names = "port0";
154 linux,pci-domain = <0>; 154 linux,pci-domain = <0>;
155 #address-cells = <3>; 155 #address-cells = <3>;
156 #size-cells = <2>; 156 #size-cells = <2>;
157 interrupts = <GIC_SPI 39 IRQ_T 157 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "pcie_irq"; 158 interrupt-names = "pcie_irq";
159 clocks = <&scu EN7523_CLK_PCIE 159 clocks = <&scu EN7523_CLK_PCIE>;
160 clock-names = "sys_ck0"; 160 clock-names = "sys_ck0";
161 bus-range = <0x00 0xff>; 161 bus-range = <0x00 0xff>;
162 ranges = <0x82000000 0 0x20000 162 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
163 status = "disabled"; 163 status = "disabled";
164 164
165 #interrupt-cells = <1>; 165 #interrupt-cells = <1>;
166 interrupt-map-mask = <0 0 0 7> 166 interrupt-map-mask = <0 0 0 7>;
167 interrupt-map = <0 0 0 1 &pcie 167 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
168 <0 0 0 2 &pcie 168 <0 0 0 2 &pcie_intc0 1>,
169 <0 0 0 3 &pcie 169 <0 0 0 3 &pcie_intc0 2>,
170 <0 0 0 4 &pcie 170 <0 0 0 4 &pcie_intc0 3>;
171 pcie_intc0: interrupt-controll 171 pcie_intc0: interrupt-controller {
172 interrupt-controller; 172 interrupt-controller;
173 #address-cells = <0>; 173 #address-cells = <0>;
174 #interrupt-cells = <1> 174 #interrupt-cells = <1>;
175 }; 175 };
176 }; 176 };
177 177
178 pcie1: pcie@1fa92000 { 178 pcie1: pcie@1fa92000 {
179 compatible = "airoha,en7523-pc 179 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
180 device_type = "pci"; 180 device_type = "pci";
181 reg = <0x1fa92000 0x1000>; 181 reg = <0x1fa92000 0x1000>;
182 reg-names = "port1"; 182 reg-names = "port1";
183 linux,pci-domain = <1>; 183 linux,pci-domain = <1>;
184 #address-cells = <3>; 184 #address-cells = <3>;
185 #size-cells = <2>; 185 #size-cells = <2>;
186 interrupts = <GIC_SPI 40 IRQ_T 186 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "pcie_irq"; 187 interrupt-names = "pcie_irq";
188 clocks = <&scu EN7523_CLK_PCIE 188 clocks = <&scu EN7523_CLK_PCIE>;
189 clock-names = "sys_ck1"; 189 clock-names = "sys_ck1";
190 bus-range = <0x00 0xff>; 190 bus-range = <0x00 0xff>;
191 ranges = <0x82000000 0 0x28000 191 ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
192 status = "disabled"; 192 status = "disabled";
193 193
194 #interrupt-cells = <1>; 194 #interrupt-cells = <1>;
195 interrupt-map-mask = <0 0 0 7> 195 interrupt-map-mask = <0 0 0 7>;
196 interrupt-map = <0 0 0 1 &pcie 196 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
197 <0 0 0 2 &pcie 197 <0 0 0 2 &pcie_intc1 1>,
198 <0 0 0 3 &pcie 198 <0 0 0 3 &pcie_intc1 2>,
199 <0 0 0 4 &pcie 199 <0 0 0 4 &pcie_intc1 3>;
200 pcie_intc1: interrupt-controll 200 pcie_intc1: interrupt-controller {
201 interrupt-controller; 201 interrupt-controller;
202 #address-cells = <0>; 202 #address-cells = <0>;
203 #interrupt-cells = <1> 203 #interrupt-cells = <1>;
204 }; 204 };
205 }; 205 };
206 }; 206 };
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