1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it
7 * of the GPL or the X11 license, at your opti
8 * licensing only applies to this file, and no
9 * whole.
10 *
11 * a) This file is free software; you can red
12 * modify it under the terms of the GNU Ge
13 * published by the Free Software Foundati
14 * License, or (at your option) any later
15 *
16 * This file is distributed in the hope th
17 * but WITHOUT ANY WARRANTY; without even
18 * MERCHANTABILITY or FITNESS FOR A PARTIC
19 * GNU General Public License for more det
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of c
24 * obtaining a copy of this software and a
25 * files (the "Software"), to deal in the
26 * restriction, including without limitati
27 * copy, modify, merge, publish, distribut
28 * sell copies of the Software, and to per
29 * Software is furnished to do so, subject
30 * conditions:
31 *
32 * The above copyright notice and this per
33 * included in all copies or substantial p
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
40 * WHETHER IN AN ACTION OF CONTRACT, TORT
41 * FROM, OUT OF OR IN CONNECTION WITH THE
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include <dt-bindings/interrupt-controller/arm
46
47 #include <dt-bindings/clock/sun6i-rtc.h>
48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.
50
51 / {
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 chosen {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 simplefb_lcd: framebuffer-lcd0
62 compatible = "allwinne
63 "simple-f
64 allwinner,pipeline = "
65 clocks = <&ccu CLK_BUS
66 <&ccu CLK_LCD
67 <&ccu CLK_DRA
68 status = "disabled";
69 };
70 };
71
72 de: display-engine {
73 /* compatible gets set in SoC
74 allwinner,pipelines = <&fe0>;
75 status = "disabled";
76 };
77
78 timer {
79 compatible = "arm,armv7-timer"
80 interrupts = <GIC_PPI 13 (GIC_
81 <GIC_PPI 14 (GIC_
82 <GIC_PPI 11 (GIC_
83 <GIC_PPI 10 (GIC_
84 clock-frequency = <24000000>;
85 arm,cpu-registers-not-fw-confi
86 };
87
88 cpus {
89 enable-method = "allwinner,sun
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 cpu0: cpu@0 {
94 compatible = "arm,cort
95 device_type = "cpu";
96 reg = <0>;
97 };
98
99 cpu@1 {
100 compatible = "arm,cort
101 device_type = "cpu";
102 reg = <1>;
103 };
104 };
105
106 clocks {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 osc24M: osc24M-clk {
112 #clock-cells = <0>;
113 compatible = "fixed-cl
114 clock-frequency = <240
115 clock-accuracy = <5000
116 clock-output-names = "
117 };
118
119 ext_osc32k: ext-osc32k-clk {
120 #clock-cells = <0>;
121 compatible = "fixed-cl
122 clock-frequency = <327
123 clock-accuracy = <5000
124 clock-output-names = "
125 };
126 };
127
128 soc {
129 compatible = "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges;
133
134 system-control@1c00000 {
135 compatible = "allwinne
136 reg = <0x01c00000 0x30
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges;
140
141 sram_c: sram@1d00000 {
142 compatible = "
143 reg = <0x01d00
144 #address-cells
145 #size-cells =
146 ranges = <0 0x
147
148 ve_sram: sram-
149 compat
150
151 reg =
152 };
153 };
154 };
155
156 dma: dma-controller@1c02000 {
157 compatible = "allwinne
158 reg = <0x01c02000 0x10
159 interrupts = <GIC_SPI
160 clocks = <&ccu CLK_BUS
161 resets = <&ccu RST_BUS
162 #dma-cells = <1>;
163 };
164
165 nfc: nand-controller@1c03000 {
166 compatible = "allwinne
167 reg = <0x01c03000 0x10
168 interrupts = <GIC_SPI
169 clocks = <&ccu CLK_BUS
170 clock-names = "ahb", "
171 resets = <&ccu RST_BUS
172 reset-names = "ahb";
173 dmas = <&dma 5>;
174 dma-names = "rxtx";
175 pinctrl-names = "defau
176 pinctrl-0 = <&nand_pin
177 status = "disabled";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181
182 tcon0: lcd-controller@1c0c000
183 /* compatible gets set
184 reg = <0x01c0c000 0x10
185 interrupts = <GIC_SPI
186 dmas = <&dma 12>;
187 clocks = <&ccu CLK_BUS
188 <&ccu CLK_LCD
189 <&ccu 13>;
190 clock-names = "ahb",
191 "tcon-ch
192 "lvds-al
193 clock-output-names = "
194 #clock-cells = <0>;
195 resets = <&ccu RST_BUS
196 <&ccu RST_BUS
197 reset-names = "lcd",
198 "lvds";
199 status = "disabled";
200
201 ports {
202 #address-cells
203 #size-cells =
204
205 tcon0_in: port
206 reg =
207
208 tcon0_
209
210 };
211 };
212
213 tcon0_out: por
214 reg =
215 };
216 };
217 };
218
219 mmc0: mmc@1c0f000 {
220 compatible = "allwinne
221 reg = <0x01c0f000 0x10
222 clocks = <&ccu CLK_BUS
223 <&ccu CLK_MMC
224 <&ccu CLK_MMC
225 <&ccu CLK_MMC
226 clock-names = "ahb",
227 "mmc",
228 "output"
229 "sample"
230 resets = <&ccu RST_BUS
231 reset-names = "ahb";
232 interrupts = <GIC_SPI
233 pinctrl-names = "defau
234 pinctrl-0 = <&mmc0_pin
235 status = "disabled";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 mmc1: mmc@1c10000 {
241 compatible = "allwinne
242 reg = <0x01c10000 0x10
243 clocks = <&ccu CLK_BUS
244 <&ccu CLK_MMC
245 <&ccu CLK_MMC
246 <&ccu CLK_MMC
247 clock-names = "ahb",
248 "mmc",
249 "output"
250 "sample"
251 resets = <&ccu RST_BUS
252 reset-names = "ahb";
253 interrupts = <GIC_SPI
254 status = "disabled";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 };
258
259 mmc2: mmc@1c11000 {
260 compatible = "allwinne
261 reg = <0x01c11000 0x10
262 clocks = <&ccu CLK_BUS
263 <&ccu CLK_MMC
264 <&ccu CLK_MMC
265 <&ccu CLK_MMC
266 clock-names = "ahb",
267 "mmc",
268 "output"
269 "sample"
270 resets = <&ccu RST_BUS
271 reset-names = "ahb";
272 interrupts = <GIC_SPI
273 status = "disabled";
274 #address-cells = <1>;
275 #size-cells = <0>;
276 };
277
278 usb_otg: usb@1c19000 {
279 /* compatible gets set
280 reg = <0x01c19000 0x04
281 clocks = <&ccu CLK_BUS
282 resets = <&ccu RST_BUS
283 interrupts = <GIC_SPI
284 interrupt-names = "mc"
285 phys = <&usbphy 0>;
286 phy-names = "usb";
287 extcon = <&usbphy 0>;
288 dr_mode = "otg";
289 status = "disabled";
290 };
291
292 usbphy: phy@1c19400 {
293 /*
294 * compatible and addr
295 * SoC specific dtsi f
296 */
297 clocks = <&ccu CLK_USB
298 <&ccu CLK_USB
299 clock-names = "usb0_ph
300 "usb1_ph
301 resets = <&ccu RST_USB
302 <&ccu RST_USB
303 reset-names = "usb0_re
304 "usb1_re
305 status = "disabled";
306 #phy-cells = <1>;
307 };
308
309 ehci0: usb@1c1a000 {
310 compatible = "allwinne
311 reg = <0x01c1a000 0x10
312 interrupts = <GIC_SPI
313 clocks = <&ccu CLK_BUS
314 resets = <&ccu RST_BUS
315 phys = <&usbphy 1>;
316 phy-names = "usb";
317 status = "disabled";
318 };
319
320 ohci0: usb@1c1a400 {
321 compatible = "allwinne
322 reg = <0x01c1a400 0x10
323 interrupts = <GIC_SPI
324 clocks = <&ccu CLK_BUS
325 resets = <&ccu RST_BUS
326 phys = <&usbphy 1>;
327 phy-names = "usb";
328 status = "disabled";
329 };
330
331 ccu: clock@1c20000 {
332 reg = <0x01c20000 0x40
333 clocks = <&osc24M>, <&
334 clock-names = "hosc",
335 #clock-cells = <1>;
336 #reset-cells = <1>;
337 };
338
339 pio: pinctrl@1c20800 {
340 /* compatible gets set
341 reg = <0x01c20800 0x40
342 interrupt-parent = <&r
343 /* interrupts get set
344 clocks = <&ccu CLK_BUS
345 <&rtc CLK_OSC
346 clock-names = "apb", "
347 gpio-controller;
348 interrupt-controller;
349 #interrupt-cells = <3>
350 #gpio-cells = <3>;
351
352 i2c0_pins: i2c0-pins {
353 pins = "PH2",
354 function = "i2
355 };
356
357 i2c1_pins: i2c1-pins {
358 pins = "PH4",
359 function = "i2
360 };
361
362 i2c2_pins: i2c2-pins {
363 pins = "PE12",
364 function = "i2
365 };
366
367 lcd_rgb666_pins: lcd-r
368 pins = "PD2",
369 "PD10",
370 "PD18",
371 "PD24",
372 function = "lc
373 };
374
375 mmc0_pins: mmc0-pins {
376 pins = "PF0",
377 "PF3",
378 function = "mm
379 drive-strength
380 bias-pull-up;
381 };
382
383 mmc1_pg_pins: mmc1-pg-
384 pins = "PG0",
385 "PG3",
386 function = "mm
387 drive-strength
388 bias-pull-up;
389 };
390
391 mmc2_8bit_pins: mmc2-8
392 pins = "PC5",
393 "PC9",
394 "PC12",
395 "PC15",
396 function = "mm
397 drive-strength
398 bias-pull-up;
399 };
400
401 nand_pins: nand-pins {
402 pins = "PC0",
403 "PC8",
404 "PC12",
405 function = "na
406 };
407
408 nand_cs0_pin: nand-cs0
409 pins = "PC4";
410 function = "na
411 bias-pull-up;
412 };
413
414 nand_cs1_pin: nand-cs1
415 pins = "PC3";
416 function = "na
417 bias-pull-up;
418 };
419
420 nand_rb0_pin: nand-rb0
421 pins = "PC6";
422 function = "na
423 bias-pull-up;
424 };
425
426 nand_rb1_pin: nand-rb1
427 pins = "PC7";
428 function = "na
429 bias-pull-up;
430 };
431
432 pwm0_pin: pwm0-pin {
433 pins = "PH0";
434 function = "pw
435 };
436
437 uart0_pf_pins: uart0-p
438 pins = "PF2",
439 function = "ua
440 };
441
442 uart1_pg_pins: uart1-p
443 pins = "PG6",
444 function = "ua
445 };
446
447 uart1_cts_rts_pg_pins:
448 pins = "PG8",
449 function = "ua
450 };
451 };
452
453 timer@1c20c00 {
454 compatible = "allwinne
455 reg = <0x01c20c00 0xa0
456 interrupts = <GIC_SPI
457 <GIC_SPI
458 clocks = <&osc24M>;
459 };
460
461 wdt0: watchdog@1c20ca0 {
462 compatible = "allwinne
463 reg = <0x01c20ca0 0x20
464 interrupts = <GIC_SPI
465 clocks = <&osc24M>;
466 };
467
468 pwm: pwm@1c21400 {
469 compatible = "allwinne
470 reg = <0x01c21400 0xc>
471 clocks = <&osc24M>;
472 #pwm-cells = <3>;
473 status = "disabled";
474 };
475
476 lradc: lradc@1c22800 {
477 compatible = "allwinne
478 reg = <0x01c22800 0x10
479 interrupt-parent = <&r
480 interrupts = <GIC_SPI
481 status = "disabled";
482 };
483
484 uart0: serial@1c28000 {
485 compatible = "snps,dw-
486 reg = <0x01c28000 0x40
487 interrupts = <GIC_SPI
488 reg-shift = <2>;
489 reg-io-width = <4>;
490 clocks = <&ccu CLK_BUS
491 resets = <&ccu RST_BUS
492 dmas = <&dma 6>, <&dma
493 dma-names = "tx", "rx"
494 status = "disabled";
495 };
496
497 uart1: serial@1c28400 {
498 compatible = "snps,dw-
499 reg = <0x01c28400 0x40
500 interrupts = <GIC_SPI
501 reg-shift = <2>;
502 reg-io-width = <4>;
503 clocks = <&ccu CLK_BUS
504 resets = <&ccu RST_BUS
505 dmas = <&dma 7>, <&dma
506 dma-names = "tx", "rx"
507 status = "disabled";
508 };
509
510 uart2: serial@1c28800 {
511 compatible = "snps,dw-
512 reg = <0x01c28800 0x40
513 interrupts = <GIC_SPI
514 reg-shift = <2>;
515 reg-io-width = <4>;
516 clocks = <&ccu CLK_BUS
517 resets = <&ccu RST_BUS
518 dmas = <&dma 8>, <&dma
519 dma-names = "tx", "rx"
520 status = "disabled";
521 };
522
523 uart3: serial@1c28c00 {
524 compatible = "snps,dw-
525 reg = <0x01c28c00 0x40
526 interrupts = <GIC_SPI
527 reg-shift = <2>;
528 reg-io-width = <4>;
529 clocks = <&ccu CLK_BUS
530 resets = <&ccu RST_BUS
531 dmas = <&dma 9>, <&dma
532 dma-names = "tx", "rx"
533 status = "disabled";
534 };
535
536 uart4: serial@1c29000 {
537 compatible = "snps,dw-
538 reg = <0x01c29000 0x40
539 interrupts = <GIC_SPI
540 reg-shift = <2>;
541 reg-io-width = <4>;
542 clocks = <&ccu CLK_BUS
543 resets = <&ccu RST_BUS
544 dmas = <&dma 10>, <&dm
545 dma-names = "tx", "rx"
546 status = "disabled";
547 };
548
549 i2c0: i2c@1c2ac00 {
550 compatible = "allwinne
551 reg = <0x01c2ac00 0x40
552 interrupts = <GIC_SPI
553 clocks = <&ccu CLK_BUS
554 resets = <&ccu RST_BUS
555 pinctrl-names = "defau
556 pinctrl-0 = <&i2c0_pin
557 status = "disabled";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 };
561
562 i2c1: i2c@1c2b000 {
563 compatible = "allwinne
564 reg = <0x01c2b000 0x40
565 interrupts = <GIC_SPI
566 clocks = <&ccu CLK_BUS
567 resets = <&ccu RST_BUS
568 pinctrl-names = "defau
569 pinctrl-0 = <&i2c1_pin
570 status = "disabled";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 };
574
575 i2c2: i2c@1c2b400 {
576 compatible = "allwinne
577 reg = <0x01c2b400 0x40
578 interrupts = <GIC_SPI
579 clocks = <&ccu CLK_BUS
580 resets = <&ccu RST_BUS
581 pinctrl-names = "defau
582 pinctrl-0 = <&i2c2_pin
583 status = "disabled";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 };
587
588 mali: gpu@1c40000 {
589 compatible = "allwinne
590 "allwinne
591 reg = <0x01c40000 0x10
592 interrupts = <GIC_SPI
593 <GIC_SPI
594 <GIC_SPI
595 <GIC_SPI
596 <GIC_SPI
597 <GIC_SPI
598 <GIC_SPI
599 interrupt-names = "gp"
600 "gpm
601 "pp0
602 "ppm
603 "pp1
604 "ppm
605 "pmu
606 clocks = <&ccu CLK_BUS
607 clock-names = "bus", "
608 resets = <&ccu RST_BUS
609 #cooling-cells = <2>;
610
611 assigned-clocks = <&cc
612 assigned-clock-rates =
613 };
614
615 gic: interrupt-controller@1c81
616 compatible = "arm,gic-
617 reg = <0x01c81000 0x10
618 <0x01c82000 0x20
619 <0x01c84000 0x20
620 <0x01c86000 0x20
621 interrupt-controller;
622 #interrupt-cells = <3>
623 interrupts = <GIC_PPI
624 };
625
626 fe0: display-frontend@1e00000
627 /* compatible gets set
628 reg = <0x01e00000 0x20
629 interrupts = <GIC_SPI
630 clocks = <&ccu CLK_BUS
631 <&ccu CLK_DRA
632 clock-names = "ahb", "
633 "ram";
634 resets = <&ccu RST_BUS
635
636 ports {
637 #address-cells
638 #size-cells =
639
640 fe0_out: port@
641 reg =
642
643 fe0_ou
644
645 };
646 };
647 };
648 };
649
650 be0: display-backend@1e60000 {
651 /* compatible gets set
652 reg = <0x01e60000 0x10
653 interrupts = <GIC_SPI
654 clocks = <&ccu CLK_BUS
655 <&ccu CLK_DRA
656 clock-names = "ahb", "
657 "ram";
658 resets = <&ccu RST_BUS
659
660 ports {
661 #address-cells
662 #size-cells =
663
664 be0_in: port@0
665 reg =
666
667 be0_in
668
669 };
670 };
671
672 be0_out: port@
673 reg =
674
675 be0_ou
676
677 };
678 };
679 };
680 };
681
682 drc0: drc@1e70000 {
683 /* compatible gets set
684 reg = <0x01e70000 0x10
685 interrupts = <GIC_SPI
686 clocks = <&ccu CLK_BUS
687 <&ccu CLK_DRA
688 clock-names = "ahb", "
689 resets = <&ccu RST_BUS
690
691 ports {
692 #address-cells
693 #size-cells =
694
695 drc0_in: port@
696 reg =
697
698 drc0_i
699
700 };
701 };
702
703 drc0_out: port
704 reg =
705
706 drc0_o
707
708 };
709 };
710 };
711 };
712
713 rtc: rtc@1f00000 {
714 compatible = "allwinne
715 reg = <0x01f00000 0x40
716 interrupt-parent = <&r
717 interrupts = <GIC_SPI
718 <GIC_SPI
719 clock-output-names = "
720 clocks = <&ext_osc32k>
721 #clock-cells = <1>;
722 };
723
724 r_intc: interrupt-controller@1
725 compatible = "allwinne
726 interrupt-controller;
727 #interrupt-cells = <3>
728 reg = <0x01f00c00 0x40
729 interrupts = <GIC_SPI
730 };
731
732 prcm@1f01400 {
733 compatible = "allwinne
734 reg = <0x01f01400 0x20
735
736 ar100: ar100-clk {
737 compatible = "
738 #clock-cells =
739 clock-div = <1
740 clock-mult = <
741 clocks = <&osc
742 clock-output-n
743 };
744
745 ahb0: ahb0-clk {
746 compatible = "
747 #clock-cells =
748 clock-div = <1
749 clock-mult = <
750 clocks = <&ar1
751 clock-output-n
752 };
753
754 apb0: apb0-clk {
755 compatible = "
756 #clock-cells =
757 clocks = <&ahb
758 clock-output-n
759 };
760
761 apb0_gates: apb0-gates
762 compatible = "
763 #clock-cells =
764 clocks = <&apb
765 clock-output-n
766
767
768 };
769
770 apb0_rst: apb0-rst {
771 compatible = "
772 #reset-cells =
773 };
774
775 codec_analog: codec-an
776 compatible = "
777 };
778 };
779
780 cpucfg@1f01c00 {
781 compatible = "allwinne
782 reg = <0x01f01c00 0x30
783 };
784
785 r_uart: serial@1f02800 {
786 compatible = "snps,dw-
787 reg = <0x01f02800 0x40
788 interrupts = <GIC_SPI
789 reg-shift = <2>;
790 reg-io-width = <4>;
791 clocks = <&apb0_gates
792 resets = <&apb0_rst 4>
793 status = "disabled";
794 };
795
796 r_i2c: i2c@1f02400 {
797 compatible = "allwinne
798 "allwinne
799 reg = <0x01f02400 0x40
800 interrupts = <GIC_SPI
801 pinctrl-names = "defau
802 pinctrl-0 = <&r_i2c_pi
803 clocks = <&apb0_gates
804 resets = <&apb0_rst 6>
805 status = "disabled";
806 #address-cells = <1>;
807 #size-cells = <0>;
808 };
809
810 r_pio: pinctrl@1f02c00 {
811 compatible = "allwinne
812 reg = <0x01f02c00 0x40
813 interrupt-parent = <&r
814 interrupts = <GIC_SPI
815 clocks = <&apb0_gates
816 clock-names = "apb", "
817 gpio-controller;
818 interrupt-controller;
819 #interrupt-cells = <3>
820 #gpio-cells = <3>;
821
822 r_i2c_pins: r-i2c-pins
823 pins = "PL0",
824 function = "s_
825 bias-pull-up;
826 };
827
828 r_rsb_pins: r-rsb-pins
829 pins = "PL0",
830 function = "s_
831 drive-strength
832 bias-pull-up;
833 };
834
835 r_uart_pins_a: r-uart-
836 pins = "PL2",
837 function = "s_
838 };
839 };
840
841 r_rsb: rsb@1f03400 {
842 compatible = "allwinne
843 reg = <0x01f03400 0x40
844 interrupts = <GIC_SPI
845 clocks = <&apb0_gates
846 clock-frequency = <300
847 resets = <&apb0_rst 3>
848 pinctrl-names = "defau
849 pinctrl-0 = <&r_rsb_pi
850 status = "disabled";
851 #address-cells = <1>;
852 #size-cells = <0>;
853 };
854 };
855 };
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