1 /*
2 * Copyright 2015 Vishnu Patekar
3 *
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * This file is dual-licensed: you can use it
7 * of the GPL or the X11 license, at your opti
8 * licensing only applies to this file, and no
9 * whole.
10 *
11 * a) This file is free software; you can red
12 * modify it under the terms of the GNU Ge
13 * published by the Free Software Foundati
14 * License, or (at your option) any later
15 *
16 * This file is distributed in the hope th
17 * but WITHOUT ANY WARRANTY; without even
18 * MERCHANTABILITY or FITNESS FOR A PARTIC
19 * GNU General Public License for more det
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of c
24 * obtaining a copy of this software and a
25 * files (the "Software"), to deal in the
26 * restriction, including without limitati
27 * copy, modify, merge, publish, distribut
28 * sell copies of the Software, and to per
29 * Software is furnished to do so, subject
30 * conditions:
31 *
32 * The above copyright notice and this per
33 * included in all copies or substantial p
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
40 * WHETHER IN AN ACTION OF CONTRACT, TORT
41 * FROM, OUT OF OR IN CONNECTION WITH THE
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include <dt-bindings/interrupt-controller/arm
46
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
54
55 / {
56 interrupt-parent = <&gic>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@0 {
65 compatible = "arm,cort
66 device_type = "cpu";
67 clocks = <&ccu CLK_C0C
68 operating-points-v2 =
69 cci-control-port = <&c
70 enable-method = "allwi
71 reg = <0>;
72 #cooling-cells = <2>;
73 };
74
75 cpu1: cpu@1 {
76 compatible = "arm,cort
77 device_type = "cpu";
78 clocks = <&ccu CLK_C0C
79 operating-points-v2 =
80 cci-control-port = <&c
81 enable-method = "allwi
82 reg = <1>;
83 #cooling-cells = <2>;
84 };
85
86 cpu2: cpu@2 {
87 compatible = "arm,cort
88 device_type = "cpu";
89 clocks = <&ccu CLK_C0C
90 operating-points-v2 =
91 cci-control-port = <&c
92 enable-method = "allwi
93 reg = <2>;
94 #cooling-cells = <2>;
95 };
96
97 cpu3: cpu@3 {
98 compatible = "arm,cort
99 device_type = "cpu";
100 clocks = <&ccu CLK_C0C
101 operating-points-v2 =
102 cci-control-port = <&c
103 enable-method = "allwi
104 reg = <3>;
105 #cooling-cells = <2>;
106 };
107
108 cpu100: cpu@100 {
109 compatible = "arm,cort
110 device_type = "cpu";
111 clocks = <&ccu CLK_C1C
112 operating-points-v2 =
113 cci-control-port = <&c
114 enable-method = "allwi
115 reg = <0x100>;
116 #cooling-cells = <2>;
117 };
118
119 cpu101: cpu@101 {
120 compatible = "arm,cort
121 device_type = "cpu";
122 clocks = <&ccu CLK_C1C
123 operating-points-v2 =
124 cci-control-port = <&c
125 enable-method = "allwi
126 reg = <0x101>;
127 #cooling-cells = <2>;
128 };
129
130 cpu102: cpu@102 {
131 compatible = "arm,cort
132 device_type = "cpu";
133 clocks = <&ccu CLK_C1C
134 operating-points-v2 =
135 cci-control-port = <&c
136 enable-method = "allwi
137 reg = <0x102>;
138 #cooling-cells = <2>;
139 };
140
141 cpu103: cpu@103 {
142 compatible = "arm,cort
143 device_type = "cpu";
144 clocks = <&ccu CLK_C1C
145 operating-points-v2 =
146 cci-control-port = <&c
147 enable-method = "allwi
148 reg = <0x103>;
149 #cooling-cells = <2>;
150 };
151 };
152
153 timer {
154 compatible = "arm,armv7-timer"
155 interrupts = <GIC_PPI 13 (GIC_
156 <GIC_PPI 14 (GIC_
157 <GIC_PPI 11 (GIC_
158 <GIC_PPI 10 (GIC_
159 };
160
161 clocks {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165
166 /* TODO: PRCM block has a mux
167 osc24M: osc24M-clk {
168 #clock-cells = <0>;
169 compatible = "fixed-cl
170 clock-frequency = <240
171 clock-accuracy = <5000
172 clock-output-names = "
173 };
174
175 /*
176 * This is called "internal OS
177 * It is an internal RC-based
178 * TODO: Its controls are in t
179 */
180 osc16M: osc16M-clk {
181 #clock-cells = <0>;
182 compatible = "fixed-cl
183 clock-frequency = <160
184 clock-output-names = "
185 };
186
187 osc16Md512: osc16Md512-clk {
188 #clock-cells = <0>;
189 compatible = "fixed-fa
190 clock-div = <512>;
191 clock-mult = <1>;
192 clocks = <&osc16M>;
193 clock-output-names = "
194 };
195 };
196
197 de: display-engine {
198 compatible = "allwinner,sun8i-
199 allwinner,pipelines = <&mixer0
200 status = "disabled";
201 };
202
203 cpu0_opp_table: opp-table-cluster0 {
204 compatible = "operating-points
205 opp-shared;
206
207 opp-480000000 {
208 opp-hz = /bits/ 64 <48
209 opp-microvolt = <84000
210 clock-latency-ns = <24
211 };
212
213 opp-600000000 {
214 opp-hz = /bits/ 64 <60
215 opp-microvolt = <84000
216 clock-latency-ns = <24
217 };
218
219 opp-720000000 {
220 opp-hz = /bits/ 64 <72
221 opp-microvolt = <84000
222 clock-latency-ns = <24
223 };
224
225 opp-864000000 {
226 opp-hz = /bits/ 64 <86
227 opp-microvolt = <84000
228 clock-latency-ns = <24
229 };
230
231 opp-912000000 {
232 opp-hz = /bits/ 64 <91
233 opp-microvolt = <84000
234 clock-latency-ns = <24
235 };
236
237 opp-1008000000 {
238 opp-hz = /bits/ 64 <10
239 opp-microvolt = <84000
240 clock-latency-ns = <24
241 };
242
243 opp-1128000000 {
244 opp-hz = /bits/ 64 <11
245 opp-microvolt = <84000
246 clock-latency-ns = <24
247 };
248
249 opp-1200000000 {
250 opp-hz = /bits/ 64 <12
251 opp-microvolt = <84000
252 clock-latency-ns = <24
253 };
254 };
255
256 cpu1_opp_table: opp-table-cluster1 {
257 compatible = "operating-points
258 opp-shared;
259
260 opp-480000000 {
261 opp-hz = /bits/ 64 <48
262 opp-microvolt = <84000
263 clock-latency-ns = <24
264 };
265
266 opp-600000000 {
267 opp-hz = /bits/ 64 <60
268 opp-microvolt = <84000
269 clock-latency-ns = <24
270 };
271
272 opp-720000000 {
273 opp-hz = /bits/ 64 <72
274 opp-microvolt = <84000
275 clock-latency-ns = <24
276 };
277
278 opp-864000000 {
279 opp-hz = /bits/ 64 <86
280 opp-microvolt = <84000
281 clock-latency-ns = <24
282 };
283
284 opp-912000000 {
285 opp-hz = /bits/ 64 <91
286 opp-microvolt = <84000
287 clock-latency-ns = <24
288 };
289
290 opp-1008000000 {
291 opp-hz = /bits/ 64 <10
292 opp-microvolt = <84000
293 clock-latency-ns = <24
294 };
295
296 opp-1128000000 {
297 opp-hz = /bits/ 64 <11
298 opp-microvolt = <84000
299 clock-latency-ns = <24
300 };
301
302 opp-1200000000 {
303 opp-hz = /bits/ 64 <12
304 opp-microvolt = <84000
305 clock-latency-ns = <24
306 };
307 };
308
309 soc {
310 compatible = "simple-bus";
311 #address-cells = <1>;
312 #size-cells = <1>;
313 ranges;
314
315 display_clocks: clock@1000000
316 compatible = "allwinne
317 reg = <0x01000000 0x10
318 clocks = <&ccu CLK_BUS
319 <&ccu CLK_PLL
320 clock-names = "bus",
321 "mod";
322 resets = <&ccu RST_BUS
323 #clock-cells = <1>;
324 #reset-cells = <1>;
325 };
326
327 rotate: rotate@1020000 {
328 compatible = "allwinne
329 reg = <0x1020000 0x100
330 interrupts = <GIC_SPI
331 clocks = <&display_clo
332 <&display_clo
333 clock-names = "bus",
334 "mod";
335 resets = <&display_clo
336 };
337
338 mixer0: mixer@1100000 {
339 compatible = "allwinne
340 reg = <0x01100000 0x10
341 clocks = <&display_clo
342 <&display_clo
343 clock-names = "bus",
344 "mod";
345 resets = <&display_clo
346
347 ports {
348 #address-cells
349 #size-cells =
350
351 mixer0_out: po
352 #addre
353 #size-
354 reg =
355
356 mixer0
357
358
359 };
360
361 mixer0
362
363
364 };
365 };
366 };
367 };
368
369 mixer1: mixer@1200000 {
370 compatible = "allwinne
371 reg = <0x01200000 0x10
372 clocks = <&display_clo
373 <&display_clo
374 clock-names = "bus",
375 "mod";
376 resets = <&display_clo
377
378 ports {
379 #address-cells
380 #size-cells =
381
382 mixer1_out: po
383 #addre
384 #size-
385 reg =
386
387 mixer1
388
389
390 };
391
392 mixer1
393
394
395 };
396 };
397 };
398 };
399
400 cpucfg@1700000 {
401 compatible = "allwinne
402 reg = <0x01700000 0x40
403 };
404
405 cci@1790000 {
406 compatible = "arm,cci-
407 #address-cells = <1>;
408 #size-cells = <1>;
409 reg = <0x01790000 0x10
410 ranges = <0x0 0x017900
411
412 cci_control0: slave-if
413 compatible = "
414 interface-type
415 reg = <0x4000
416 };
417
418 cci_control1: slave-if
419 compatible = "
420 interface-type
421 reg = <0x5000
422 };
423
424 pmu@9000 {
425 compatible = "
426 reg = <0x9000
427 interrupts = <
428 <
429 <
430 <
431 <
432 <
433 <
434 <
435 };
436 };
437
438 syscon: syscon@1c00000 {
439 compatible = "allwinne
440 "syscon";
441 reg = <0x01c00000 0x10
442 };
443
444 dma: dma-controller@1c02000 {
445 compatible = "allwinne
446 reg = <0x01c02000 0x10
447 interrupts = <GIC_SPI
448 clocks = <&ccu CLK_BUS
449 resets = <&ccu RST_BUS
450 #dma-cells = <1>;
451 };
452
453 tcon0: lcd-controller@1c0c000
454 compatible = "allwinne
455 reg = <0x01c0c000 0x10
456 interrupts = <GIC_SPI
457 clocks = <&ccu CLK_BUS
458 clock-names = "ahb", "
459 clock-output-names = "
460 #clock-cells = <0>;
461 resets = <&ccu RST_BUS
462 reset-names = "lcd", "
463
464 ports {
465 #address-cells
466 #size-cells =
467
468 tcon0_in: port
469 #addre
470 #size-
471 reg =
472
473 tcon0_
474
475
476 };
477
478 tcon0_
479
480
481 };
482 };
483
484 tcon0_out: por
485 reg =
486 };
487 };
488 };
489
490 tcon1: lcd-controller@1c0d000
491 compatible = "allwinne
492 reg = <0x01c0d000 0x10
493 interrupts = <GIC_SPI
494 clocks = <&ccu CLK_BUS
495 clock-names = "ahb", "
496 resets = <&ccu RST_BUS
497 reset-names = "lcd";
498
499 ports {
500 #address-cells
501 #size-cells =
502
503 tcon1_in: port
504 #addre
505 #size-
506 reg =
507
508 tcon1_
509
510
511 };
512
513 tcon1_
514
515
516 };
517 };
518
519 tcon1_out: por
520 #addre
521 #size-
522 reg =
523
524 tcon1_
525
526
527 };
528 };
529 };
530 };
531
532 mmc0: mmc@1c0f000 {
533 compatible = "allwinne
534 "allwinne
535 reg = <0x01c0f000 0x10
536 clocks = <&ccu CLK_BUS
537 <&ccu CLK_MMC
538 <&ccu CLK_MMC
539 <&ccu CLK_MMC
540 clock-names = "ahb",
541 "mmc",
542 "output"
543 "sample"
544 resets = <&ccu RST_BUS
545 reset-names = "ahb";
546 interrupts = <GIC_SPI
547 status = "disabled";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 };
551
552 mmc1: mmc@1c10000 {
553 compatible = "allwinne
554 "allwinne
555 reg = <0x01c10000 0x10
556 clocks = <&ccu CLK_BUS
557 <&ccu CLK_MMC
558 <&ccu CLK_MMC
559 <&ccu CLK_MMC
560 clock-names = "ahb",
561 "mmc",
562 "output"
563 "sample"
564 resets = <&ccu RST_BUS
565 reset-names = "ahb";
566 interrupts = <GIC_SPI
567 pinctrl-names = "defau
568 pinctrl-0 = <&mmc1_pin
569 status = "disabled";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 };
573
574 mmc2: mmc@1c11000 {
575 compatible = "allwinne
576 reg = <0x01c11000 0x10
577 clocks = <&ccu CLK_BUS
578 <&ccu CLK_MMC
579 <&ccu CLK_MMC
580 <&ccu CLK_MMC
581 clock-names = "ahb",
582 "mmc",
583 "output"
584 "sample"
585 resets = <&ccu RST_BUS
586 reset-names = "ahb";
587 interrupts = <GIC_SPI
588 status = "disabled";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 };
592
593 sid: eeprom@1c14000 {
594 compatible = "allwinne
595 reg = <0x1c14000 0x400
596 #address-cells = <1>;
597 #size-cells = <1>;
598
599 ths_calibration: therm
600 reg = <0x34 8>
601 };
602 };
603
604 crypto: crypto@1c15000 {
605 compatible = "allwinne
606 reg = <0x01c15000 0x10
607 interrupts = <GIC_SPI
608 resets = <&ccu RST_BUS
609 clocks = <&ccu CLK_BUS
610 clock-names = "bus", "
611 };
612
613 msgbox: mailbox@1c17000 {
614 compatible = "allwinne
615 "allwinne
616 reg = <0x01c17000 0x10
617 clocks = <&ccu CLK_BUS
618 resets = <&ccu RST_BUS
619 interrupts = <GIC_SPI
620 #mbox-cells = <1>;
621 };
622
623 usb_otg: usb@1c19000 {
624 compatible = "allwinne
625 "allwinne
626 reg = <0x01c19000 0x04
627 clocks = <&ccu CLK_BUS
628 resets = <&ccu RST_BUS
629 interrupts = <GIC_SPI
630 interrupt-names = "mc"
631 phys = <&usbphy 0>;
632 phy-names = "usb";
633 extcon = <&usbphy 0>;
634 dr_mode = "otg";
635 status = "disabled";
636 };
637
638 usbphy: phy@1c19400 {
639 compatible = "allwinne
640 reg = <0x01c19400 0x10
641 <0x01c1a800 0x14
642 <0x01c1b800 0x14
643 reg-names = "phy_ctrl"
644 "pmu1",
645 "pmu2";
646 clocks = <&ccu CLK_USB
647 <&ccu CLK_USB
648 <&ccu CLK_USB
649 <&ccu CLK_USB
650 clock-names = "usb0_ph
651 "usb1_ph
652 "usb2_ph
653 "usb2_hs
654 resets = <&ccu RST_USB
655 <&ccu RST_USB
656 <&ccu RST_USB
657 reset-names = "usb0_re
658 "usb1_re
659 "usb2_re
660 status = "disabled";
661 #phy-cells = <1>;
662 };
663
664 ehci0: usb@1c1a000 {
665 compatible = "allwinne
666 "generic-
667 reg = <0x01c1a000 0x10
668 interrupts = <GIC_SPI
669 clocks = <&ccu CLK_BUS
670 resets = <&ccu RST_BUS
671 phys = <&usbphy 1>;
672 phy-names = "usb";
673 status = "disabled";
674 };
675
676 ohci0: usb@1c1a400 {
677 compatible = "allwinne
678 "generic-
679 reg = <0x01c1a400 0x10
680 interrupts = <GIC_SPI
681 clocks = <&ccu CLK_BUS
682 resets = <&ccu RST_BUS
683 phys = <&usbphy 1>;
684 phy-names = "usb";
685 status = "disabled";
686 };
687
688 ehci1: usb@1c1b000 {
689 compatible = "allwinne
690 "generic-
691 reg = <0x01c1b000 0x10
692 interrupts = <GIC_SPI
693 clocks = <&ccu CLK_BUS
694 resets = <&ccu RST_BUS
695 phys = <&usbphy 2>;
696 phy-names = "usb";
697 status = "disabled";
698 };
699
700 ccu: clock@1c20000 {
701 compatible = "allwinne
702 reg = <0x01c20000 0x40
703 clocks = <&osc24M>, <&
704 clock-names = "hosc",
705 #clock-cells = <1>;
706 #reset-cells = <1>;
707 };
708
709 pio: pinctrl@1c20800 {
710 compatible = "allwinne
711 interrupt-parent = <&r
712 interrupts = <GIC_SPI
713 <GIC_SPI
714 <GIC_SPI
715 reg = <0x01c20800 0x40
716 clocks = <&ccu CLK_BUS
717 clock-names = "apb", "
718 gpio-controller;
719 interrupt-controller;
720 #interrupt-cells = <3>
721 #gpio-cells = <3>;
722
723 /omit-if-no-ref/
724 csi_8bit_parallel_pins
725 pins = "PE0",
726 "PE8",
727 "PE12",
728 function = "cs
729 };
730
731 /omit-if-no-ref/
732 csi_mclk_pin: csi-mclk
733 pins = "PE1";
734 function = "cs
735 };
736
737 emac_rgmii_pins: emac-
738 pins = "PD2",
739 "PD11",
740 "PD19",
741 function = "gm
742 /*
743 * data lines
744 * and need a
745 */
746 drive-strength
747 };
748
749 hdmi_pins: hdmi-pins {
750 pins = "PH6",
751 function = "hd
752 };
753
754 i2c0_pins: i2c0-pins {
755 pins = "PH0",
756 function = "i2
757 };
758
759 i2c1_pins: i2c1-pins {
760 pins = "PH2",
761 function = "i2
762 };
763
764 /omit-if-no-ref/
765 i2c2_pe_pins: i2c2-pe-
766 pins = "PE14",
767 function = "i2
768 };
769
770 i2c2_ph_pins: i2c2-ph-
771 pins = "PH4",
772 function = "i2
773 };
774
775 i2s1_pins: i2s1-pins {
776 /* I2S1 does n
777 pins = "PG10",
778 function = "i2
779 };
780
781 lcd_lvds_pins: lcd-lvd
782 pins = "PD18",
783 "PD23",
784 function = "lv
785 };
786
787 mmc0_pins: mmc0-pins {
788 pins = "PF0",
789 "PF3",
790 function = "mm
791 drive-strength
792 bias-pull-up;
793 };
794
795 mmc1_pins: mmc1-pins {
796 pins = "PG0",
797 "PG3",
798 function = "mm
799 drive-strength
800 bias-pull-up;
801 };
802
803 mmc2_8bit_emmc_pins: m
804 pins = "PC5",
805 "PC10",
806 "PC14",
807 function = "mm
808 drive-strength
809 bias-pull-up;
810 };
811
812 pwm_pin: pwm-pin {
813 pins = "PD28";
814 function = "pw
815 };
816
817 spdif_tx_pin: spdif-tx
818 pins = "PE18";
819 function = "sp
820 };
821
822 uart0_pb_pins: uart0-p
823 pins = "PB9",
824 function = "ua
825 };
826
827 uart0_pf_pins: uart0-p
828 pins = "PF2",
829 function = "ua
830 };
831
832 uart1_pins: uart1-pins
833 pins = "PG6",
834 function = "ua
835 };
836
837 uart1_rts_cts_pins: ua
838 pins = "PG8",
839 function = "ua
840 };
841
842 /omit-if-no-ref/
843 uart2_pb_pins: uart2-p
844 pins = "PB0",
845 function = "ua
846 };
847 };
848
849 timer@1c20c00 {
850 compatible = "allwinne
851 reg = <0x01c20c00 0xa0
852 interrupts = <GIC_SPI
853 <GIC_SPI
854 clocks = <&osc24M>;
855 };
856
857 watchdog@1c20ca0 {
858 compatible = "allwinne
859 reg = <0x01c20ca0 0x20
860 interrupts = <GIC_SPI
861 clocks = <&osc24M>;
862 };
863
864 spdif: spdif@1c21000 {
865 #sound-dai-cells = <0>
866 compatible = "allwinne
867 "allwinne
868 reg = <0x01c21000 0x40
869 interrupts = <GIC_SPI
870 clocks = <&ccu CLK_BUS
871 resets = <&ccu RST_BUS
872 clock-names = "apb", "
873 dmas = <&dma 2>;
874 dma-names = "tx";
875 pinctrl-names = "defau
876 pinctrl-0 = <&spdif_tx
877 status = "disabled";
878 };
879
880 i2s0: i2s@1c22000 {
881 #sound-dai-cells = <0>
882 compatible = "allwinne
883 reg = <0x01c22000 0x40
884 interrupts = <GIC_SPI
885 clocks = <&ccu CLK_BUS
886 clock-names = "apb", "
887 dmas = <&dma 3>, <&dma
888 resets = <&ccu RST_BUS
889 dma-names = "rx", "tx"
890 status = "disabled";
891 };
892
893 i2s1: i2s@1c22400 {
894 #sound-dai-cells = <0>
895 compatible = "allwinne
896 reg = <0x01c22400 0x40
897 interrupts = <GIC_SPI
898 clocks = <&ccu CLK_BUS
899 clock-names = "apb", "
900 dmas = <&dma 4>, <&dma
901 resets = <&ccu RST_BUS
902 dma-names = "rx", "tx"
903 pinctrl-names = "defau
904 pinctrl-0 = <&i2s1_pin
905 status = "disabled";
906 };
907
908 i2s2: i2s@1c22800 {
909 #sound-dai-cells = <0>
910 compatible = "allwinne
911 reg = <0x01c22800 0x40
912 interrupts = <GIC_SPI
913 clocks = <&ccu CLK_BUS
914 clock-names = "apb", "
915 dmas = <&dma 27>;
916 resets = <&ccu RST_BUS
917 dma-names = "tx";
918 status = "disabled";
919 };
920
921 pwm: pwm@1c21400 {
922 compatible = "allwinne
923 "allwinne
924 reg = <0x01c21400 0x40
925 clocks = <&osc24M>;
926 #pwm-cells = <3>;
927 status = "disabled";
928 };
929
930 uart0: serial@1c28000 {
931 compatible = "snps,dw-
932 reg = <0x01c28000 0x40
933 interrupts = <GIC_SPI
934 reg-shift = <2>;
935 reg-io-width = <4>;
936 clocks = <&ccu CLK_BUS
937 resets = <&ccu RST_BUS
938 status = "disabled";
939 };
940
941 uart1: serial@1c28400 {
942 compatible = "snps,dw-
943 reg = <0x01c28400 0x40
944 interrupts = <GIC_SPI
945 reg-shift = <2>;
946 reg-io-width = <4>;
947 clocks = <&ccu CLK_BUS
948 resets = <&ccu RST_BUS
949 status = "disabled";
950 };
951
952 uart2: serial@1c28800 {
953 compatible = "snps,dw-
954 reg = <0x01c28800 0x40
955 interrupts = <GIC_SPI
956 reg-shift = <2>;
957 reg-io-width = <4>;
958 clocks = <&ccu CLK_BUS
959 resets = <&ccu RST_BUS
960 status = "disabled";
961 };
962
963 uart3: serial@1c28c00 {
964 compatible = "snps,dw-
965 reg = <0x01c28c00 0x40
966 interrupts = <GIC_SPI
967 reg-shift = <2>;
968 reg-io-width = <4>;
969 clocks = <&ccu CLK_BUS
970 resets = <&ccu RST_BUS
971 status = "disabled";
972 };
973
974 uart4: serial@1c29000 {
975 compatible = "snps,dw-
976 reg = <0x01c29000 0x40
977 interrupts = <GIC_SPI
978 reg-shift = <2>;
979 reg-io-width = <4>;
980 clocks = <&ccu CLK_BUS
981 resets = <&ccu RST_BUS
982 status = "disabled";
983 };
984
985 i2c0: i2c@1c2ac00 {
986 compatible = "allwinne
987 "allwinne
988 reg = <0x01c2ac00 0x40
989 interrupts = <GIC_SPI
990 clocks = <&ccu CLK_BUS
991 resets = <&ccu RST_BUS
992 pinctrl-names = "defau
993 pinctrl-0 = <&i2c0_pin
994 status = "disabled";
995 #address-cells = <1>;
996 #size-cells = <0>;
997 };
998
999 i2c1: i2c@1c2b000 {
1000 compatible = "allwinn
1001 "allwinn
1002 reg = <0x01c2b000 0x4
1003 interrupts = <GIC_SPI
1004 clocks = <&ccu CLK_BU
1005 resets = <&ccu RST_BU
1006 pinctrl-names = "defa
1007 pinctrl-0 = <&i2c1_pi
1008 status = "disabled";
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 };
1012
1013 i2c2: i2c@1c2b400 {
1014 compatible = "allwinn
1015 "allwinn
1016 reg = <0x01c2b400 0x4
1017 interrupts = <GIC_SPI
1018 clocks = <&ccu CLK_BU
1019 resets = <&ccu RST_BU
1020 status = "disabled";
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024
1025 emac: ethernet@1c30000 {
1026 compatible = "allwinn
1027 syscon = <&syscon>;
1028 reg = <0x01c30000 0x1
1029 interrupts = <GIC_SPI
1030 interrupt-names = "ma
1031 clocks = <&ccu CLK_BU
1032 clock-names = "stmmac
1033 resets = <&ccu RST_BU
1034 reset-names = "stmmac
1035 status = "disabled";
1036
1037 mdio: mdio {
1038 compatible =
1039 #address-cell
1040 #size-cells =
1041 };
1042 };
1043
1044 gic: interrupt-controller@1c8
1045 compatible = "arm,gic
1046 reg = <0x01c81000 0x1
1047 <0x01c82000 0x2
1048 <0x01c84000 0x2
1049 <0x01c86000 0x2
1050 interrupt-controller;
1051 #interrupt-cells = <3
1052 interrupts = <GIC_PPI
1053 };
1054
1055 csi: camera@1cb0000 {
1056 compatible = "allwinn
1057 reg = <0x01cb0000 0x1
1058 interrupts = <GIC_SPI
1059 clocks = <&ccu CLK_BU
1060 <&ccu CLK_CS
1061 <&ccu CLK_DR
1062 clock-names = "bus",
1063 resets = <&ccu RST_BU
1064 status = "disabled";
1065 };
1066
1067 hdmi: hdmi@1ee0000 {
1068 compatible = "allwinn
1069 reg = <0x01ee0000 0x1
1070 reg-io-width = <1>;
1071 interrupts = <GIC_SPI
1072 clocks = <&ccu CLK_BU
1073 <&ccu CLK_HD
1074 clock-names = "iahb",
1075 resets = <&ccu RST_BU
1076 reset-names = "ctrl";
1077 phys = <&hdmi_phy>;
1078 phy-names = "phy";
1079 pinctrl-names = "defa
1080 pinctrl-0 = <&hdmi_pi
1081 status = "disabled";
1082
1083 ports {
1084 #address-cell
1085 #size-cells =
1086
1087 hdmi_in: port
1088 reg =
1089
1090 hdmi_
1091
1092 };
1093 };
1094
1095 hdmi_out: por
1096 reg =
1097 };
1098 };
1099 };
1100
1101 hdmi_phy: hdmi-phy@1ef0000 {
1102 compatible = "allwinn
1103 reg = <0x01ef0000 0x1
1104 clocks = <&ccu CLK_BU
1105 clock-names = "bus",
1106 resets = <&ccu RST_BU
1107 reset-names = "phy";
1108 #phy-cells = <0>;
1109 };
1110
1111 r_intc: interrupt-controller@
1112 compatible = "allwinn
1113 "allwinn
1114 interrupt-controller;
1115 #interrupt-cells = <3
1116 reg = <0x01f00c00 0x4
1117 interrupts = <GIC_SPI
1118 };
1119
1120 r_ccu: clock@1f01400 {
1121 compatible = "allwinn
1122 reg = <0x01f01400 0x4
1123 clocks = <&osc24M>, <
1124 <&ccu CLK_PL
1125 clock-names = "hosc",
1126 #clock-cells = <1>;
1127 #reset-cells = <1>;
1128 };
1129
1130 cpucfg@1f01c00 {
1131 compatible = "allwinn
1132 reg = <0x1f01c00 0x40
1133 };
1134
1135 r_cir: ir@1f02000 {
1136 compatible = "allwinn
1137 "allwinner,su
1138 clocks = <&r_ccu CLK_
1139 clock-names = "apb",
1140 resets = <&r_ccu RST_
1141 interrupts = <GIC_SPI
1142 reg = <0x01f02000 0x4
1143 pinctrl-names = "defa
1144 pinctrl-0 = <&r_cir_p
1145 status = "disabled";
1146 };
1147
1148 r_lradc: lradc@1f03c00 {
1149 compatible = "allwinn
1150 reg = <0x01f03c00 0x1
1151 interrupt-parent = <&
1152 interrupts = <GIC_SPI
1153 status = "disabled";
1154 };
1155
1156 r_pio: pinctrl@1f02c00 {
1157 compatible = "allwinn
1158 reg = <0x01f02c00 0x4
1159 interrupt-parent = <&
1160 interrupts = <GIC_SPI
1161 clocks = <&r_ccu CLK_
1162 <&osc16Md512
1163 clock-names = "apb",
1164 gpio-controller;
1165 #gpio-cells = <3>;
1166 interrupt-controller;
1167 #interrupt-cells = <3
1168
1169 r_cir_pin: r-cir-pin
1170 pins = "PL12"
1171 function = "s
1172 };
1173
1174 r_rsb_pins: r-rsb-pin
1175 pins = "PL0",
1176 function = "s
1177 drive-strengt
1178 bias-pull-up;
1179 };
1180 };
1181
1182 r_rsb: rsb@1f03400 {
1183 compatible = "allwinn
1184 "allwinn
1185 reg = <0x01f03400 0x4
1186 interrupts = <GIC_SPI
1187 clocks = <&r_ccu CLK_
1188 clock-frequency = <30
1189 resets = <&r_ccu RST_
1190 pinctrl-names = "defa
1191 pinctrl-0 = <&r_rsb_p
1192 status = "disabled";
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195 };
1196
1197 ths: thermal-sensor@1f04000 {
1198 compatible = "allwinn
1199 reg = <0x01f04000 0x1
1200 interrupts = <GIC_SPI
1201 nvmem-cells = <&ths_c
1202 nvmem-cell-names = "c
1203 #thermal-sensor-cells
1204 };
1205 };
1206
1207 thermal-zones {
1208 cpu0_thermal: cpu0-thermal {
1209 polling-delay-passive
1210 polling-delay = <0>;
1211 thermal-sensors = <&t
1212
1213 trips {
1214 cpu0_hot: cpu
1215 tempe
1216 hyste
1217 type
1218 };
1219
1220 cpu0_very_hot
1221 tempe
1222 hyste
1223 type
1224 };
1225 };
1226
1227 cooling-maps {
1228 cpu-hot-limit
1229 trip
1230 cooli
1231
1232
1233
1234 };
1235 };
1236 };
1237
1238 cpu1_thermal: cpu1-thermal {
1239 polling-delay-passive
1240 polling-delay = <0>;
1241 thermal-sensors = <&t
1242
1243 trips {
1244 cpu1_hot: cpu
1245 tempe
1246 hyste
1247 type
1248 };
1249
1250 cpu1_very_hot
1251 tempe
1252 hyste
1253 type
1254 };
1255 };
1256
1257 cooling-maps {
1258 cpu-hot-limit
1259 trip
1260 cooli
1261
1262
1263
1264 };
1265 };
1266 };
1267
1268 gpu_thermal: gpu-thermal {
1269 polling-delay-passive
1270 polling-delay = <0>;
1271 thermal-sensors = <&t
1272 };
1273 };
1274 };
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