1 /* 1 /*
2 * Copyright 2015 Vishnu Patekar 2 * Copyright 2015 Vishnu Patekar
3 * 3 *
4 * Vishnu Patekar <vishnupatekar0510@gmail.com> 4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
5 * 5 *
6 * This file is dual-licensed: you can use it 6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your opti 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and no 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This file is free software; you can red 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Ge 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundati 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later 14 * License, or (at your option) any later version.
15 * 15 *
16 * This file is distributed in the hope th 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTIC 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more det 19 * GNU General Public License for more details.
20 * 20 *
21 * Or, alternatively, 21 * Or, alternatively,
22 * 22 *
23 * b) Permission is hereby granted, free of c 23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and a 24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the 25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitati 26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribut 27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to per 28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject 29 * Software is furnished to do so, subject to the following
30 * conditions: 30 * conditions:
31 * 31 *
32 * The above copyright notice and this per 32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial p 33 * included in all copies or substantial portions of the Software.
34 * 34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45 #include <dt-bindings/interrupt-controller/arm 45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 46
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h> 47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h> 48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h> 49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h> 50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h> 51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h> 52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h> 53 #include <dt-bindings/thermal/thermal.h>
54 54
55 / { 55 / {
56 interrupt-parent = <&gic>; 56 interrupt-parent = <&gic>;
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <1>; 58 #size-cells = <1>;
59 59
60 cpus { 60 cpus {
61 #address-cells = <1>; 61 #address-cells = <1>;
62 #size-cells = <0>; 62 #size-cells = <0>;
63 63
64 cpu0: cpu@0 { 64 cpu0: cpu@0 {
65 compatible = "arm,cort 65 compatible = "arm,cortex-a7";
66 device_type = "cpu"; 66 device_type = "cpu";
67 clocks = <&ccu CLK_C0C 67 clocks = <&ccu CLK_C0CPUX>;
68 operating-points-v2 = 68 operating-points-v2 = <&cpu0_opp_table>;
69 cci-control-port = <&c 69 cci-control-port = <&cci_control0>;
70 enable-method = "allwi 70 enable-method = "allwinner,sun8i-a83t-smp";
71 reg = <0>; 71 reg = <0>;
72 #cooling-cells = <2>; 72 #cooling-cells = <2>;
73 }; 73 };
74 74
75 cpu1: cpu@1 { 75 cpu1: cpu@1 {
76 compatible = "arm,cort 76 compatible = "arm,cortex-a7";
77 device_type = "cpu"; 77 device_type = "cpu";
78 clocks = <&ccu CLK_C0C 78 clocks = <&ccu CLK_C0CPUX>;
79 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
80 cci-control-port = <&c 80 cci-control-port = <&cci_control0>;
81 enable-method = "allwi 81 enable-method = "allwinner,sun8i-a83t-smp";
82 reg = <1>; 82 reg = <1>;
83 #cooling-cells = <2>; 83 #cooling-cells = <2>;
84 }; 84 };
85 85
86 cpu2: cpu@2 { 86 cpu2: cpu@2 {
87 compatible = "arm,cort 87 compatible = "arm,cortex-a7";
88 device_type = "cpu"; 88 device_type = "cpu";
89 clocks = <&ccu CLK_C0C 89 clocks = <&ccu CLK_C0CPUX>;
90 operating-points-v2 = 90 operating-points-v2 = <&cpu0_opp_table>;
91 cci-control-port = <&c 91 cci-control-port = <&cci_control0>;
92 enable-method = "allwi 92 enable-method = "allwinner,sun8i-a83t-smp";
93 reg = <2>; 93 reg = <2>;
94 #cooling-cells = <2>; 94 #cooling-cells = <2>;
95 }; 95 };
96 96
97 cpu3: cpu@3 { 97 cpu3: cpu@3 {
98 compatible = "arm,cort 98 compatible = "arm,cortex-a7";
99 device_type = "cpu"; 99 device_type = "cpu";
100 clocks = <&ccu CLK_C0C 100 clocks = <&ccu CLK_C0CPUX>;
101 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
102 cci-control-port = <&c 102 cci-control-port = <&cci_control0>;
103 enable-method = "allwi 103 enable-method = "allwinner,sun8i-a83t-smp";
104 reg = <3>; 104 reg = <3>;
105 #cooling-cells = <2>; 105 #cooling-cells = <2>;
106 }; 106 };
107 107
108 cpu100: cpu@100 { 108 cpu100: cpu@100 {
109 compatible = "arm,cort 109 compatible = "arm,cortex-a7";
110 device_type = "cpu"; 110 device_type = "cpu";
111 clocks = <&ccu CLK_C1C 111 clocks = <&ccu CLK_C1CPUX>;
112 operating-points-v2 = 112 operating-points-v2 = <&cpu1_opp_table>;
113 cci-control-port = <&c 113 cci-control-port = <&cci_control1>;
114 enable-method = "allwi 114 enable-method = "allwinner,sun8i-a83t-smp";
115 reg = <0x100>; 115 reg = <0x100>;
116 #cooling-cells = <2>; 116 #cooling-cells = <2>;
117 }; 117 };
118 118
119 cpu101: cpu@101 { 119 cpu101: cpu@101 {
120 compatible = "arm,cort 120 compatible = "arm,cortex-a7";
121 device_type = "cpu"; 121 device_type = "cpu";
122 clocks = <&ccu CLK_C1C 122 clocks = <&ccu CLK_C1CPUX>;
123 operating-points-v2 = 123 operating-points-v2 = <&cpu1_opp_table>;
124 cci-control-port = <&c 124 cci-control-port = <&cci_control1>;
125 enable-method = "allwi 125 enable-method = "allwinner,sun8i-a83t-smp";
126 reg = <0x101>; 126 reg = <0x101>;
127 #cooling-cells = <2>; 127 #cooling-cells = <2>;
128 }; 128 };
129 129
130 cpu102: cpu@102 { 130 cpu102: cpu@102 {
131 compatible = "arm,cort 131 compatible = "arm,cortex-a7";
132 device_type = "cpu"; 132 device_type = "cpu";
133 clocks = <&ccu CLK_C1C 133 clocks = <&ccu CLK_C1CPUX>;
134 operating-points-v2 = 134 operating-points-v2 = <&cpu1_opp_table>;
135 cci-control-port = <&c 135 cci-control-port = <&cci_control1>;
136 enable-method = "allwi 136 enable-method = "allwinner,sun8i-a83t-smp";
137 reg = <0x102>; 137 reg = <0x102>;
138 #cooling-cells = <2>; 138 #cooling-cells = <2>;
139 }; 139 };
140 140
141 cpu103: cpu@103 { 141 cpu103: cpu@103 {
142 compatible = "arm,cort 142 compatible = "arm,cortex-a7";
143 device_type = "cpu"; 143 device_type = "cpu";
144 clocks = <&ccu CLK_C1C 144 clocks = <&ccu CLK_C1CPUX>;
145 operating-points-v2 = 145 operating-points-v2 = <&cpu1_opp_table>;
146 cci-control-port = <&c 146 cci-control-port = <&cci_control1>;
147 enable-method = "allwi 147 enable-method = "allwinner,sun8i-a83t-smp";
148 reg = <0x103>; 148 reg = <0x103>;
149 #cooling-cells = <2>; 149 #cooling-cells = <2>;
150 }; 150 };
151 }; 151 };
152 152
153 timer { 153 timer {
154 compatible = "arm,armv7-timer" 154 compatible = "arm,armv7-timer";
155 interrupts = <GIC_PPI 13 (GIC_ 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 14 (GIC_ 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 11 (GIC_ 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
158 <GIC_PPI 10 (GIC_ 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
159 }; 159 };
160 160
161 clocks { 161 clocks {
162 #address-cells = <1>; 162 #address-cells = <1>;
163 #size-cells = <1>; 163 #size-cells = <1>;
164 ranges; 164 ranges;
165 165
166 /* TODO: PRCM block has a mux 166 /* TODO: PRCM block has a mux for this. */
167 osc24M: osc24M-clk { 167 osc24M: osc24M-clk {
168 #clock-cells = <0>; 168 #clock-cells = <0>;
169 compatible = "fixed-cl 169 compatible = "fixed-clock";
170 clock-frequency = <240 170 clock-frequency = <24000000>;
171 clock-accuracy = <5000 171 clock-accuracy = <50000>;
172 clock-output-names = " 172 clock-output-names = "osc24M";
173 }; 173 };
174 174
175 /* 175 /*
176 * This is called "internal OS 176 * This is called "internal OSC" in some places.
177 * It is an internal RC-based 177 * It is an internal RC-based oscillator.
178 * TODO: Its controls are in t 178 * TODO: Its controls are in the PRCM block.
179 */ 179 */
180 osc16M: osc16M-clk { 180 osc16M: osc16M-clk {
181 #clock-cells = <0>; 181 #clock-cells = <0>;
182 compatible = "fixed-cl 182 compatible = "fixed-clock";
183 clock-frequency = <160 183 clock-frequency = <16000000>;
184 clock-output-names = " 184 clock-output-names = "osc16M";
185 }; 185 };
186 186
187 osc16Md512: osc16Md512-clk { 187 osc16Md512: osc16Md512-clk {
188 #clock-cells = <0>; 188 #clock-cells = <0>;
189 compatible = "fixed-fa 189 compatible = "fixed-factor-clock";
190 clock-div = <512>; 190 clock-div = <512>;
191 clock-mult = <1>; 191 clock-mult = <1>;
192 clocks = <&osc16M>; 192 clocks = <&osc16M>;
193 clock-output-names = " 193 clock-output-names = "osc16M-d512";
194 }; 194 };
195 }; 195 };
196 196
197 de: display-engine { 197 de: display-engine {
198 compatible = "allwinner,sun8i- 198 compatible = "allwinner,sun8i-a83t-display-engine";
199 allwinner,pipelines = <&mixer0 199 allwinner,pipelines = <&mixer0>, <&mixer1>;
200 status = "disabled"; 200 status = "disabled";
201 }; 201 };
202 202
203 cpu0_opp_table: opp-table-cluster0 { 203 cpu0_opp_table: opp-table-cluster0 {
204 compatible = "operating-points 204 compatible = "operating-points-v2";
205 opp-shared; 205 opp-shared;
206 206
207 opp-480000000 { 207 opp-480000000 {
208 opp-hz = /bits/ 64 <48 208 opp-hz = /bits/ 64 <480000000>;
209 opp-microvolt = <84000 209 opp-microvolt = <840000>;
210 clock-latency-ns = <24 210 clock-latency-ns = <244144>; /* 8 32k periods */
211 }; 211 };
212 212
213 opp-600000000 { 213 opp-600000000 {
214 opp-hz = /bits/ 64 <60 214 opp-hz = /bits/ 64 <600000000>;
215 opp-microvolt = <84000 215 opp-microvolt = <840000>;
216 clock-latency-ns = <24 216 clock-latency-ns = <244144>; /* 8 32k periods */
217 }; 217 };
218 218
219 opp-720000000 { 219 opp-720000000 {
220 opp-hz = /bits/ 64 <72 220 opp-hz = /bits/ 64 <720000000>;
221 opp-microvolt = <84000 221 opp-microvolt = <840000>;
222 clock-latency-ns = <24 222 clock-latency-ns = <244144>; /* 8 32k periods */
223 }; 223 };
224 224
225 opp-864000000 { 225 opp-864000000 {
226 opp-hz = /bits/ 64 <86 226 opp-hz = /bits/ 64 <864000000>;
227 opp-microvolt = <84000 227 opp-microvolt = <840000>;
228 clock-latency-ns = <24 228 clock-latency-ns = <244144>; /* 8 32k periods */
229 }; 229 };
230 230
231 opp-912000000 { 231 opp-912000000 {
232 opp-hz = /bits/ 64 <91 232 opp-hz = /bits/ 64 <912000000>;
233 opp-microvolt = <84000 233 opp-microvolt = <840000>;
234 clock-latency-ns = <24 234 clock-latency-ns = <244144>; /* 8 32k periods */
235 }; 235 };
236 236
237 opp-1008000000 { 237 opp-1008000000 {
238 opp-hz = /bits/ 64 <10 238 opp-hz = /bits/ 64 <1008000000>;
239 opp-microvolt = <84000 239 opp-microvolt = <840000>;
240 clock-latency-ns = <24 240 clock-latency-ns = <244144>; /* 8 32k periods */
241 }; 241 };
242 242
243 opp-1128000000 { 243 opp-1128000000 {
244 opp-hz = /bits/ 64 <11 244 opp-hz = /bits/ 64 <1128000000>;
245 opp-microvolt = <84000 245 opp-microvolt = <840000>;
246 clock-latency-ns = <24 246 clock-latency-ns = <244144>; /* 8 32k periods */
247 }; 247 };
248 248
249 opp-1200000000 { 249 opp-1200000000 {
250 opp-hz = /bits/ 64 <12 250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <84000 251 opp-microvolt = <840000>;
252 clock-latency-ns = <24 252 clock-latency-ns = <244144>; /* 8 32k periods */
253 }; 253 };
254 }; 254 };
255 255
256 cpu1_opp_table: opp-table-cluster1 { 256 cpu1_opp_table: opp-table-cluster1 {
257 compatible = "operating-points 257 compatible = "operating-points-v2";
258 opp-shared; 258 opp-shared;
259 259
260 opp-480000000 { 260 opp-480000000 {
261 opp-hz = /bits/ 64 <48 261 opp-hz = /bits/ 64 <480000000>;
262 opp-microvolt = <84000 262 opp-microvolt = <840000>;
263 clock-latency-ns = <24 263 clock-latency-ns = <244144>; /* 8 32k periods */
264 }; 264 };
265 265
266 opp-600000000 { 266 opp-600000000 {
267 opp-hz = /bits/ 64 <60 267 opp-hz = /bits/ 64 <600000000>;
268 opp-microvolt = <84000 268 opp-microvolt = <840000>;
269 clock-latency-ns = <24 269 clock-latency-ns = <244144>; /* 8 32k periods */
270 }; 270 };
271 271
272 opp-720000000 { 272 opp-720000000 {
273 opp-hz = /bits/ 64 <72 273 opp-hz = /bits/ 64 <720000000>;
274 opp-microvolt = <84000 274 opp-microvolt = <840000>;
275 clock-latency-ns = <24 275 clock-latency-ns = <244144>; /* 8 32k periods */
276 }; 276 };
277 277
278 opp-864000000 { 278 opp-864000000 {
279 opp-hz = /bits/ 64 <86 279 opp-hz = /bits/ 64 <864000000>;
280 opp-microvolt = <84000 280 opp-microvolt = <840000>;
281 clock-latency-ns = <24 281 clock-latency-ns = <244144>; /* 8 32k periods */
282 }; 282 };
283 283
284 opp-912000000 { 284 opp-912000000 {
285 opp-hz = /bits/ 64 <91 285 opp-hz = /bits/ 64 <912000000>;
286 opp-microvolt = <84000 286 opp-microvolt = <840000>;
287 clock-latency-ns = <24 287 clock-latency-ns = <244144>; /* 8 32k periods */
288 }; 288 };
289 289
290 opp-1008000000 { 290 opp-1008000000 {
291 opp-hz = /bits/ 64 <10 291 opp-hz = /bits/ 64 <1008000000>;
292 opp-microvolt = <84000 292 opp-microvolt = <840000>;
293 clock-latency-ns = <24 293 clock-latency-ns = <244144>; /* 8 32k periods */
294 }; 294 };
295 295
296 opp-1128000000 { 296 opp-1128000000 {
297 opp-hz = /bits/ 64 <11 297 opp-hz = /bits/ 64 <1128000000>;
298 opp-microvolt = <84000 298 opp-microvolt = <840000>;
299 clock-latency-ns = <24 299 clock-latency-ns = <244144>; /* 8 32k periods */
300 }; 300 };
301 301
302 opp-1200000000 { 302 opp-1200000000 {
303 opp-hz = /bits/ 64 <12 303 opp-hz = /bits/ 64 <1200000000>;
304 opp-microvolt = <84000 304 opp-microvolt = <840000>;
305 clock-latency-ns = <24 305 clock-latency-ns = <244144>; /* 8 32k periods */
306 }; 306 };
307 }; 307 };
308 308
309 soc { 309 soc {
310 compatible = "simple-bus"; 310 compatible = "simple-bus";
311 #address-cells = <1>; 311 #address-cells = <1>;
312 #size-cells = <1>; 312 #size-cells = <1>;
313 ranges; 313 ranges;
314 314
315 display_clocks: clock@1000000 315 display_clocks: clock@1000000 {
316 compatible = "allwinne 316 compatible = "allwinner,sun8i-a83t-de2-clk";
317 reg = <0x01000000 0x10 317 reg = <0x01000000 0x10000>;
318 clocks = <&ccu CLK_BUS 318 clocks = <&ccu CLK_BUS_DE>,
319 <&ccu CLK_PLL 319 <&ccu CLK_PLL_DE>;
320 clock-names = "bus", 320 clock-names = "bus",
321 "mod"; 321 "mod";
322 resets = <&ccu RST_BUS 322 resets = <&ccu RST_BUS_DE>;
323 #clock-cells = <1>; 323 #clock-cells = <1>;
324 #reset-cells = <1>; 324 #reset-cells = <1>;
325 }; 325 };
326 326
327 rotate: rotate@1020000 { 327 rotate: rotate@1020000 {
328 compatible = "allwinne 328 compatible = "allwinner,sun8i-a83t-de2-rotate";
329 reg = <0x1020000 0x100 329 reg = <0x1020000 0x10000>;
330 interrupts = <GIC_SPI 330 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&display_clo 331 clocks = <&display_clocks CLK_BUS_ROT>,
332 <&display_clo 332 <&display_clocks CLK_ROT>;
333 clock-names = "bus", 333 clock-names = "bus",
334 "mod"; 334 "mod";
335 resets = <&display_clo 335 resets = <&display_clocks RST_ROT>;
336 }; 336 };
337 337
338 mixer0: mixer@1100000 { 338 mixer0: mixer@1100000 {
339 compatible = "allwinne 339 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
340 reg = <0x01100000 0x10 340 reg = <0x01100000 0x100000>;
341 clocks = <&display_clo 341 clocks = <&display_clocks CLK_BUS_MIXER0>,
342 <&display_clo 342 <&display_clocks CLK_MIXER0>;
343 clock-names = "bus", 343 clock-names = "bus",
344 "mod"; 344 "mod";
345 resets = <&display_clo 345 resets = <&display_clocks RST_MIXER0>;
346 346
347 ports { 347 ports {
348 #address-cells 348 #address-cells = <1>;
349 #size-cells = 349 #size-cells = <0>;
350 350
351 mixer0_out: po 351 mixer0_out: port@1 {
352 #addre 352 #address-cells = <1>;
353 #size- 353 #size-cells = <0>;
354 reg = 354 reg = <1>;
355 355
356 mixer0 356 mixer0_out_tcon0: endpoint@0 {
357 357 reg = <0>;
358 358 remote-endpoint = <&tcon0_in_mixer0>;
359 }; 359 };
360 360
361 mixer0 361 mixer0_out_tcon1: endpoint@1 {
362 362 reg = <1>;
363 363 remote-endpoint = <&tcon1_in_mixer0>;
364 }; 364 };
365 }; 365 };
366 }; 366 };
367 }; 367 };
368 368
369 mixer1: mixer@1200000 { 369 mixer1: mixer@1200000 {
370 compatible = "allwinne 370 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
371 reg = <0x01200000 0x10 371 reg = <0x01200000 0x100000>;
372 clocks = <&display_clo 372 clocks = <&display_clocks CLK_BUS_MIXER1>,
373 <&display_clo 373 <&display_clocks CLK_MIXER1>;
374 clock-names = "bus", 374 clock-names = "bus",
375 "mod"; 375 "mod";
376 resets = <&display_clo 376 resets = <&display_clocks RST_WB>;
377 377
378 ports { 378 ports {
379 #address-cells 379 #address-cells = <1>;
380 #size-cells = 380 #size-cells = <0>;
381 381
382 mixer1_out: po 382 mixer1_out: port@1 {
383 #addre 383 #address-cells = <1>;
384 #size- 384 #size-cells = <0>;
385 reg = 385 reg = <1>;
386 386
387 mixer1 387 mixer1_out_tcon0: endpoint@0 {
388 388 reg = <0>;
389 389 remote-endpoint = <&tcon0_in_mixer1>;
390 }; 390 };
391 391
392 mixer1 392 mixer1_out_tcon1: endpoint@1 {
393 393 reg = <1>;
394 394 remote-endpoint = <&tcon1_in_mixer1>;
395 }; 395 };
396 }; 396 };
397 }; 397 };
398 }; 398 };
399 399
400 cpucfg@1700000 { 400 cpucfg@1700000 {
401 compatible = "allwinne 401 compatible = "allwinner,sun8i-a83t-cpucfg";
402 reg = <0x01700000 0x40 402 reg = <0x01700000 0x400>;
403 }; 403 };
404 404
405 cci@1790000 { 405 cci@1790000 {
406 compatible = "arm,cci- 406 compatible = "arm,cci-400";
407 #address-cells = <1>; 407 #address-cells = <1>;
408 #size-cells = <1>; 408 #size-cells = <1>;
409 reg = <0x01790000 0x10 409 reg = <0x01790000 0x10000>;
410 ranges = <0x0 0x017900 410 ranges = <0x0 0x01790000 0x10000>;
411 411
412 cci_control0: slave-if 412 cci_control0: slave-if@4000 {
413 compatible = " 413 compatible = "arm,cci-400-ctrl-if";
414 interface-type 414 interface-type = "ace";
415 reg = <0x4000 415 reg = <0x4000 0x1000>;
416 }; 416 };
417 417
418 cci_control1: slave-if 418 cci_control1: slave-if@5000 {
419 compatible = " 419 compatible = "arm,cci-400-ctrl-if";
420 interface-type 420 interface-type = "ace";
421 reg = <0x5000 421 reg = <0x5000 0x1000>;
422 }; 422 };
423 423
424 pmu@9000 { 424 pmu@9000 {
425 compatible = " 425 compatible = "arm,cci-400-pmu,r1";
426 reg = <0x9000 426 reg = <0x9000 0x5000>;
427 interrupts = < 427 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
428 < 428 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
429 < 429 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
430 < 430 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
431 < 431 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
432 < 432 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
433 < 433 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
434 < 434 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
435 }; 435 };
436 }; 436 };
437 437
438 syscon: syscon@1c00000 { 438 syscon: syscon@1c00000 {
439 compatible = "allwinne 439 compatible = "allwinner,sun8i-a83t-system-controller",
440 "syscon"; 440 "syscon";
441 reg = <0x01c00000 0x10 441 reg = <0x01c00000 0x1000>;
442 }; 442 };
443 443
444 dma: dma-controller@1c02000 { 444 dma: dma-controller@1c02000 {
445 compatible = "allwinne 445 compatible = "allwinner,sun8i-a83t-dma";
446 reg = <0x01c02000 0x10 446 reg = <0x01c02000 0x1000>;
447 interrupts = <GIC_SPI 447 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&ccu CLK_BUS 448 clocks = <&ccu CLK_BUS_DMA>;
449 resets = <&ccu RST_BUS 449 resets = <&ccu RST_BUS_DMA>;
450 #dma-cells = <1>; 450 #dma-cells = <1>;
451 }; 451 };
452 452
453 tcon0: lcd-controller@1c0c000 453 tcon0: lcd-controller@1c0c000 {
454 compatible = "allwinne 454 compatible = "allwinner,sun8i-a83t-tcon-lcd";
455 reg = <0x01c0c000 0x10 455 reg = <0x01c0c000 0x1000>;
456 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&ccu CLK_BUS 457 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
458 clock-names = "ahb", " 458 clock-names = "ahb", "tcon-ch0";
459 clock-output-names = " 459 clock-output-names = "tcon-data-clock";
460 #clock-cells = <0>; 460 #clock-cells = <0>;
461 resets = <&ccu RST_BUS 461 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
462 reset-names = "lcd", " 462 reset-names = "lcd", "lvds";
463 463
464 ports { 464 ports {
465 #address-cells 465 #address-cells = <1>;
466 #size-cells = 466 #size-cells = <0>;
467 467
468 tcon0_in: port 468 tcon0_in: port@0 {
469 #addre 469 #address-cells = <1>;
470 #size- 470 #size-cells = <0>;
471 reg = 471 reg = <0>;
472 472
473 tcon0_ 473 tcon0_in_mixer0: endpoint@0 {
474 474 reg = <0>;
475 475 remote-endpoint = <&mixer0_out_tcon0>;
476 }; 476 };
477 477
478 tcon0_ 478 tcon0_in_mixer1: endpoint@1 {
479 479 reg = <1>;
480 480 remote-endpoint = <&mixer1_out_tcon0>;
481 }; 481 };
482 }; 482 };
483 483
484 tcon0_out: por 484 tcon0_out: port@1 {
485 reg = 485 reg = <1>;
486 }; 486 };
487 }; 487 };
488 }; 488 };
489 489
490 tcon1: lcd-controller@1c0d000 490 tcon1: lcd-controller@1c0d000 {
491 compatible = "allwinne 491 compatible = "allwinner,sun8i-a83t-tcon-tv";
492 reg = <0x01c0d000 0x10 492 reg = <0x01c0d000 0x1000>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&ccu CLK_BUS 494 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
495 clock-names = "ahb", " 495 clock-names = "ahb", "tcon-ch1";
496 resets = <&ccu RST_BUS 496 resets = <&ccu RST_BUS_TCON1>;
497 reset-names = "lcd"; 497 reset-names = "lcd";
498 498
499 ports { 499 ports {
500 #address-cells 500 #address-cells = <1>;
501 #size-cells = 501 #size-cells = <0>;
502 502
503 tcon1_in: port 503 tcon1_in: port@0 {
504 #addre 504 #address-cells = <1>;
505 #size- 505 #size-cells = <0>;
506 reg = 506 reg = <0>;
507 507
508 tcon1_ 508 tcon1_in_mixer0: endpoint@0 {
509 509 reg = <0>;
510 510 remote-endpoint = <&mixer0_out_tcon1>;
511 }; 511 };
512 512
513 tcon1_ 513 tcon1_in_mixer1: endpoint@1 {
514 514 reg = <1>;
515 515 remote-endpoint = <&mixer1_out_tcon1>;
516 }; 516 };
517 }; 517 };
518 518
519 tcon1_out: por 519 tcon1_out: port@1 {
520 #addre 520 #address-cells = <1>;
521 #size- 521 #size-cells = <0>;
522 reg = 522 reg = <1>;
523 523
524 tcon1_ 524 tcon1_out_hdmi: endpoint@1 {
525 525 reg = <1>;
526 526 remote-endpoint = <&hdmi_in_tcon1>;
527 }; 527 };
528 }; 528 };
529 }; 529 };
530 }; 530 };
531 531
532 mmc0: mmc@1c0f000 { 532 mmc0: mmc@1c0f000 {
533 compatible = "allwinne 533 compatible = "allwinner,sun8i-a83t-mmc",
534 "allwinne 534 "allwinner,sun7i-a20-mmc";
535 reg = <0x01c0f000 0x10 535 reg = <0x01c0f000 0x1000>;
536 clocks = <&ccu CLK_BUS 536 clocks = <&ccu CLK_BUS_MMC0>,
537 <&ccu CLK_MMC 537 <&ccu CLK_MMC0>,
538 <&ccu CLK_MMC 538 <&ccu CLK_MMC0_OUTPUT>,
539 <&ccu CLK_MMC 539 <&ccu CLK_MMC0_SAMPLE>;
540 clock-names = "ahb", 540 clock-names = "ahb",
541 "mmc", 541 "mmc",
542 "output" 542 "output",
543 "sample" 543 "sample";
544 resets = <&ccu RST_BUS 544 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 545 reset-names = "ahb";
546 interrupts = <GIC_SPI 546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 status = "disabled"; 547 status = "disabled";
548 #address-cells = <1>; 548 #address-cells = <1>;
549 #size-cells = <0>; 549 #size-cells = <0>;
550 }; 550 };
551 551
552 mmc1: mmc@1c10000 { 552 mmc1: mmc@1c10000 {
553 compatible = "allwinne 553 compatible = "allwinner,sun8i-a83t-mmc",
554 "allwinne 554 "allwinner,sun7i-a20-mmc";
555 reg = <0x01c10000 0x10 555 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 556 clocks = <&ccu CLK_BUS_MMC1>,
557 <&ccu CLK_MMC 557 <&ccu CLK_MMC1>,
558 <&ccu CLK_MMC 558 <&ccu CLK_MMC1_OUTPUT>,
559 <&ccu CLK_MMC 559 <&ccu CLK_MMC1_SAMPLE>;
560 clock-names = "ahb", 560 clock-names = "ahb",
561 "mmc", 561 "mmc",
562 "output" 562 "output",
563 "sample" 563 "sample";
564 resets = <&ccu RST_BUS 564 resets = <&ccu RST_BUS_MMC1>;
565 reset-names = "ahb"; 565 reset-names = "ahb";
566 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
567 pinctrl-names = "defau 567 pinctrl-names = "default";
568 pinctrl-0 = <&mmc1_pin 568 pinctrl-0 = <&mmc1_pins>;
569 status = "disabled"; 569 status = "disabled";
570 #address-cells = <1>; 570 #address-cells = <1>;
571 #size-cells = <0>; 571 #size-cells = <0>;
572 }; 572 };
573 573
574 mmc2: mmc@1c11000 { 574 mmc2: mmc@1c11000 {
575 compatible = "allwinne 575 compatible = "allwinner,sun8i-a83t-emmc";
576 reg = <0x01c11000 0x10 576 reg = <0x01c11000 0x1000>;
577 clocks = <&ccu CLK_BUS 577 clocks = <&ccu CLK_BUS_MMC2>,
578 <&ccu CLK_MMC 578 <&ccu CLK_MMC2>,
579 <&ccu CLK_MMC 579 <&ccu CLK_MMC2_OUTPUT>,
580 <&ccu CLK_MMC 580 <&ccu CLK_MMC2_SAMPLE>;
581 clock-names = "ahb", 581 clock-names = "ahb",
582 "mmc", 582 "mmc",
583 "output" 583 "output",
584 "sample" 584 "sample";
585 resets = <&ccu RST_BUS 585 resets = <&ccu RST_BUS_MMC2>;
586 reset-names = "ahb"; 586 reset-names = "ahb";
587 interrupts = <GIC_SPI 587 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
588 status = "disabled"; 588 status = "disabled";
589 #address-cells = <1>; 589 #address-cells = <1>;
590 #size-cells = <0>; 590 #size-cells = <0>;
591 }; 591 };
592 592
593 sid: eeprom@1c14000 { 593 sid: eeprom@1c14000 {
594 compatible = "allwinne 594 compatible = "allwinner,sun8i-a83t-sid";
595 reg = <0x1c14000 0x400 595 reg = <0x1c14000 0x400>;
596 #address-cells = <1>; 596 #address-cells = <1>;
597 #size-cells = <1>; 597 #size-cells = <1>;
598 598
599 ths_calibration: therm 599 ths_calibration: thermal-sensor-calibration@34 {
600 reg = <0x34 8> 600 reg = <0x34 8>;
601 }; 601 };
602 }; 602 };
603 603
604 crypto: crypto@1c15000 { 604 crypto: crypto@1c15000 {
605 compatible = "allwinne 605 compatible = "allwinner,sun8i-a83t-crypto";
606 reg = <0x01c15000 0x10 606 reg = <0x01c15000 0x1000>;
607 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
608 resets = <&ccu RST_BUS 608 resets = <&ccu RST_BUS_SS>;
609 clocks = <&ccu CLK_BUS 609 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
610 clock-names = "bus", " 610 clock-names = "bus", "mod";
611 }; 611 };
612 612
613 msgbox: mailbox@1c17000 { 613 msgbox: mailbox@1c17000 {
614 compatible = "allwinne 614 compatible = "allwinner,sun8i-a83t-msgbox",
615 "allwinne 615 "allwinner,sun6i-a31-msgbox";
616 reg = <0x01c17000 0x10 616 reg = <0x01c17000 0x1000>;
617 clocks = <&ccu CLK_BUS 617 clocks = <&ccu CLK_BUS_MSGBOX>;
618 resets = <&ccu RST_BUS 618 resets = <&ccu RST_BUS_MSGBOX>;
619 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
620 #mbox-cells = <1>; 620 #mbox-cells = <1>;
621 }; 621 };
622 622
623 usb_otg: usb@1c19000 { 623 usb_otg: usb@1c19000 {
624 compatible = "allwinne 624 compatible = "allwinner,sun8i-a83t-musb",
625 "allwinne 625 "allwinner,sun8i-a33-musb";
626 reg = <0x01c19000 0x04 626 reg = <0x01c19000 0x0400>;
627 clocks = <&ccu CLK_BUS 627 clocks = <&ccu CLK_BUS_OTG>;
628 resets = <&ccu RST_BUS 628 resets = <&ccu RST_BUS_OTG>;
629 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
630 interrupt-names = "mc" 630 interrupt-names = "mc";
631 phys = <&usbphy 0>; 631 phys = <&usbphy 0>;
632 phy-names = "usb"; 632 phy-names = "usb";
633 extcon = <&usbphy 0>; 633 extcon = <&usbphy 0>;
634 dr_mode = "otg"; 634 dr_mode = "otg";
635 status = "disabled"; 635 status = "disabled";
636 }; 636 };
637 637
638 usbphy: phy@1c19400 { 638 usbphy: phy@1c19400 {
639 compatible = "allwinne 639 compatible = "allwinner,sun8i-a83t-usb-phy";
640 reg = <0x01c19400 0x10 640 reg = <0x01c19400 0x10>,
641 <0x01c1a800 0x14 641 <0x01c1a800 0x14>,
642 <0x01c1b800 0x14 642 <0x01c1b800 0x14>;
643 reg-names = "phy_ctrl" 643 reg-names = "phy_ctrl",
644 "pmu1", 644 "pmu1",
645 "pmu2"; 645 "pmu2";
646 clocks = <&ccu CLK_USB 646 clocks = <&ccu CLK_USB_PHY0>,
647 <&ccu CLK_USB 647 <&ccu CLK_USB_PHY1>,
648 <&ccu CLK_USB 648 <&ccu CLK_USB_HSIC>,
649 <&ccu CLK_USB 649 <&ccu CLK_USB_HSIC_12M>;
650 clock-names = "usb0_ph 650 clock-names = "usb0_phy",
651 "usb1_ph 651 "usb1_phy",
652 "usb2_ph 652 "usb2_phy",
653 "usb2_hs 653 "usb2_hsic_12M";
654 resets = <&ccu RST_USB 654 resets = <&ccu RST_USB_PHY0>,
655 <&ccu RST_USB 655 <&ccu RST_USB_PHY1>,
656 <&ccu RST_USB 656 <&ccu RST_USB_HSIC>;
657 reset-names = "usb0_re 657 reset-names = "usb0_reset",
658 "usb1_re 658 "usb1_reset",
659 "usb2_re 659 "usb2_reset";
660 status = "disabled"; 660 status = "disabled";
661 #phy-cells = <1>; 661 #phy-cells = <1>;
662 }; 662 };
663 663
664 ehci0: usb@1c1a000 { 664 ehci0: usb@1c1a000 {
665 compatible = "allwinne 665 compatible = "allwinner,sun8i-a83t-ehci",
666 "generic- 666 "generic-ehci";
667 reg = <0x01c1a000 0x10 667 reg = <0x01c1a000 0x100>;
668 interrupts = <GIC_SPI 668 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&ccu CLK_BUS 669 clocks = <&ccu CLK_BUS_EHCI0>;
670 resets = <&ccu RST_BUS 670 resets = <&ccu RST_BUS_EHCI0>;
671 phys = <&usbphy 1>; 671 phys = <&usbphy 1>;
672 phy-names = "usb"; 672 phy-names = "usb";
673 status = "disabled"; 673 status = "disabled";
674 }; 674 };
675 675
676 ohci0: usb@1c1a400 { 676 ohci0: usb@1c1a400 {
677 compatible = "allwinne 677 compatible = "allwinner,sun8i-a83t-ohci",
678 "generic- 678 "generic-ohci";
679 reg = <0x01c1a400 0x10 679 reg = <0x01c1a400 0x100>;
680 interrupts = <GIC_SPI 680 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&ccu CLK_BUS 681 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
682 resets = <&ccu RST_BUS 682 resets = <&ccu RST_BUS_OHCI0>;
683 phys = <&usbphy 1>; 683 phys = <&usbphy 1>;
684 phy-names = "usb"; 684 phy-names = "usb";
685 status = "disabled"; 685 status = "disabled";
686 }; 686 };
687 687
688 ehci1: usb@1c1b000 { 688 ehci1: usb@1c1b000 {
689 compatible = "allwinne 689 compatible = "allwinner,sun8i-a83t-ehci",
690 "generic- 690 "generic-ehci";
691 reg = <0x01c1b000 0x10 691 reg = <0x01c1b000 0x100>;
692 interrupts = <GIC_SPI 692 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&ccu CLK_BUS 693 clocks = <&ccu CLK_BUS_EHCI1>;
694 resets = <&ccu RST_BUS 694 resets = <&ccu RST_BUS_EHCI1>;
695 phys = <&usbphy 2>; 695 phys = <&usbphy 2>;
696 phy-names = "usb"; 696 phy-names = "usb";
697 status = "disabled"; 697 status = "disabled";
698 }; 698 };
699 699
700 ccu: clock@1c20000 { 700 ccu: clock@1c20000 {
701 compatible = "allwinne 701 compatible = "allwinner,sun8i-a83t-ccu";
702 reg = <0x01c20000 0x40 702 reg = <0x01c20000 0x400>;
703 clocks = <&osc24M>, <& 703 clocks = <&osc24M>, <&osc16Md512>;
704 clock-names = "hosc", 704 clock-names = "hosc", "losc";
705 #clock-cells = <1>; 705 #clock-cells = <1>;
706 #reset-cells = <1>; 706 #reset-cells = <1>;
707 }; 707 };
708 708
709 pio: pinctrl@1c20800 { 709 pio: pinctrl@1c20800 {
710 compatible = "allwinne 710 compatible = "allwinner,sun8i-a83t-pinctrl";
711 interrupt-parent = <&r 711 interrupt-parent = <&r_intc>;
712 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 713 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 714 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
715 reg = <0x01c20800 0x40 715 reg = <0x01c20800 0x400>;
716 clocks = <&ccu CLK_BUS 716 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
717 clock-names = "apb", " 717 clock-names = "apb", "hosc", "losc";
718 gpio-controller; 718 gpio-controller;
719 interrupt-controller; 719 interrupt-controller;
720 #interrupt-cells = <3> 720 #interrupt-cells = <3>;
721 #gpio-cells = <3>; 721 #gpio-cells = <3>;
722 722
723 /omit-if-no-ref/ 723 /omit-if-no-ref/
724 csi_8bit_parallel_pins 724 csi_8bit_parallel_pins: csi-8bit-parallel-pins {
725 pins = "PE0", 725 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
726 "PE8", 726 "PE8", "PE9", "PE10", "PE11",
727 "PE12", 727 "PE12", "PE13";
728 function = "cs 728 function = "csi";
729 }; 729 };
730 730
731 /omit-if-no-ref/ 731 /omit-if-no-ref/
732 csi_mclk_pin: csi-mclk 732 csi_mclk_pin: csi-mclk-pin {
733 pins = "PE1"; 733 pins = "PE1";
734 function = "cs 734 function = "csi";
735 }; 735 };
736 736
737 emac_rgmii_pins: emac- 737 emac_rgmii_pins: emac-rgmii-pins {
738 pins = "PD2", 738 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
739 "PD11", 739 "PD11", "PD12", "PD13", "PD14", "PD18",
740 "PD19", 740 "PD19", "PD21", "PD22", "PD23";
741 function = "gm 741 function = "gmac";
742 /* 742 /*
743 * data lines 743 * data lines in RGMII mode use DDR mode
744 * and need a 744 * and need a higher signal drive strength
745 */ 745 */
746 drive-strength 746 drive-strength = <40>;
747 }; 747 };
748 748
749 hdmi_pins: hdmi-pins { 749 hdmi_pins: hdmi-pins {
750 pins = "PH6", 750 pins = "PH6", "PH7", "PH8";
751 function = "hd 751 function = "hdmi";
752 }; 752 };
753 753
754 i2c0_pins: i2c0-pins { 754 i2c0_pins: i2c0-pins {
755 pins = "PH0", 755 pins = "PH0", "PH1";
756 function = "i2 756 function = "i2c0";
757 }; 757 };
758 758
759 i2c1_pins: i2c1-pins { 759 i2c1_pins: i2c1-pins {
760 pins = "PH2", 760 pins = "PH2", "PH3";
761 function = "i2 761 function = "i2c1";
762 }; 762 };
763 763
764 /omit-if-no-ref/ 764 /omit-if-no-ref/
765 i2c2_pe_pins: i2c2-pe- 765 i2c2_pe_pins: i2c2-pe-pins {
766 pins = "PE14", 766 pins = "PE14", "PE15";
767 function = "i2 767 function = "i2c2";
768 }; 768 };
769 769
770 i2c2_ph_pins: i2c2-ph- 770 i2c2_ph_pins: i2c2-ph-pins {
771 pins = "PH4", 771 pins = "PH4", "PH5";
772 function = "i2 772 function = "i2c2";
773 }; 773 };
774 774
775 i2s1_pins: i2s1-pins { 775 i2s1_pins: i2s1-pins {
776 /* I2S1 does n 776 /* I2S1 does not have external MCLK pin */
777 pins = "PG10", 777 pins = "PG10", "PG11", "PG12", "PG13";
778 function = "i2 778 function = "i2s1";
779 }; 779 };
780 780
781 lcd_lvds_pins: lcd-lvd 781 lcd_lvds_pins: lcd-lvds-pins {
782 pins = "PD18", 782 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
783 "PD23", 783 "PD23", "PD24", "PD25", "PD26", "PD27";
784 function = "lv 784 function = "lvds0";
785 }; 785 };
786 786
787 mmc0_pins: mmc0-pins { 787 mmc0_pins: mmc0-pins {
788 pins = "PF0", 788 pins = "PF0", "PF1", "PF2",
789 "PF3", 789 "PF3", "PF4", "PF5";
790 function = "mm 790 function = "mmc0";
791 drive-strength 791 drive-strength = <30>;
792 bias-pull-up; 792 bias-pull-up;
793 }; 793 };
794 794
795 mmc1_pins: mmc1-pins { 795 mmc1_pins: mmc1-pins {
796 pins = "PG0", 796 pins = "PG0", "PG1", "PG2",
797 "PG3", 797 "PG3", "PG4", "PG5";
798 function = "mm 798 function = "mmc1";
799 drive-strength 799 drive-strength = <30>;
800 bias-pull-up; 800 bias-pull-up;
801 }; 801 };
802 802
803 mmc2_8bit_emmc_pins: m 803 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
804 pins = "PC5", 804 pins = "PC5", "PC6", "PC8", "PC9",
805 "PC10", 805 "PC10", "PC11", "PC12", "PC13",
806 "PC14", 806 "PC14", "PC15", "PC16";
807 function = "mm 807 function = "mmc2";
808 drive-strength 808 drive-strength = <30>;
809 bias-pull-up; 809 bias-pull-up;
810 }; 810 };
811 811
812 pwm_pin: pwm-pin { 812 pwm_pin: pwm-pin {
813 pins = "PD28"; 813 pins = "PD28";
814 function = "pw 814 function = "pwm";
815 }; 815 };
816 816
817 spdif_tx_pin: spdif-tx 817 spdif_tx_pin: spdif-tx-pin {
818 pins = "PE18"; 818 pins = "PE18";
819 function = "sp 819 function = "spdif";
820 }; 820 };
821 821
822 uart0_pb_pins: uart0-p 822 uart0_pb_pins: uart0-pb-pins {
823 pins = "PB9", 823 pins = "PB9", "PB10";
824 function = "ua 824 function = "uart0";
825 }; 825 };
826 826
827 uart0_pf_pins: uart0-p 827 uart0_pf_pins: uart0-pf-pins {
828 pins = "PF2", 828 pins = "PF2", "PF4";
829 function = "ua 829 function = "uart0";
830 }; 830 };
831 831
832 uart1_pins: uart1-pins 832 uart1_pins: uart1-pins {
833 pins = "PG6", 833 pins = "PG6", "PG7";
834 function = "ua 834 function = "uart1";
835 }; 835 };
836 836
837 uart1_rts_cts_pins: ua 837 uart1_rts_cts_pins: uart1-rts-cts-pins {
838 pins = "PG8", 838 pins = "PG8", "PG9";
839 function = "ua 839 function = "uart1";
840 }; 840 };
841 841
842 /omit-if-no-ref/ 842 /omit-if-no-ref/
843 uart2_pb_pins: uart2-p 843 uart2_pb_pins: uart2-pb-pins {
844 pins = "PB0", 844 pins = "PB0", "PB1";
845 function = "ua 845 function = "uart2";
846 }; 846 };
847 }; 847 };
848 848
849 timer@1c20c00 { 849 timer@1c20c00 {
850 compatible = "allwinne 850 compatible = "allwinner,sun8i-a23-timer";
851 reg = <0x01c20c00 0xa0 851 reg = <0x01c20c00 0xa0>;
852 interrupts = <GIC_SPI 852 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 853 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&osc24M>; 854 clocks = <&osc24M>;
855 }; 855 };
856 856
857 watchdog@1c20ca0 { 857 watchdog@1c20ca0 {
858 compatible = "allwinne 858 compatible = "allwinner,sun6i-a31-wdt";
859 reg = <0x01c20ca0 0x20 859 reg = <0x01c20ca0 0x20>;
860 interrupts = <GIC_SPI 860 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&osc24M>; 861 clocks = <&osc24M>;
862 }; 862 };
863 863
864 spdif: spdif@1c21000 { 864 spdif: spdif@1c21000 {
865 #sound-dai-cells = <0> 865 #sound-dai-cells = <0>;
866 compatible = "allwinne 866 compatible = "allwinner,sun8i-a83t-spdif",
867 "allwinne 867 "allwinner,sun8i-h3-spdif";
868 reg = <0x01c21000 0x40 868 reg = <0x01c21000 0x400>;
869 interrupts = <GIC_SPI 869 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&ccu CLK_BUS 870 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
871 resets = <&ccu RST_BUS 871 resets = <&ccu RST_BUS_SPDIF>;
872 clock-names = "apb", " 872 clock-names = "apb", "spdif";
873 dmas = <&dma 2>; 873 dmas = <&dma 2>;
874 dma-names = "tx"; 874 dma-names = "tx";
875 pinctrl-names = "defau 875 pinctrl-names = "default";
876 pinctrl-0 = <&spdif_tx 876 pinctrl-0 = <&spdif_tx_pin>;
877 status = "disabled"; 877 status = "disabled";
878 }; 878 };
879 879
880 i2s0: i2s@1c22000 { 880 i2s0: i2s@1c22000 {
881 #sound-dai-cells = <0> 881 #sound-dai-cells = <0>;
882 compatible = "allwinne 882 compatible = "allwinner,sun8i-a83t-i2s";
883 reg = <0x01c22000 0x40 883 reg = <0x01c22000 0x400>;
884 interrupts = <GIC_SPI 884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&ccu CLK_BUS 885 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
886 clock-names = "apb", " 886 clock-names = "apb", "mod";
887 dmas = <&dma 3>, <&dma 887 dmas = <&dma 3>, <&dma 3>;
888 resets = <&ccu RST_BUS 888 resets = <&ccu RST_BUS_I2S0>;
889 dma-names = "rx", "tx" 889 dma-names = "rx", "tx";
890 status = "disabled"; 890 status = "disabled";
891 }; 891 };
892 892
893 i2s1: i2s@1c22400 { 893 i2s1: i2s@1c22400 {
894 #sound-dai-cells = <0> 894 #sound-dai-cells = <0>;
895 compatible = "allwinne 895 compatible = "allwinner,sun8i-a83t-i2s";
896 reg = <0x01c22400 0x40 896 reg = <0x01c22400 0x400>;
897 interrupts = <GIC_SPI 897 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&ccu CLK_BUS 898 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
899 clock-names = "apb", " 899 clock-names = "apb", "mod";
900 dmas = <&dma 4>, <&dma 900 dmas = <&dma 4>, <&dma 4>;
901 resets = <&ccu RST_BUS 901 resets = <&ccu RST_BUS_I2S1>;
902 dma-names = "rx", "tx" 902 dma-names = "rx", "tx";
903 pinctrl-names = "defau 903 pinctrl-names = "default";
904 pinctrl-0 = <&i2s1_pin 904 pinctrl-0 = <&i2s1_pins>;
905 status = "disabled"; 905 status = "disabled";
906 }; 906 };
907 907
908 i2s2: i2s@1c22800 { 908 i2s2: i2s@1c22800 {
909 #sound-dai-cells = <0> 909 #sound-dai-cells = <0>;
910 compatible = "allwinne 910 compatible = "allwinner,sun8i-a83t-i2s";
911 reg = <0x01c22800 0x40 911 reg = <0x01c22800 0x400>;
912 interrupts = <GIC_SPI 912 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&ccu CLK_BUS 913 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
914 clock-names = "apb", " 914 clock-names = "apb", "mod";
915 dmas = <&dma 27>; 915 dmas = <&dma 27>;
916 resets = <&ccu RST_BUS 916 resets = <&ccu RST_BUS_I2S2>;
917 dma-names = "tx"; 917 dma-names = "tx";
918 status = "disabled"; 918 status = "disabled";
919 }; 919 };
920 920
921 pwm: pwm@1c21400 { 921 pwm: pwm@1c21400 {
922 compatible = "allwinne 922 compatible = "allwinner,sun8i-a83t-pwm",
923 "allwinne 923 "allwinner,sun8i-h3-pwm";
924 reg = <0x01c21400 0x40 924 reg = <0x01c21400 0x400>;
925 clocks = <&osc24M>; 925 clocks = <&osc24M>;
926 #pwm-cells = <3>; 926 #pwm-cells = <3>;
927 status = "disabled"; 927 status = "disabled";
928 }; 928 };
929 929
930 uart0: serial@1c28000 { 930 uart0: serial@1c28000 {
931 compatible = "snps,dw- 931 compatible = "snps,dw-apb-uart";
932 reg = <0x01c28000 0x40 932 reg = <0x01c28000 0x400>;
933 interrupts = <GIC_SPI 933 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
934 reg-shift = <2>; 934 reg-shift = <2>;
935 reg-io-width = <4>; 935 reg-io-width = <4>;
936 clocks = <&ccu CLK_BUS 936 clocks = <&ccu CLK_BUS_UART0>;
937 resets = <&ccu RST_BUS 937 resets = <&ccu RST_BUS_UART0>;
938 status = "disabled"; 938 status = "disabled";
939 }; 939 };
940 940
941 uart1: serial@1c28400 { 941 uart1: serial@1c28400 {
942 compatible = "snps,dw- 942 compatible = "snps,dw-apb-uart";
943 reg = <0x01c28400 0x40 943 reg = <0x01c28400 0x400>;
944 interrupts = <GIC_SPI 944 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
945 reg-shift = <2>; 945 reg-shift = <2>;
946 reg-io-width = <4>; 946 reg-io-width = <4>;
947 clocks = <&ccu CLK_BUS 947 clocks = <&ccu CLK_BUS_UART1>;
948 resets = <&ccu RST_BUS 948 resets = <&ccu RST_BUS_UART1>;
949 status = "disabled"; 949 status = "disabled";
950 }; 950 };
951 951
952 uart2: serial@1c28800 { 952 uart2: serial@1c28800 {
953 compatible = "snps,dw- 953 compatible = "snps,dw-apb-uart";
954 reg = <0x01c28800 0x40 954 reg = <0x01c28800 0x400>;
955 interrupts = <GIC_SPI 955 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
956 reg-shift = <2>; 956 reg-shift = <2>;
957 reg-io-width = <4>; 957 reg-io-width = <4>;
958 clocks = <&ccu CLK_BUS 958 clocks = <&ccu CLK_BUS_UART2>;
959 resets = <&ccu RST_BUS 959 resets = <&ccu RST_BUS_UART2>;
960 status = "disabled"; 960 status = "disabled";
961 }; 961 };
962 962
963 uart3: serial@1c28c00 { 963 uart3: serial@1c28c00 {
964 compatible = "snps,dw- 964 compatible = "snps,dw-apb-uart";
965 reg = <0x01c28c00 0x40 965 reg = <0x01c28c00 0x400>;
966 interrupts = <GIC_SPI 966 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
967 reg-shift = <2>; 967 reg-shift = <2>;
968 reg-io-width = <4>; 968 reg-io-width = <4>;
969 clocks = <&ccu CLK_BUS 969 clocks = <&ccu CLK_BUS_UART3>;
970 resets = <&ccu RST_BUS 970 resets = <&ccu RST_BUS_UART3>;
971 status = "disabled"; 971 status = "disabled";
972 }; 972 };
973 973
974 uart4: serial@1c29000 { 974 uart4: serial@1c29000 {
975 compatible = "snps,dw- 975 compatible = "snps,dw-apb-uart";
976 reg = <0x01c29000 0x40 976 reg = <0x01c29000 0x400>;
977 interrupts = <GIC_SPI 977 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
978 reg-shift = <2>; 978 reg-shift = <2>;
979 reg-io-width = <4>; 979 reg-io-width = <4>;
980 clocks = <&ccu CLK_BUS 980 clocks = <&ccu CLK_BUS_UART4>;
981 resets = <&ccu RST_BUS 981 resets = <&ccu RST_BUS_UART4>;
982 status = "disabled"; 982 status = "disabled";
983 }; 983 };
984 984
985 i2c0: i2c@1c2ac00 { 985 i2c0: i2c@1c2ac00 {
986 compatible = "allwinne 986 compatible = "allwinner,sun8i-a83t-i2c",
987 "allwinne 987 "allwinner,sun6i-a31-i2c";
988 reg = <0x01c2ac00 0x40 988 reg = <0x01c2ac00 0x400>;
989 interrupts = <GIC_SPI 989 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&ccu CLK_BUS 990 clocks = <&ccu CLK_BUS_I2C0>;
991 resets = <&ccu RST_BUS 991 resets = <&ccu RST_BUS_I2C0>;
992 pinctrl-names = "defau 992 pinctrl-names = "default";
993 pinctrl-0 = <&i2c0_pin 993 pinctrl-0 = <&i2c0_pins>;
994 status = "disabled"; 994 status = "disabled";
995 #address-cells = <1>; 995 #address-cells = <1>;
996 #size-cells = <0>; 996 #size-cells = <0>;
997 }; 997 };
998 998
999 i2c1: i2c@1c2b000 { 999 i2c1: i2c@1c2b000 {
1000 compatible = "allwinn 1000 compatible = "allwinner,sun8i-a83t-i2c",
1001 "allwinn 1001 "allwinner,sun6i-a31-i2c";
1002 reg = <0x01c2b000 0x4 1002 reg = <0x01c2b000 0x400>;
1003 interrupts = <GIC_SPI 1003 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&ccu CLK_BU 1004 clocks = <&ccu CLK_BUS_I2C1>;
1005 resets = <&ccu RST_BU 1005 resets = <&ccu RST_BUS_I2C1>;
1006 pinctrl-names = "defa 1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c1_pi 1007 pinctrl-0 = <&i2c1_pins>;
1008 status = "disabled"; 1008 status = "disabled";
1009 #address-cells = <1>; 1009 #address-cells = <1>;
1010 #size-cells = <0>; 1010 #size-cells = <0>;
1011 }; 1011 };
1012 1012
1013 i2c2: i2c@1c2b400 { 1013 i2c2: i2c@1c2b400 {
1014 compatible = "allwinn 1014 compatible = "allwinner,sun8i-a83t-i2c",
1015 "allwinn 1015 "allwinner,sun6i-a31-i2c";
1016 reg = <0x01c2b400 0x4 1016 reg = <0x01c2b400 0x400>;
1017 interrupts = <GIC_SPI 1017 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&ccu CLK_BU 1018 clocks = <&ccu CLK_BUS_I2C2>;
1019 resets = <&ccu RST_BU 1019 resets = <&ccu RST_BUS_I2C2>;
1020 status = "disabled"; 1020 status = "disabled";
1021 #address-cells = <1>; 1021 #address-cells = <1>;
1022 #size-cells = <0>; 1022 #size-cells = <0>;
1023 }; 1023 };
1024 1024
1025 emac: ethernet@1c30000 { 1025 emac: ethernet@1c30000 {
1026 compatible = "allwinn 1026 compatible = "allwinner,sun8i-a83t-emac";
1027 syscon = <&syscon>; 1027 syscon = <&syscon>;
1028 reg = <0x01c30000 0x1 1028 reg = <0x01c30000 0x104>;
1029 interrupts = <GIC_SPI 1029 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1030 interrupt-names = "ma 1030 interrupt-names = "macirq";
1031 clocks = <&ccu CLK_BU 1031 clocks = <&ccu CLK_BUS_EMAC>;
1032 clock-names = "stmmac 1032 clock-names = "stmmaceth";
1033 resets = <&ccu RST_BU 1033 resets = <&ccu RST_BUS_EMAC>;
1034 reset-names = "stmmac 1034 reset-names = "stmmaceth";
1035 status = "disabled"; 1035 status = "disabled";
1036 1036
1037 mdio: mdio { 1037 mdio: mdio {
1038 compatible = 1038 compatible = "snps,dwmac-mdio";
1039 #address-cell 1039 #address-cells = <1>;
1040 #size-cells = 1040 #size-cells = <0>;
1041 }; 1041 };
1042 }; 1042 };
1043 1043
1044 gic: interrupt-controller@1c8 1044 gic: interrupt-controller@1c81000 {
1045 compatible = "arm,gic 1045 compatible = "arm,gic-400";
1046 reg = <0x01c81000 0x1 1046 reg = <0x01c81000 0x1000>,
1047 <0x01c82000 0x2 1047 <0x01c82000 0x2000>,
1048 <0x01c84000 0x2 1048 <0x01c84000 0x2000>,
1049 <0x01c86000 0x2 1049 <0x01c86000 0x2000>;
1050 interrupt-controller; 1050 interrupt-controller;
1051 #interrupt-cells = <3 1051 #interrupt-cells = <3>;
1052 interrupts = <GIC_PPI 1052 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1053 }; 1053 };
1054 1054
1055 csi: camera@1cb0000 { 1055 csi: camera@1cb0000 {
1056 compatible = "allwinn 1056 compatible = "allwinner,sun8i-a83t-csi";
1057 reg = <0x01cb0000 0x1 1057 reg = <0x01cb0000 0x1000>;
1058 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&ccu CLK_BU 1059 clocks = <&ccu CLK_BUS_CSI>,
1060 <&ccu CLK_CS 1060 <&ccu CLK_CSI_SCLK>,
1061 <&ccu CLK_DR 1061 <&ccu CLK_DRAM_CSI>;
1062 clock-names = "bus", 1062 clock-names = "bus", "mod", "ram";
1063 resets = <&ccu RST_BU 1063 resets = <&ccu RST_BUS_CSI>;
1064 status = "disabled"; 1064 status = "disabled";
1065 }; 1065 };
1066 1066
1067 hdmi: hdmi@1ee0000 { 1067 hdmi: hdmi@1ee0000 {
1068 compatible = "allwinn 1068 compatible = "allwinner,sun8i-a83t-dw-hdmi";
1069 reg = <0x01ee0000 0x1 1069 reg = <0x01ee0000 0x10000>;
1070 reg-io-width = <1>; 1070 reg-io-width = <1>;
1071 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&ccu CLK_BU 1072 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1073 <&ccu CLK_HD 1073 <&ccu CLK_HDMI>;
1074 clock-names = "iahb", 1074 clock-names = "iahb", "isfr", "tmds";
1075 resets = <&ccu RST_BU 1075 resets = <&ccu RST_BUS_HDMI1>;
1076 reset-names = "ctrl"; 1076 reset-names = "ctrl";
1077 phys = <&hdmi_phy>; 1077 phys = <&hdmi_phy>;
1078 phy-names = "phy"; 1078 phy-names = "phy";
1079 pinctrl-names = "defa 1079 pinctrl-names = "default";
1080 pinctrl-0 = <&hdmi_pi 1080 pinctrl-0 = <&hdmi_pins>;
1081 status = "disabled"; 1081 status = "disabled";
1082 1082
1083 ports { 1083 ports {
1084 #address-cell 1084 #address-cells = <1>;
1085 #size-cells = 1085 #size-cells = <0>;
1086 1086
1087 hdmi_in: port 1087 hdmi_in: port@0 {
1088 reg = 1088 reg = <0>;
1089 1089
1090 hdmi_ 1090 hdmi_in_tcon1: endpoint {
1091 1091 remote-endpoint = <&tcon1_out_hdmi>;
1092 }; 1092 };
1093 }; 1093 };
1094 1094
1095 hdmi_out: por 1095 hdmi_out: port@1 {
1096 reg = 1096 reg = <1>;
1097 }; 1097 };
1098 }; 1098 };
1099 }; 1099 };
1100 1100
1101 hdmi_phy: hdmi-phy@1ef0000 { 1101 hdmi_phy: hdmi-phy@1ef0000 {
1102 compatible = "allwinn 1102 compatible = "allwinner,sun8i-a83t-hdmi-phy";
1103 reg = <0x01ef0000 0x1 1103 reg = <0x01ef0000 0x10000>;
1104 clocks = <&ccu CLK_BU 1104 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1105 clock-names = "bus", 1105 clock-names = "bus", "mod";
1106 resets = <&ccu RST_BU 1106 resets = <&ccu RST_BUS_HDMI0>;
1107 reset-names = "phy"; 1107 reset-names = "phy";
1108 #phy-cells = <0>; 1108 #phy-cells = <0>;
1109 }; 1109 };
1110 1110
1111 r_intc: interrupt-controller@ 1111 r_intc: interrupt-controller@1f00c00 {
1112 compatible = "allwinn 1112 compatible = "allwinner,sun8i-a83t-r-intc",
1113 "allwinn 1113 "allwinner,sun6i-a31-r-intc";
1114 interrupt-controller; 1114 interrupt-controller;
1115 #interrupt-cells = <3 1115 #interrupt-cells = <3>;
1116 reg = <0x01f00c00 0x4 1116 reg = <0x01f00c00 0x400>;
1117 interrupts = <GIC_SPI 1117 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1118 }; 1118 };
1119 1119
1120 r_ccu: clock@1f01400 { 1120 r_ccu: clock@1f01400 {
1121 compatible = "allwinn 1121 compatible = "allwinner,sun8i-a83t-r-ccu";
1122 reg = <0x01f01400 0x4 1122 reg = <0x01f01400 0x400>;
1123 clocks = <&osc24M>, < 1123 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1124 <&ccu CLK_PL 1124 <&ccu CLK_PLL_PERIPH>;
1125 clock-names = "hosc", 1125 clock-names = "hosc", "losc", "iosc", "pll-periph";
1126 #clock-cells = <1>; 1126 #clock-cells = <1>;
1127 #reset-cells = <1>; 1127 #reset-cells = <1>;
1128 }; 1128 };
1129 1129
1130 cpucfg@1f01c00 { 1130 cpucfg@1f01c00 {
1131 compatible = "allwinn 1131 compatible = "allwinner,sun8i-a83t-r-cpucfg";
1132 reg = <0x1f01c00 0x40 1132 reg = <0x1f01c00 0x400>;
1133 }; 1133 };
1134 1134
1135 r_cir: ir@1f02000 { 1135 r_cir: ir@1f02000 {
1136 compatible = "allwinn 1136 compatible = "allwinner,sun8i-a83t-ir",
1137 "allwinner,su 1137 "allwinner,sun6i-a31-ir";
1138 clocks = <&r_ccu CLK_ 1138 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1139 clock-names = "apb", 1139 clock-names = "apb", "ir";
1140 resets = <&r_ccu RST_ 1140 resets = <&r_ccu RST_APB0_IR>;
1141 interrupts = <GIC_SPI 1141 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1142 reg = <0x01f02000 0x4 1142 reg = <0x01f02000 0x400>;
1143 pinctrl-names = "defa 1143 pinctrl-names = "default";
1144 pinctrl-0 = <&r_cir_p 1144 pinctrl-0 = <&r_cir_pin>;
1145 status = "disabled"; 1145 status = "disabled";
1146 }; 1146 };
1147 1147
1148 r_lradc: lradc@1f03c00 { 1148 r_lradc: lradc@1f03c00 {
1149 compatible = "allwinn 1149 compatible = "allwinner,sun8i-a83t-r-lradc";
1150 reg = <0x01f03c00 0x1 1150 reg = <0x01f03c00 0x100>;
1151 interrupt-parent = <& 1151 interrupt-parent = <&r_intc>;
1152 interrupts = <GIC_SPI 1152 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1153 status = "disabled"; 1153 status = "disabled";
1154 }; 1154 };
1155 1155
1156 r_pio: pinctrl@1f02c00 { 1156 r_pio: pinctrl@1f02c00 {
1157 compatible = "allwinn 1157 compatible = "allwinner,sun8i-a83t-r-pinctrl";
1158 reg = <0x01f02c00 0x4 1158 reg = <0x01f02c00 0x400>;
1159 interrupt-parent = <& 1159 interrupt-parent = <&r_intc>;
1160 interrupts = <GIC_SPI 1160 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&r_ccu CLK_ 1161 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1162 <&osc16Md512 1162 <&osc16Md512>;
1163 clock-names = "apb", 1163 clock-names = "apb", "hosc", "losc";
1164 gpio-controller; 1164 gpio-controller;
1165 #gpio-cells = <3>; 1165 #gpio-cells = <3>;
1166 interrupt-controller; 1166 interrupt-controller;
1167 #interrupt-cells = <3 1167 #interrupt-cells = <3>;
1168 1168
1169 r_cir_pin: r-cir-pin 1169 r_cir_pin: r-cir-pin {
1170 pins = "PL12" 1170 pins = "PL12";
1171 function = "s 1171 function = "s_cir_rx";
1172 }; 1172 };
1173 1173
1174 r_rsb_pins: r-rsb-pin 1174 r_rsb_pins: r-rsb-pins {
1175 pins = "PL0", 1175 pins = "PL0", "PL1";
1176 function = "s 1176 function = "s_rsb";
1177 drive-strengt 1177 drive-strength = <20>;
1178 bias-pull-up; 1178 bias-pull-up;
1179 }; 1179 };
1180 }; 1180 };
1181 1181
1182 r_rsb: rsb@1f03400 { 1182 r_rsb: rsb@1f03400 {
1183 compatible = "allwinn 1183 compatible = "allwinner,sun8i-a83t-rsb",
1184 "allwinn 1184 "allwinner,sun8i-a23-rsb";
1185 reg = <0x01f03400 0x4 1185 reg = <0x01f03400 0x400>;
1186 interrupts = <GIC_SPI 1186 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&r_ccu CLK_ 1187 clocks = <&r_ccu CLK_APB0_RSB>;
1188 clock-frequency = <30 1188 clock-frequency = <3000000>;
1189 resets = <&r_ccu RST_ 1189 resets = <&r_ccu RST_APB0_RSB>;
1190 pinctrl-names = "defa 1190 pinctrl-names = "default";
1191 pinctrl-0 = <&r_rsb_p 1191 pinctrl-0 = <&r_rsb_pins>;
1192 status = "disabled"; 1192 status = "disabled";
1193 #address-cells = <1>; 1193 #address-cells = <1>;
1194 #size-cells = <0>; 1194 #size-cells = <0>;
1195 }; 1195 };
1196 1196
1197 ths: thermal-sensor@1f04000 { 1197 ths: thermal-sensor@1f04000 {
1198 compatible = "allwinn 1198 compatible = "allwinner,sun8i-a83t-ths";
1199 reg = <0x01f04000 0x1 1199 reg = <0x01f04000 0x100>;
1200 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1201 nvmem-cells = <&ths_c 1201 nvmem-cells = <&ths_calibration>;
1202 nvmem-cell-names = "c 1202 nvmem-cell-names = "calibration";
1203 #thermal-sensor-cells 1203 #thermal-sensor-cells = <1>;
1204 }; 1204 };
1205 }; 1205 };
1206 1206
1207 thermal-zones { 1207 thermal-zones {
1208 cpu0_thermal: cpu0-thermal { 1208 cpu0_thermal: cpu0-thermal {
1209 polling-delay-passive 1209 polling-delay-passive = <0>;
1210 polling-delay = <0>; 1210 polling-delay = <0>;
1211 thermal-sensors = <&t 1211 thermal-sensors = <&ths 0>;
1212 1212
1213 trips { 1213 trips {
1214 cpu0_hot: cpu 1214 cpu0_hot: cpu-hot {
1215 tempe 1215 temperature = <80000>;
1216 hyste 1216 hysteresis = <2000>;
1217 type 1217 type = "passive";
1218 }; 1218 };
1219 1219
1220 cpu0_very_hot 1220 cpu0_very_hot: cpu-very-hot {
1221 tempe 1221 temperature = <100000>;
1222 hyste 1222 hysteresis = <0>;
1223 type 1223 type = "critical";
1224 }; 1224 };
1225 }; 1225 };
1226 1226
1227 cooling-maps { 1227 cooling-maps {
1228 cpu-hot-limit 1228 cpu-hot-limit {
1229 trip 1229 trip = <&cpu0_hot>;
1230 cooli 1230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1231 1231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1232 1232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1233 1233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1234 }; 1234 };
1235 }; 1235 };
1236 }; 1236 };
1237 1237
1238 cpu1_thermal: cpu1-thermal { 1238 cpu1_thermal: cpu1-thermal {
1239 polling-delay-passive 1239 polling-delay-passive = <0>;
1240 polling-delay = <0>; 1240 polling-delay = <0>;
1241 thermal-sensors = <&t 1241 thermal-sensors = <&ths 1>;
1242 1242
1243 trips { 1243 trips {
1244 cpu1_hot: cpu 1244 cpu1_hot: cpu-hot {
1245 tempe 1245 temperature = <80000>;
1246 hyste 1246 hysteresis = <2000>;
1247 type 1247 type = "passive";
1248 }; 1248 };
1249 1249
1250 cpu1_very_hot 1250 cpu1_very_hot: cpu-very-hot {
1251 tempe 1251 temperature = <100000>;
1252 hyste 1252 hysteresis = <0>;
1253 type 1253 type = "critical";
1254 }; 1254 };
1255 }; 1255 };
1256 1256
1257 cooling-maps { 1257 cooling-maps {
1258 cpu-hot-limit 1258 cpu-hot-limit {
1259 trip 1259 trip = <&cpu1_hot>;
1260 cooli 1260 cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1261 1261 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1262 1262 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1263 1263 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1264 }; 1264 };
1265 }; 1265 };
1266 }; 1266 };
1267 1267
1268 gpu_thermal: gpu-thermal { 1268 gpu_thermal: gpu-thermal {
1269 polling-delay-passive 1269 polling-delay-passive = <0>;
1270 polling-delay = <0>; 1270 polling-delay = <0>;
1271 thermal-sensors = <&t 1271 thermal-sensors = <&ths 2>;
1272 }; 1272 };
1273 }; 1273 };
1274 }; 1274 };
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