1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it
7 * of the GPL or the X11 license, at your opti
8 * licensing only applies to this file, and no
9 * whole.
10 *
11 * a) This file is free software; you can red
12 * modify it under the terms of the GNU Ge
13 * published by the Free Software Foundati
14 * License, or (at your option) any later
15 *
16 * This file is distributed in the hope th
17 * but WITHOUT ANY WARRANTY; without even
18 * MERCHANTABILITY or FITNESS FOR A PARTIC
19 * GNU General Public License for more det
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of c
24 * obtaining a copy of this software and a
25 * files (the "Software"), to deal in the
26 * restriction, including without limitati
27 * copy, modify, merge, publish, distribut
28 * sell copies of the Software, and to per
29 * Software is furnished to do so, subject
30 * conditions:
31 *
32 * The above copyright notice and this per
33 * included in all copies or substantial p
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
40 * WHETHER IN AN ACTION OF CONTRACT, TORT
41 * FROM, OUT OF OR IN CONNECTION WITH THE
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include <dt-bindings/interrupt-controller/arm
46
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
53
54 / {
55 #address-cells = <2>;
56 #size-cells = <2>;
57 interrupt-parent = <&gic>;
58
59 aliases {
60 ethernet0 = &gmac;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: cpu@0 {
68 compatible = "arm,cort
69 device_type = "cpu";
70 cci-control-port = <&c
71 clock-frequency = <120
72 enable-method = "allwi
73 reg = <0x0>;
74 };
75
76 cpu1: cpu@1 {
77 compatible = "arm,cort
78 device_type = "cpu";
79 cci-control-port = <&c
80 clock-frequency = <120
81 enable-method = "allwi
82 reg = <0x1>;
83 };
84
85 cpu2: cpu@2 {
86 compatible = "arm,cort
87 device_type = "cpu";
88 cci-control-port = <&c
89 clock-frequency = <120
90 enable-method = "allwi
91 reg = <0x2>;
92 };
93
94 cpu3: cpu@3 {
95 compatible = "arm,cort
96 device_type = "cpu";
97 cci-control-port = <&c
98 clock-frequency = <120
99 enable-method = "allwi
100 reg = <0x3>;
101 };
102
103 cpu4: cpu@100 {
104 compatible = "arm,cort
105 device_type = "cpu";
106 cci-control-port = <&c
107 clock-frequency = <180
108 enable-method = "allwi
109 reg = <0x100>;
110 };
111
112 cpu5: cpu@101 {
113 compatible = "arm,cort
114 device_type = "cpu";
115 cci-control-port = <&c
116 clock-frequency = <180
117 enable-method = "allwi
118 reg = <0x101>;
119 };
120
121 cpu6: cpu@102 {
122 compatible = "arm,cort
123 device_type = "cpu";
124 cci-control-port = <&c
125 clock-frequency = <180
126 enable-method = "allwi
127 reg = <0x102>;
128 };
129
130 cpu7: cpu@103 {
131 compatible = "arm,cort
132 device_type = "cpu";
133 cci-control-port = <&c
134 clock-frequency = <180
135 enable-method = "allwi
136 reg = <0x103>;
137 };
138 };
139
140 timer {
141 compatible = "arm,armv7-timer"
142 interrupts = <GIC_PPI 13 (GIC_
143 <GIC_PPI 14 (GIC_
144 <GIC_PPI 11 (GIC_
145 <GIC_PPI 10 (GIC_
146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-confi
148 };
149
150 clocks {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 /*
154 * map 64 bit address range do
155 * as the peripherals are all
156 */
157 ranges = <0 0 0 0x20000000>;
158
159 /*
160 * This clock is actually conf
161 * space. The external 24M osc
162 * the clock switched to an in
163 * normal operation there's no
164 * default is to use the exter
165 * as a fixed clock. Also it i
166 * osc24M mux in the PRCM affe
167 * would also throw all the PL
168 * downstream clocks in the PR
169 */
170 osc24M: clk-24M {
171 #clock-cells = <0>;
172 compatible = "fixed-cl
173 clock-frequency = <240
174 clock-output-names = "
175 };
176
177 /*
178 * The 32k clock is from an ex
179 * AC100 codec/RTC chip. This
180 * board dts files to specify
181 */
182 osc32k: clk-32k {
183 #clock-cells = <0>;
184 compatible = "fixed-fa
185 clock-div = <1>;
186 clock-mult = <1>;
187 clock-output-names = "
188 };
189
190 /*
191 * The following two are dummy
192 * used in the gmac_tx clock.
193 * choose one parent depending
194 * mode, using clk_set_rate au
195 *
196 * The actual TX clock rate is
197 * gmac_tx clock.
198 */
199 mii_phy_tx_clk: mii-phy-tx-clk
200 #clock-cells = <0>;
201 compatible = "fixed-cl
202 clock-frequency = <250
203 clock-output-names = "
204 };
205
206 gmac_int_tx_clk: gmac-int-tx-c
207 #clock-cells = <0>;
208 compatible = "fixed-cl
209 clock-frequency = <125
210 clock-output-names = "
211 };
212
213 gmac_tx_clk: clk@800030 {
214 #clock-cells = <0>;
215 compatible = "allwinne
216 reg = <0x00800030 0x4>
217 clocks = <&mii_phy_tx_
218 clock-output-names = "
219 };
220
221 cpus_clk: clk@8001410 {
222 compatible = "allwinne
223 reg = <0x08001410 0x4>
224 #clock-cells = <0>;
225 clocks = <&osc32k>, <&
226 <&ccu CLK_PLL
227 <&ccu CLK_PLL
228 clock-output-names = "
229 };
230
231 ahbs: clk-ahbs {
232 compatible = "fixed-fa
233 #clock-cells = <0>;
234 clock-div = <1>;
235 clock-mult = <1>;
236 clocks = <&cpus_clk>;
237 clock-output-names = "
238 };
239
240 apbs: clk@800141c {
241 compatible = "allwinne
242 reg = <0x0800141c 0x4>
243 #clock-cells = <0>;
244 clocks = <&ahbs>;
245 clock-output-names = "
246 };
247
248 apbs_gates: clk@8001428 {
249 compatible = "allwinne
250 reg = <0x08001428 0x4>
251 #clock-cells = <1>;
252 clocks = <&apbs>;
253 clock-indices = <0>, <
254 <2>, <
255 <4>, <
256 <6>, <
257 <12>,
258 <16>,
259 <18>,
260 clock-output-names = "
261 "apbs_
262 "apbs_
263 "apbs_
264 "apbs_
265 "apbs_
266 "apbs_
267 };
268
269 r_1wire_clk: clk@8001450 {
270 reg = <0x08001450 0x4>
271 #clock-cells = <0>;
272 compatible = "allwinne
273 clocks = <&osc32k>, <&
274 clock-output-names = "
275 };
276
277 r_ir_clk: clk@8001454 {
278 reg = <0x08001454 0x4>
279 #clock-cells = <0>;
280 compatible = "allwinne
281 clocks = <&osc32k>, <&
282 clock-output-names = "
283 };
284 };
285
286 de: display-engine {
287 compatible = "allwinner,sun9i-
288 allwinner,pipelines = <&fe0>,
289 status = "disabled";
290 };
291
292 soc@20000 {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 /*
297 * map 64 bit address range do
298 * as the peripherals are all
299 */
300 ranges = <0 0 0 0x20000000>;
301
302 sram_b: sram@20000 {
303 /* 256 KiB secure SRAM
304 compatible = "mmio-sra
305 reg = <0x00020000 0x40
306
307 #address-cells = <1>;
308 #size-cells = <1>;
309 ranges = <0 0x00020000
310
311 smp-sram@1000 {
312 /*
313 * This is che
314 * cpu0 should
315 */
316 compatible = "
317 reg = <0x1000
318 };
319 };
320
321 gmac: ethernet@830000 {
322 compatible = "allwinne
323 reg = <0x00830000 0x10
324 interrupts = <GIC_SPI
325 interrupt-names = "mac
326 clocks = <&ccu CLK_BUS
327 clock-names = "stmmace
328 resets = <&ccu RST_BUS
329 reset-names = "stmmace
330 snps,pbl = <2>;
331 snps,fixed-burst;
332 snps,force_sf_dma_mode
333 status = "disabled";
334
335 mdio: mdio {
336 compatible = "
337 #address-cells
338 #size-cells =
339 };
340 };
341
342 ehci0: usb@a00000 {
343 compatible = "allwinne
344 reg = <0x00a00000 0x10
345 interrupts = <GIC_SPI
346 clocks = <&usb_clocks
347 resets = <&usb_clocks
348 phys = <&usbphy1>;
349 phy-names = "usb";
350 status = "disabled";
351 };
352
353 ohci0: usb@a00400 {
354 compatible = "allwinne
355 reg = <0x00a00400 0x10
356 interrupts = <GIC_SPI
357 clocks = <&usb_clocks
358 <&usb_clocks
359 resets = <&usb_clocks
360 phys = <&usbphy1>;
361 phy-names = "usb";
362 status = "disabled";
363 };
364
365 usbphy1: phy@a00800 {
366 compatible = "allwinne
367 reg = <0x00a00800 0x4>
368 clocks = <&usb_clocks
369 clock-names = "phy";
370 resets = <&usb_clocks
371 reset-names = "phy";
372 status = "disabled";
373 #phy-cells = <0>;
374 };
375
376 ehci1: usb@a01000 {
377 compatible = "allwinne
378 reg = <0x00a01000 0x10
379 interrupts = <GIC_SPI
380 clocks = <&usb_clocks
381 resets = <&usb_clocks
382 phys = <&usbphy2>;
383 phy-names = "usb";
384 status = "disabled";
385 };
386
387 usbphy2: phy@a01800 {
388 compatible = "allwinne
389 reg = <0x00a01800 0x4>
390 clocks = <&usb_clocks
391 <&usb_clocks
392 <&usb_clocks
393 clock-names = "phy",
394 "hsic_12
395 "hsic_48
396 resets = <&usb_clocks
397 <&usb_clocks
398 reset-names = "phy",
399 "hsic";
400 status = "disabled";
401 #phy-cells = <0>;
402 /* usb1 is always used
403 phy_type = "hsic";
404 };
405
406 ehci2: usb@a02000 {
407 compatible = "allwinne
408 reg = <0x00a02000 0x10
409 interrupts = <GIC_SPI
410 clocks = <&usb_clocks
411 resets = <&usb_clocks
412 phys = <&usbphy3>;
413 phy-names = "usb";
414 status = "disabled";
415 };
416
417 ohci2: usb@a02400 {
418 compatible = "allwinne
419 reg = <0x00a02400 0x10
420 interrupts = <GIC_SPI
421 clocks = <&usb_clocks
422 <&usb_clocks
423 resets = <&usb_clocks
424 phys = <&usbphy3>;
425 phy-names = "usb";
426 status = "disabled";
427 };
428
429 usbphy3: phy@a02800 {
430 compatible = "allwinne
431 reg = <0x00a02800 0x4>
432 clocks = <&usb_clocks
433 <&usb_clocks
434 <&usb_clocks
435 clock-names = "phy",
436 "hsic_12
437 "hsic_48
438 resets = <&usb_clocks
439 <&usb_clocks
440 reset-names = "phy",
441 "hsic";
442 status = "disabled";
443 #phy-cells = <0>;
444 };
445
446 usb_clocks: clock@a08000 {
447 compatible = "allwinne
448 reg = <0x00a08000 0x8>
449 clocks = <&ccu CLK_BUS
450 clock-names = "bus", "
451 #clock-cells = <1>;
452 #reset-cells = <1>;
453 };
454
455 cpucfg@1700000 {
456 compatible = "allwinne
457 reg = <0x01700000 0x10
458 };
459
460 crypto: crypto@1c02000 {
461 compatible = "allwinne
462 reg = <0x01c02000 0x10
463 interrupts = <GIC_SPI
464 resets = <&ccu RST_BUS
465 clocks = <&ccu CLK_BUS
466 clock-names = "bus", "
467 };
468
469 mmc0: mmc@1c0f000 {
470 compatible = "allwinne
471 reg = <0x01c0f000 0x10
472 clocks = <&mmc_config_
473 <&ccu CLK_MMC
474 <&ccu CLK_MMC
475 clock-names = "ahb", "
476 resets = <&mmc_config_
477 reset-names = "ahb";
478 interrupts = <GIC_SPI
479 status = "disabled";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 };
483
484 mmc1: mmc@1c10000 {
485 compatible = "allwinne
486 reg = <0x01c10000 0x10
487 clocks = <&mmc_config_
488 <&ccu CLK_MMC
489 <&ccu CLK_MMC
490 clock-names = "ahb", "
491 resets = <&mmc_config_
492 reset-names = "ahb";
493 interrupts = <GIC_SPI
494 status = "disabled";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 };
498
499 mmc2: mmc@1c11000 {
500 compatible = "allwinne
501 reg = <0x01c11000 0x10
502 clocks = <&mmc_config_
503 <&ccu CLK_MMC
504 <&ccu CLK_MMC
505 clock-names = "ahb", "
506 resets = <&mmc_config_
507 reset-names = "ahb";
508 interrupts = <GIC_SPI
509 status = "disabled";
510 #address-cells = <1>;
511 #size-cells = <0>;
512 };
513
514 mmc3: mmc@1c12000 {
515 compatible = "allwinne
516 reg = <0x01c12000 0x10
517 clocks = <&mmc_config_
518 <&ccu CLK_MMC
519 <&ccu CLK_MMC
520 clock-names = "ahb", "
521 resets = <&mmc_config_
522 reset-names = "ahb";
523 interrupts = <GIC_SPI
524 status = "disabled";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 };
528
529 mmc_config_clk: clk@1c13000 {
530 compatible = "allwinne
531 reg = <0x01c13000 0x10
532 clocks = <&ccu CLK_BUS
533 resets = <&ccu RST_BUS
534 #clock-cells = <1>;
535 #reset-cells = <1>;
536 clock-output-names = "
537 "
538 };
539
540 gic: interrupt-controller@1c41
541 compatible = "arm,gic-
542 reg = <0x01c41000 0x10
543 <0x01c42000 0x20
544 <0x01c44000 0x20
545 <0x01c46000 0x20
546 interrupt-controller;
547 #interrupt-cells = <3>
548 interrupts = <GIC_PPI
549 };
550
551 cci: cci@1c90000 {
552 compatible = "arm,cci-
553 #address-cells = <1>;
554 #size-cells = <1>;
555 reg = <0x01c90000 0x10
556 ranges = <0x0 0x01c900
557
558 cci_control0: slave-if
559 compatible = "
560 interface-type
561 reg = <0x4000
562 };
563
564 cci_control1: slave-if
565 compatible = "
566 interface-type
567 reg = <0x5000
568 };
569
570 pmu@9000 {
571 compatible =
572 reg = <0x9000
573 interrupts =
574
575
576
577
578 };
579 };
580
581 de_clocks: clock@3000000 {
582 compatible = "allwinne
583 reg = <0x03000000 0x30
584 clocks = <&ccu CLK_DE>
585 <&ccu CLK_SDR
586 <&ccu CLK_BUS
587 clock-names = "mod",
588 "dram",
589 "bus";
590 resets = <&ccu RST_BUS
591 #clock-cells = <1>;
592 #reset-cells = <1>;
593 };
594
595 fe0: display-frontend@3100000
596 compatible = "allwinne
597 reg = <0x03100000 0x40
598 interrupts = <GIC_SPI
599 clocks = <&de_clocks C
600 <&de_clocks C
601 clock-names = "ahb", "
602 "ram";
603 resets = <&de_clocks R
604
605 ports {
606 #address-cells
607 #size-cells =
608
609 fe0_out: port@
610 reg =
611
612 fe0_ou
613
614 };
615 };
616 };
617 };
618
619 fe1: display-frontend@3140000
620 compatible = "allwinne
621 reg = <0x03140000 0x40
622 interrupts = <GIC_SPI
623 clocks = <&de_clocks C
624 <&de_clocks C
625 clock-names = "ahb", "
626 "ram";
627 resets = <&de_clocks R
628
629 ports {
630 #address-cells
631 #size-cells =
632
633 fe1_out: port@
634 reg =
635
636 fe1_ou
637
638 };
639 };
640 };
641 };
642
643 be0: display-backend@3200000 {
644 compatible = "allwinne
645 reg = <0x03200000 0x40
646 interrupts = <GIC_SPI
647 clocks = <&de_clocks C
648 <&de_clocks C
649 clock-names = "ahb", "
650 "ram";
651 resets = <&de_clocks R
652
653 ports {
654 #address-cells
655 #size-cells =
656
657 be0_in: port@0
658 #addre
659 #size-
660 reg =
661
662 be0_in
663
664
665 };
666
667 be0_in
668
669
670 };
671 };
672
673 be0_out: port@
674 reg =
675
676 be0_ou
677
678 };
679 };
680 };
681 };
682
683 be1: display-backend@3240000 {
684 compatible = "allwinne
685 reg = <0x03240000 0x40
686 interrupts = <GIC_SPI
687 clocks = <&de_clocks C
688 <&de_clocks C
689 clock-names = "ahb", "
690 "ram";
691 resets = <&de_clocks R
692
693 ports {
694 #address-cells
695 #size-cells =
696
697 be1_in: port@0
698 #addre
699 #size-
700 reg =
701
702 be1_in
703
704
705 };
706
707 be1_in
708
709
710 };
711 };
712
713 be1_out: port@
714 reg =
715
716 be1_ou
717
718 };
719 };
720 };
721 };
722
723 deu0: deu@3300000 {
724 compatible = "allwinne
725 reg = <0x03300000 0x40
726 interrupts = <GIC_SPI
727 clocks = <&de_clocks C
728 <&de_clocks C
729 <&de_clocks C
730 clock-names = "ahb",
731 "mod",
732 "ram";
733 resets = <&de_clocks R
734
735 ports {
736 #address-cells
737 #size-cells =
738
739 deu0_in: port@
740 reg =
741
742 deu0_i
743
744 };
745 };
746
747 deu0_out: port
748 #addre
749 #size-
750 reg =
751
752 deu0_o
753
754
755 };
756
757 deu0_o
758
759
760 };
761 };
762 };
763 };
764
765 deu1: deu@3340000 {
766 compatible = "allwinne
767 reg = <0x03340000 0x40
768 interrupts = <GIC_SPI
769 clocks = <&de_clocks C
770 <&de_clocks C
771 <&de_clocks C
772 clock-names = "ahb",
773 "mod",
774 "ram";
775 resets = <&de_clocks R
776
777 ports {
778 #address-cells
779 #size-cells =
780
781 deu1_in: port@
782 reg =
783
784 deu1_i
785
786 };
787 };
788
789 deu1_out: port
790 #addre
791 #size-
792 reg =
793
794 deu1_o
795
796
797 };
798
799 deu1_o
800
801
802 };
803 };
804 };
805 };
806
807 drc0: drc@3400000 {
808 compatible = "allwinne
809 reg = <0x03400000 0x40
810 interrupts = <GIC_SPI
811 clocks = <&de_clocks C
812 <&de_clocks C
813 <&de_clocks C
814 clock-names = "ahb",
815 "mod",
816 "ram";
817 resets = <&de_clocks R
818
819 ports {
820 #address-cells
821 #size-cells =
822
823 drc0_in: port@
824 reg =
825
826 drc0_i
827
828 };
829 };
830
831 drc0_out: port
832 reg =
833
834 drc0_o
835
836 };
837 };
838 };
839 };
840
841 drc1: drc@3440000 {
842 compatible = "allwinne
843 reg = <0x03440000 0x40
844 interrupts = <GIC_SPI
845 clocks = <&de_clocks C
846 <&de_clocks C
847 <&de_clocks C
848 clock-names = "ahb",
849 "mod",
850 "ram";
851 resets = <&de_clocks R
852
853 ports {
854 #address-cells
855 #size-cells =
856
857 drc1_in: port@
858 reg =
859
860 drc1_i
861
862 };
863 };
864
865 drc1_out: port
866 reg =
867
868 drc1_o
869
870 };
871 };
872 };
873 };
874
875 tcon0: lcd-controller@3c00000
876 compatible = "allwinne
877 reg = <0x03c00000 0x10
878 interrupts = <GIC_SPI
879 clocks = <&ccu CLK_BUS
880 clock-names = "ahb", "
881 resets = <&ccu RST_BUS
882 <&ccu RST_BUS
883 <&ccu RST_BUS
884 reset-names = "lcd",
885 "edp",
886 "lvds";
887 clock-output-names = "
888 #clock-cells = <0>;
889
890 ports {
891 #address-cells
892 #size-cells =
893
894 tcon0_in: port
895 reg =
896
897 tcon0_
898
899 };
900 };
901
902 tcon0_out: por
903 reg =
904 };
905 };
906 };
907
908 tcon1: lcd-controller@3c10000
909 compatible = "allwinne
910 reg = <0x03c10000 0x10
911 interrupts = <GIC_SPI
912 clocks = <&ccu CLK_BUS
913 clock-names = "ahb", "
914 resets = <&ccu RST_BUS
915 reset-names = "lcd", "
916
917 ports {
918 #address-cells
919 #size-cells =
920
921 tcon1_in: port
922 reg =
923
924 tcon1_
925
926 };
927 };
928
929 tcon1_out: por
930 reg =
931 };
932 };
933 };
934
935 ccu: clock@6000000 {
936 compatible = "allwinne
937 reg = <0x06000000 0x80
938 clocks = <&osc24M>, <&
939 clock-names = "hosc",
940 #clock-cells = <1>;
941 #reset-cells = <1>;
942 };
943
944 timer@6000c00 {
945 compatible = "allwinne
946 reg = <0x06000c00 0xa0
947 interrupts = <GIC_SPI
948 <GIC_SPI
949 <GIC_SPI
950 <GIC_SPI
951 <GIC_SPI
952 <GIC_SPI
953
954 clocks = <&osc24M>;
955 };
956
957 wdt: watchdog@6000ca0 {
958 compatible = "allwinne
959 reg = <0x06000ca0 0x20
960 interrupts = <GIC_SPI
961 clocks = <&osc24M>;
962 };
963
964 pio: pinctrl@6000800 {
965 compatible = "allwinne
966 reg = <0x06000800 0x40
967 interrupts = <GIC_SPI
968 <GIC_SPI
969 <GIC_SPI
970 <GIC_SPI
971 <GIC_SPI
972 clocks = <&ccu CLK_BUS
973 clock-names = "apb", "
974 gpio-controller;
975 interrupt-controller;
976 #interrupt-cells = <3>
977 #gpio-cells = <3>;
978
979 gmac_rgmii_pins: gmac-
980 pins = "PA0",
981 "PA7",
982 "PA13",
983 function = "gm
984 /*
985 * data lines
986 * and need a
987 */
988 drive-strength
989 };
990
991 i2c3_pins: i2c3-pins {
992 pins = "PG10",
993 function = "i2
994 };
995
996 lcd0_rgb888_pins: lcd0
997 pins = "PD0",
998 "PD4",
999 "PD8",
1000 "PD12"
1001 "PD16"
1002 "PD20"
1003 "PD24"
1004 function = "l
1005 };
1006
1007 mmc0_pins: mmc0-pins
1008 pins = "PF0",
1009 "PF4",
1010 function = "m
1011 drive-strengt
1012 bias-pull-up;
1013 };
1014
1015 mmc1_pins: mmc1-pins
1016 pins = "PG0",
1017
1018 function = "m
1019 drive-strengt
1020 bias-pull-up;
1021 };
1022
1023 mmc2_8bit_pins: mmc2-
1024 pins = "PC6",
1025 "PC10"
1026 "PC13"
1027 "PC16"
1028 function = "m
1029 drive-strengt
1030 bias-pull-up;
1031 };
1032
1033 uart0_ph_pins: uart0-
1034 pins = "PH12"
1035 function = "u
1036 };
1037
1038 uart4_pins: uart4-pin
1039 pins = "PG12"
1040 function = "u
1041 };
1042 };
1043
1044 uart0: serial@7000000 {
1045 compatible = "snps,dw
1046 reg = <0x07000000 0x4
1047 interrupts = <GIC_SPI
1048 reg-shift = <2>;
1049 reg-io-width = <4>;
1050 clocks = <&ccu CLK_BU
1051 resets = <&ccu RST_BU
1052 status = "disabled";
1053 };
1054
1055 uart1: serial@7000400 {
1056 compatible = "snps,dw
1057 reg = <0x07000400 0x4
1058 interrupts = <GIC_SPI
1059 reg-shift = <2>;
1060 reg-io-width = <4>;
1061 clocks = <&ccu CLK_BU
1062 resets = <&ccu RST_BU
1063 status = "disabled";
1064 };
1065
1066 uart2: serial@7000800 {
1067 compatible = "snps,dw
1068 reg = <0x07000800 0x4
1069 interrupts = <GIC_SPI
1070 reg-shift = <2>;
1071 reg-io-width = <4>;
1072 clocks = <&ccu CLK_BU
1073 resets = <&ccu RST_BU
1074 status = "disabled";
1075 };
1076
1077 uart3: serial@7000c00 {
1078 compatible = "snps,dw
1079 reg = <0x07000c00 0x4
1080 interrupts = <GIC_SPI
1081 reg-shift = <2>;
1082 reg-io-width = <4>;
1083 clocks = <&ccu CLK_BU
1084 resets = <&ccu RST_BU
1085 status = "disabled";
1086 };
1087
1088 uart4: serial@7001000 {
1089 compatible = "snps,dw
1090 reg = <0x07001000 0x4
1091 interrupts = <GIC_SPI
1092 reg-shift = <2>;
1093 reg-io-width = <4>;
1094 clocks = <&ccu CLK_BU
1095 resets = <&ccu RST_BU
1096 status = "disabled";
1097 };
1098
1099 uart5: serial@7001400 {
1100 compatible = "snps,dw
1101 reg = <0x07001400 0x4
1102 interrupts = <GIC_SPI
1103 reg-shift = <2>;
1104 reg-io-width = <4>;
1105 clocks = <&ccu CLK_BU
1106 resets = <&ccu RST_BU
1107 status = "disabled";
1108 };
1109
1110 i2c0: i2c@7002800 {
1111 compatible = "allwinn
1112 reg = <0x07002800 0x4
1113 interrupts = <GIC_SPI
1114 clocks = <&ccu CLK_BU
1115 resets = <&ccu RST_BU
1116 status = "disabled";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 };
1120
1121 i2c1: i2c@7002c00 {
1122 compatible = "allwinn
1123 reg = <0x07002c00 0x4
1124 interrupts = <GIC_SPI
1125 clocks = <&ccu CLK_BU
1126 resets = <&ccu RST_BU
1127 status = "disabled";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 };
1131
1132 i2c2: i2c@7003000 {
1133 compatible = "allwinn
1134 reg = <0x07003000 0x4
1135 interrupts = <GIC_SPI
1136 clocks = <&ccu CLK_BU
1137 resets = <&ccu RST_BU
1138 status = "disabled";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 };
1142
1143 i2c3: i2c@7003400 {
1144 compatible = "allwinn
1145 reg = <0x07003400 0x4
1146 interrupts = <GIC_SPI
1147 clocks = <&ccu CLK_BU
1148 resets = <&ccu RST_BU
1149 status = "disabled";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152 };
1153
1154 i2c4: i2c@7003800 {
1155 compatible = "allwinn
1156 reg = <0x07003800 0x4
1157 interrupts = <GIC_SPI
1158 clocks = <&ccu CLK_BU
1159 resets = <&ccu RST_BU
1160 status = "disabled";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163 };
1164
1165 r_wdt: watchdog@8001000 {
1166 compatible = "allwinn
1167 reg = <0x08001000 0x2
1168 interrupts = <GIC_SPI
1169 clocks = <&osc24M>;
1170 };
1171
1172 prcm@8001400 {
1173 compatible = "allwinn
1174 reg = <0x08001400 0x2
1175 };
1176
1177 apbs_rst: reset@80014b0 {
1178 reg = <0x080014b0 0x4
1179 compatible = "allwinn
1180 #reset-cells = <1>;
1181 };
1182
1183 nmi_intc: interrupt-controlle
1184 compatible = "allwinn
1185 interrupt-controller;
1186 #interrupt-cells = <2
1187 reg = <0x080015a0 0xc
1188 interrupts = <GIC_SPI
1189 };
1190
1191 r_ir: ir@8002000 {
1192 compatible = "allwinn
1193 interrupts = <GIC_SPI
1194 pinctrl-names = "defa
1195 pinctrl-0 = <&r_ir_pi
1196 clocks = <&apbs_gates
1197 clock-names = "apb",
1198 resets = <&apbs_rst 1
1199 reg = <0x08002000 0x4
1200 status = "disabled";
1201 };
1202
1203 r_uart: serial@8002800 {
1204 compatible = "snps,dw
1205 reg = <0x08002800 0x4
1206 interrupts = <GIC_SPI
1207 reg-shift = <2>;
1208 reg-io-width = <4>;
1209 clocks = <&apbs_gates
1210 resets = <&apbs_rst 4
1211 status = "disabled";
1212 };
1213
1214 r_pio: pinctrl@8002c00 {
1215 compatible = "allwinn
1216 reg = <0x08002c00 0x4
1217 interrupts = <GIC_SPI
1218 <GIC_SPI
1219 clocks = <&apbs_gates
1220 clock-names = "apb",
1221 gpio-controller;
1222 interrupt-controller;
1223 #interrupt-cells = <3
1224 #gpio-cells = <3>;
1225
1226 r_ir_pins: r-ir-pins
1227 pins = "PL6";
1228 function = "s
1229 };
1230
1231 r_rsb_pins: r-rsb-pin
1232 pins = "PN0",
1233 function = "s
1234 drive-strengt
1235 bias-pull-up;
1236 };
1237 };
1238
1239 r_rsb: rsb@8003400 {
1240 compatible = "allwinn
1241 reg = <0x08003400 0x4
1242 interrupts = <GIC_SPI
1243 clocks = <&apbs_gates
1244 clock-frequency = <30
1245 resets = <&apbs_rst 3
1246 pinctrl-names = "defa
1247 pinctrl-0 = <&r_rsb_p
1248 status = "disabled";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 };
1252 };
1253 };
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