1 /* 1 /*
2 * Copyright 2014 Chen-Yu Tsai 2 * Copyright 2014 Chen-Yu Tsai
3 * 3 *
4 * Chen-Yu Tsai <wens@csie.org> 4 * Chen-Yu Tsai <wens@csie.org>
5 * 5 *
6 * This file is dual-licensed: you can use it 6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your opti 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and no 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This file is free software; you can red 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Ge 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundati 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later 14 * License, or (at your option) any later version.
15 * 15 *
16 * This file is distributed in the hope th 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTIC 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more det 19 * GNU General Public License for more details.
20 * 20 *
21 * Or, alternatively, 21 * Or, alternatively,
22 * 22 *
23 * b) Permission is hereby granted, free of c 23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and a 24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the 25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitati 26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribut 27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to per 28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject 29 * Software is furnished to do so, subject to the following
30 * conditions: 30 * conditions:
31 * 31 *
32 * The above copyright notice and this per 32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial p 33 * included in all copies or substantial portions of the Software.
34 * 34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45 #include <dt-bindings/interrupt-controller/arm 45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 46
47 #include <dt-bindings/clock/sun9i-a80-ccu.h> 47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h> 48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h> 49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h> 50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h> 51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h> 52 #include <dt-bindings/reset/sun9i-a80-usb.h>
53 53
54 / { 54 / {
55 #address-cells = <2>; 55 #address-cells = <2>;
56 #size-cells = <2>; 56 #size-cells = <2>;
57 interrupt-parent = <&gic>; 57 interrupt-parent = <&gic>;
58 58
59 aliases { 59 aliases {
60 ethernet0 = &gmac; 60 ethernet0 = &gmac;
61 }; 61 };
62 62
63 cpus { 63 cpus {
64 #address-cells = <1>; 64 #address-cells = <1>;
65 #size-cells = <0>; 65 #size-cells = <0>;
66 66
67 cpu0: cpu@0 { 67 cpu0: cpu@0 {
68 compatible = "arm,cort 68 compatible = "arm,cortex-a7";
69 device_type = "cpu"; 69 device_type = "cpu";
70 cci-control-port = <&c 70 cci-control-port = <&cci_control0>;
71 clock-frequency = <120 71 clock-frequency = <12000000>;
72 enable-method = "allwi 72 enable-method = "allwinner,sun9i-a80-smp";
73 reg = <0x0>; 73 reg = <0x0>;
74 }; 74 };
75 75
76 cpu1: cpu@1 { 76 cpu1: cpu@1 {
77 compatible = "arm,cort 77 compatible = "arm,cortex-a7";
78 device_type = "cpu"; 78 device_type = "cpu";
79 cci-control-port = <&c 79 cci-control-port = <&cci_control0>;
80 clock-frequency = <120 80 clock-frequency = <12000000>;
81 enable-method = "allwi 81 enable-method = "allwinner,sun9i-a80-smp";
82 reg = <0x1>; 82 reg = <0x1>;
83 }; 83 };
84 84
85 cpu2: cpu@2 { 85 cpu2: cpu@2 {
86 compatible = "arm,cort 86 compatible = "arm,cortex-a7";
87 device_type = "cpu"; 87 device_type = "cpu";
88 cci-control-port = <&c 88 cci-control-port = <&cci_control0>;
89 clock-frequency = <120 89 clock-frequency = <12000000>;
90 enable-method = "allwi 90 enable-method = "allwinner,sun9i-a80-smp";
91 reg = <0x2>; 91 reg = <0x2>;
92 }; 92 };
93 93
94 cpu3: cpu@3 { 94 cpu3: cpu@3 {
95 compatible = "arm,cort 95 compatible = "arm,cortex-a7";
96 device_type = "cpu"; 96 device_type = "cpu";
97 cci-control-port = <&c 97 cci-control-port = <&cci_control0>;
98 clock-frequency = <120 98 clock-frequency = <12000000>;
99 enable-method = "allwi 99 enable-method = "allwinner,sun9i-a80-smp";
100 reg = <0x3>; 100 reg = <0x3>;
101 }; 101 };
102 102
103 cpu4: cpu@100 { 103 cpu4: cpu@100 {
104 compatible = "arm,cort 104 compatible = "arm,cortex-a15";
105 device_type = "cpu"; 105 device_type = "cpu";
106 cci-control-port = <&c 106 cci-control-port = <&cci_control1>;
107 clock-frequency = <180 107 clock-frequency = <18000000>;
108 enable-method = "allwi 108 enable-method = "allwinner,sun9i-a80-smp";
109 reg = <0x100>; 109 reg = <0x100>;
110 }; 110 };
111 111
112 cpu5: cpu@101 { 112 cpu5: cpu@101 {
113 compatible = "arm,cort 113 compatible = "arm,cortex-a15";
114 device_type = "cpu"; 114 device_type = "cpu";
115 cci-control-port = <&c 115 cci-control-port = <&cci_control1>;
116 clock-frequency = <180 116 clock-frequency = <18000000>;
117 enable-method = "allwi 117 enable-method = "allwinner,sun9i-a80-smp";
118 reg = <0x101>; 118 reg = <0x101>;
119 }; 119 };
120 120
121 cpu6: cpu@102 { 121 cpu6: cpu@102 {
122 compatible = "arm,cort 122 compatible = "arm,cortex-a15";
123 device_type = "cpu"; 123 device_type = "cpu";
124 cci-control-port = <&c 124 cci-control-port = <&cci_control1>;
125 clock-frequency = <180 125 clock-frequency = <18000000>;
126 enable-method = "allwi 126 enable-method = "allwinner,sun9i-a80-smp";
127 reg = <0x102>; 127 reg = <0x102>;
128 }; 128 };
129 129
130 cpu7: cpu@103 { 130 cpu7: cpu@103 {
131 compatible = "arm,cort 131 compatible = "arm,cortex-a15";
132 device_type = "cpu"; 132 device_type = "cpu";
133 cci-control-port = <&c 133 cci-control-port = <&cci_control1>;
134 clock-frequency = <180 134 clock-frequency = <18000000>;
135 enable-method = "allwi 135 enable-method = "allwinner,sun9i-a80-smp";
136 reg = <0x103>; 136 reg = <0x103>;
137 }; 137 };
138 }; 138 };
139 139
140 timer { 140 timer {
141 compatible = "arm,armv7-timer" 141 compatible = "arm,armv7-timer";
142 interrupts = <GIC_PPI 13 (GIC_ 142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_ 143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 11 (GIC_ 144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 10 (GIC_ 145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146 clock-frequency = <24000000>; 146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-confi 147 arm,cpu-registers-not-fw-configured;
148 }; 148 };
149 149
150 clocks { 150 clocks {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 /* 153 /*
154 * map 64 bit address range do 154 * map 64 bit address range down to 32 bits,
155 * as the peripherals are all 155 * as the peripherals are all under 512MB.
156 */ 156 */
157 ranges = <0 0 0 0x20000000>; 157 ranges = <0 0 0 0x20000000>;
158 158
159 /* 159 /*
160 * This clock is actually conf 160 * This clock is actually configurable from the PRCM address
161 * space. The external 24M osc 161 * space. The external 24M oscillator can be turned off, and
162 * the clock switched to an in 162 * the clock switched to an internal 16M RC oscillator. Under
163 * normal operation there's no 163 * normal operation there's no reason to do this, and the
164 * default is to use the exter 164 * default is to use the external good one, so just model this
165 * as a fixed clock. Also it i 165 * as a fixed clock. Also it is not entirely clear if the
166 * osc24M mux in the PRCM affe 166 * osc24M mux in the PRCM affects the entire clock tree, which
167 * would also throw all the PL 167 * would also throw all the PLL clock rates off, or just the
168 * downstream clocks in the PR 168 * downstream clocks in the PRCM.
169 */ 169 */
170 osc24M: clk-24M { 170 osc24M: clk-24M {
171 #clock-cells = <0>; 171 #clock-cells = <0>;
172 compatible = "fixed-cl 172 compatible = "fixed-clock";
173 clock-frequency = <240 173 clock-frequency = <24000000>;
174 clock-output-names = " 174 clock-output-names = "osc24M";
175 }; 175 };
176 176
177 /* 177 /*
178 * The 32k clock is from an ex 178 * The 32k clock is from an external source, normally the
179 * AC100 codec/RTC chip. This 179 * AC100 codec/RTC chip. This serves as a placeholder for
180 * board dts files to specify 180 * board dts files to specify the source.
181 */ 181 */
182 osc32k: clk-32k { 182 osc32k: clk-32k {
183 #clock-cells = <0>; 183 #clock-cells = <0>;
184 compatible = "fixed-fa 184 compatible = "fixed-factor-clock";
185 clock-div = <1>; 185 clock-div = <1>;
186 clock-mult = <1>; 186 clock-mult = <1>;
187 clock-output-names = " 187 clock-output-names = "osc32k";
188 }; 188 };
189 189
190 /* 190 /*
191 * The following two are dummy 191 * The following two are dummy clocks, placeholders
192 * used in the gmac_tx clock. 192 * used in the gmac_tx clock. The gmac driver will
193 * choose one parent depending 193 * choose one parent depending on the PHY interface
194 * mode, using clk_set_rate au 194 * mode, using clk_set_rate auto-reparenting.
195 * 195 *
196 * The actual TX clock rate is 196 * The actual TX clock rate is not controlled by the
197 * gmac_tx clock. 197 * gmac_tx clock.
198 */ 198 */
199 mii_phy_tx_clk: mii-phy-tx-clk 199 mii_phy_tx_clk: mii-phy-tx-clk {
200 #clock-cells = <0>; 200 #clock-cells = <0>;
201 compatible = "fixed-cl 201 compatible = "fixed-clock";
202 clock-frequency = <250 202 clock-frequency = <25000000>;
203 clock-output-names = " 203 clock-output-names = "mii_phy_tx";
204 }; 204 };
205 205
206 gmac_int_tx_clk: gmac-int-tx-c 206 gmac_int_tx_clk: gmac-int-tx-clk {
207 #clock-cells = <0>; 207 #clock-cells = <0>;
208 compatible = "fixed-cl 208 compatible = "fixed-clock";
209 clock-frequency = <125 209 clock-frequency = <125000000>;
210 clock-output-names = " 210 clock-output-names = "gmac_int_tx";
211 }; 211 };
212 212
213 gmac_tx_clk: clk@800030 { 213 gmac_tx_clk: clk@800030 {
214 #clock-cells = <0>; 214 #clock-cells = <0>;
215 compatible = "allwinne 215 compatible = "allwinner,sun7i-a20-gmac-clk";
216 reg = <0x00800030 0x4> 216 reg = <0x00800030 0x4>;
217 clocks = <&mii_phy_tx_ 217 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218 clock-output-names = " 218 clock-output-names = "gmac_tx";
219 }; 219 };
220 220
221 cpus_clk: clk@8001410 { 221 cpus_clk: clk@8001410 {
222 compatible = "allwinne 222 compatible = "allwinner,sun9i-a80-cpus-clk";
223 reg = <0x08001410 0x4> 223 reg = <0x08001410 0x4>;
224 #clock-cells = <0>; 224 #clock-cells = <0>;
225 clocks = <&osc32k>, <& 225 clocks = <&osc32k>, <&osc24M>,
226 <&ccu CLK_PLL 226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL 227 <&ccu CLK_PLL_AUDIO>;
228 clock-output-names = " 228 clock-output-names = "cpus";
229 }; 229 };
230 230
231 ahbs: clk-ahbs { 231 ahbs: clk-ahbs {
232 compatible = "fixed-fa 232 compatible = "fixed-factor-clock";
233 #clock-cells = <0>; 233 #clock-cells = <0>;
234 clock-div = <1>; 234 clock-div = <1>;
235 clock-mult = <1>; 235 clock-mult = <1>;
236 clocks = <&cpus_clk>; 236 clocks = <&cpus_clk>;
237 clock-output-names = " 237 clock-output-names = "ahbs";
238 }; 238 };
239 239
240 apbs: clk@800141c { 240 apbs: clk@800141c {
241 compatible = "allwinne 241 compatible = "allwinner,sun8i-a23-apb0-clk";
242 reg = <0x0800141c 0x4> 242 reg = <0x0800141c 0x4>;
243 #clock-cells = <0>; 243 #clock-cells = <0>;
244 clocks = <&ahbs>; 244 clocks = <&ahbs>;
245 clock-output-names = " 245 clock-output-names = "apbs";
246 }; 246 };
247 247
248 apbs_gates: clk@8001428 { 248 apbs_gates: clk@8001428 {
249 compatible = "allwinne 249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250 reg = <0x08001428 0x4> 250 reg = <0x08001428 0x4>;
251 #clock-cells = <1>; 251 #clock-cells = <1>;
252 clocks = <&apbs>; 252 clocks = <&apbs>;
253 clock-indices = <0>, < 253 clock-indices = <0>, <1>,
254 <2>, < 254 <2>, <3>,
255 <4>, < 255 <4>, <5>,
256 <6>, < 256 <6>, <7>,
257 <12>, 257 <12>, <13>,
258 <16>, 258 <16>, <17>,
259 <18>, 259 <18>, <20>;
260 clock-output-names = " 260 clock-output-names = "apbs_pio", "apbs_ir",
261 "apbs_ 261 "apbs_timer", "apbs_rsb",
262 "apbs_ 262 "apbs_uart", "apbs_1wire",
263 "apbs_ 263 "apbs_i2c0", "apbs_i2c1",
264 "apbs_ 264 "apbs_ps2_0", "apbs_ps2_1",
265 "apbs_ 265 "apbs_dma", "apbs_i2s0",
266 "apbs_ 266 "apbs_i2s1", "apbs_twd";
267 }; 267 };
268 268
269 r_1wire_clk: clk@8001450 { 269 r_1wire_clk: clk@8001450 {
270 reg = <0x08001450 0x4> 270 reg = <0x08001450 0x4>;
271 #clock-cells = <0>; 271 #clock-cells = <0>;
272 compatible = "allwinne 272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 clocks = <&osc32k>, <& 273 clocks = <&osc32k>, <&osc24M>;
274 clock-output-names = " 274 clock-output-names = "r_1wire";
275 }; 275 };
276 276
277 r_ir_clk: clk@8001454 { 277 r_ir_clk: clk@8001454 {
278 reg = <0x08001454 0x4> 278 reg = <0x08001454 0x4>;
279 #clock-cells = <0>; 279 #clock-cells = <0>;
280 compatible = "allwinne 280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 clocks = <&osc32k>, <& 281 clocks = <&osc32k>, <&osc24M>;
282 clock-output-names = " 282 clock-output-names = "r_ir";
283 }; 283 };
284 }; 284 };
285 285
286 de: display-engine { 286 de: display-engine {
287 compatible = "allwinner,sun9i- 287 compatible = "allwinner,sun9i-a80-display-engine";
288 allwinner,pipelines = <&fe0>, 288 allwinner,pipelines = <&fe0>, <&fe1>;
289 status = "disabled"; 289 status = "disabled";
290 }; 290 };
291 291
292 soc@20000 { 292 soc@20000 {
293 compatible = "simple-bus"; 293 compatible = "simple-bus";
294 #address-cells = <1>; 294 #address-cells = <1>;
295 #size-cells = <1>; 295 #size-cells = <1>;
296 /* 296 /*
297 * map 64 bit address range do 297 * map 64 bit address range down to 32 bits,
298 * as the peripherals are all 298 * as the peripherals are all under 512MB.
299 */ 299 */
300 ranges = <0 0 0 0x20000000>; 300 ranges = <0 0 0 0x20000000>;
301 301
302 sram_b: sram@20000 { 302 sram_b: sram@20000 {
303 /* 256 KiB secure SRAM 303 /* 256 KiB secure SRAM at 0x20000 */
304 compatible = "mmio-sra 304 compatible = "mmio-sram";
305 reg = <0x00020000 0x40 305 reg = <0x00020000 0x40000>;
306 306
307 #address-cells = <1>; 307 #address-cells = <1>;
308 #size-cells = <1>; 308 #size-cells = <1>;
309 ranges = <0 0x00020000 309 ranges = <0 0x00020000 0x40000>;
310 310
311 smp-sram@1000 { 311 smp-sram@1000 {
312 /* 312 /*
313 * This is che 313 * This is checked by BROM to determine if
314 * cpu0 should 314 * cpu0 should jump to SMP entry vector
315 */ 315 */
316 compatible = " 316 compatible = "allwinner,sun9i-a80-smp-sram";
317 reg = <0x1000 317 reg = <0x1000 0x8>;
318 }; 318 };
319 }; 319 };
320 320
321 gmac: ethernet@830000 { 321 gmac: ethernet@830000 {
322 compatible = "allwinne 322 compatible = "allwinner,sun7i-a20-gmac";
323 reg = <0x00830000 0x10 323 reg = <0x00830000 0x1054>;
324 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "mac 325 interrupt-names = "macirq";
326 clocks = <&ccu CLK_BUS 326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327 clock-names = "stmmace 327 clock-names = "stmmaceth", "allwinner_gmac_tx";
328 resets = <&ccu RST_BUS 328 resets = <&ccu RST_BUS_GMAC>;
329 reset-names = "stmmace 329 reset-names = "stmmaceth";
330 snps,pbl = <2>; 330 snps,pbl = <2>;
331 snps,fixed-burst; 331 snps,fixed-burst;
332 snps,force_sf_dma_mode 332 snps,force_sf_dma_mode;
333 status = "disabled"; 333 status = "disabled";
334 334
335 mdio: mdio { 335 mdio: mdio {
336 compatible = " 336 compatible = "snps,dwmac-mdio";
337 #address-cells 337 #address-cells = <1>;
338 #size-cells = 338 #size-cells = <0>;
339 }; 339 };
340 }; 340 };
341 341
342 ehci0: usb@a00000 { 342 ehci0: usb@a00000 {
343 compatible = "allwinne 343 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
344 reg = <0x00a00000 0x10 344 reg = <0x00a00000 0x100>;
345 interrupts = <GIC_SPI 345 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&usb_clocks 346 clocks = <&usb_clocks CLK_BUS_HCI0>;
347 resets = <&usb_clocks 347 resets = <&usb_clocks RST_USB0_HCI>;
348 phys = <&usbphy1>; 348 phys = <&usbphy1>;
349 phy-names = "usb"; 349 phy-names = "usb";
350 status = "disabled"; 350 status = "disabled";
351 }; 351 };
352 352
353 ohci0: usb@a00400 { 353 ohci0: usb@a00400 {
354 compatible = "allwinne 354 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
355 reg = <0x00a00400 0x10 355 reg = <0x00a00400 0x100>;
356 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&usb_clocks 357 clocks = <&usb_clocks CLK_BUS_HCI0>,
358 <&usb_clocks 358 <&usb_clocks CLK_USB_OHCI0>;
359 resets = <&usb_clocks 359 resets = <&usb_clocks RST_USB0_HCI>;
360 phys = <&usbphy1>; 360 phys = <&usbphy1>;
361 phy-names = "usb"; 361 phy-names = "usb";
362 status = "disabled"; 362 status = "disabled";
363 }; 363 };
364 364
365 usbphy1: phy@a00800 { 365 usbphy1: phy@a00800 {
366 compatible = "allwinne 366 compatible = "allwinner,sun9i-a80-usb-phy";
367 reg = <0x00a00800 0x4> 367 reg = <0x00a00800 0x4>;
368 clocks = <&usb_clocks 368 clocks = <&usb_clocks CLK_USB0_PHY>;
369 clock-names = "phy"; 369 clock-names = "phy";
370 resets = <&usb_clocks 370 resets = <&usb_clocks RST_USB0_PHY>;
371 reset-names = "phy"; 371 reset-names = "phy";
372 status = "disabled"; 372 status = "disabled";
373 #phy-cells = <0>; 373 #phy-cells = <0>;
374 }; 374 };
375 375
376 ehci1: usb@a01000 { 376 ehci1: usb@a01000 {
377 compatible = "allwinne 377 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
378 reg = <0x00a01000 0x10 378 reg = <0x00a01000 0x100>;
379 interrupts = <GIC_SPI 379 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&usb_clocks 380 clocks = <&usb_clocks CLK_BUS_HCI1>;
381 resets = <&usb_clocks 381 resets = <&usb_clocks RST_USB1_HCI>;
382 phys = <&usbphy2>; 382 phys = <&usbphy2>;
383 phy-names = "usb"; 383 phy-names = "usb";
384 status = "disabled"; 384 status = "disabled";
385 }; 385 };
386 386
387 usbphy2: phy@a01800 { 387 usbphy2: phy@a01800 {
388 compatible = "allwinne 388 compatible = "allwinner,sun9i-a80-usb-phy";
389 reg = <0x00a01800 0x4> 389 reg = <0x00a01800 0x4>;
390 clocks = <&usb_clocks 390 clocks = <&usb_clocks CLK_USB1_PHY>,
391 <&usb_clocks 391 <&usb_clocks CLK_USB_HSIC>,
392 <&usb_clocks 392 <&usb_clocks CLK_USB1_HSIC>;
393 clock-names = "phy", 393 clock-names = "phy",
394 "hsic_12 394 "hsic_12M",
395 "hsic_48 395 "hsic_480M";
396 resets = <&usb_clocks 396 resets = <&usb_clocks RST_USB1_PHY>,
397 <&usb_clocks 397 <&usb_clocks RST_USB1_HSIC>;
398 reset-names = "phy", 398 reset-names = "phy",
399 "hsic"; 399 "hsic";
400 status = "disabled"; 400 status = "disabled";
401 #phy-cells = <0>; 401 #phy-cells = <0>;
402 /* usb1 is always used 402 /* usb1 is always used with HSIC */
403 phy_type = "hsic"; 403 phy_type = "hsic";
404 }; 404 };
405 405
406 ehci2: usb@a02000 { 406 ehci2: usb@a02000 {
407 compatible = "allwinne 407 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
408 reg = <0x00a02000 0x10 408 reg = <0x00a02000 0x100>;
409 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&usb_clocks 410 clocks = <&usb_clocks CLK_BUS_HCI2>;
411 resets = <&usb_clocks 411 resets = <&usb_clocks RST_USB2_HCI>;
412 phys = <&usbphy3>; 412 phys = <&usbphy3>;
413 phy-names = "usb"; 413 phy-names = "usb";
414 status = "disabled"; 414 status = "disabled";
415 }; 415 };
416 416
417 ohci2: usb@a02400 { 417 ohci2: usb@a02400 {
418 compatible = "allwinne 418 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
419 reg = <0x00a02400 0x10 419 reg = <0x00a02400 0x100>;
420 interrupts = <GIC_SPI 420 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&usb_clocks 421 clocks = <&usb_clocks CLK_BUS_HCI2>,
422 <&usb_clocks 422 <&usb_clocks CLK_USB_OHCI2>;
423 resets = <&usb_clocks 423 resets = <&usb_clocks RST_USB2_HCI>;
424 phys = <&usbphy3>; 424 phys = <&usbphy3>;
425 phy-names = "usb"; 425 phy-names = "usb";
426 status = "disabled"; 426 status = "disabled";
427 }; 427 };
428 428
429 usbphy3: phy@a02800 { 429 usbphy3: phy@a02800 {
430 compatible = "allwinne 430 compatible = "allwinner,sun9i-a80-usb-phy";
431 reg = <0x00a02800 0x4> 431 reg = <0x00a02800 0x4>;
432 clocks = <&usb_clocks 432 clocks = <&usb_clocks CLK_USB2_PHY>,
433 <&usb_clocks 433 <&usb_clocks CLK_USB_HSIC>,
434 <&usb_clocks 434 <&usb_clocks CLK_USB2_HSIC>;
435 clock-names = "phy", 435 clock-names = "phy",
436 "hsic_12 436 "hsic_12M",
437 "hsic_48 437 "hsic_480M";
438 resets = <&usb_clocks 438 resets = <&usb_clocks RST_USB2_PHY>,
439 <&usb_clocks 439 <&usb_clocks RST_USB2_HSIC>;
440 reset-names = "phy", 440 reset-names = "phy",
441 "hsic"; 441 "hsic";
442 status = "disabled"; 442 status = "disabled";
443 #phy-cells = <0>; 443 #phy-cells = <0>;
444 }; 444 };
445 445
446 usb_clocks: clock@a08000 { 446 usb_clocks: clock@a08000 {
447 compatible = "allwinne 447 compatible = "allwinner,sun9i-a80-usb-clks";
448 reg = <0x00a08000 0x8> 448 reg = <0x00a08000 0x8>;
449 clocks = <&ccu CLK_BUS 449 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
450 clock-names = "bus", " 450 clock-names = "bus", "hosc";
451 #clock-cells = <1>; 451 #clock-cells = <1>;
452 #reset-cells = <1>; 452 #reset-cells = <1>;
453 }; 453 };
454 454
455 cpucfg@1700000 { 455 cpucfg@1700000 {
456 compatible = "allwinne 456 compatible = "allwinner,sun9i-a80-cpucfg";
457 reg = <0x01700000 0x10 457 reg = <0x01700000 0x100>;
458 }; 458 };
459 459
460 crypto: crypto@1c02000 { 460 crypto: crypto@1c02000 {
461 compatible = "allwinne 461 compatible = "allwinner,sun9i-a80-crypto";
462 reg = <0x01c02000 0x10 462 reg = <0x01c02000 0x1000>;
463 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
464 resets = <&ccu RST_BUS 464 resets = <&ccu RST_BUS_SS>;
465 clocks = <&ccu CLK_BUS 465 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
466 clock-names = "bus", " 466 clock-names = "bus", "mod";
467 }; 467 };
468 468
469 mmc0: mmc@1c0f000 { 469 mmc0: mmc@1c0f000 {
470 compatible = "allwinne 470 compatible = "allwinner,sun9i-a80-mmc";
471 reg = <0x01c0f000 0x10 471 reg = <0x01c0f000 0x1000>;
472 clocks = <&mmc_config_ 472 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
473 <&ccu CLK_MMC 473 <&ccu CLK_MMC0_OUTPUT>,
474 <&ccu CLK_MMC 474 <&ccu CLK_MMC0_SAMPLE>;
475 clock-names = "ahb", " 475 clock-names = "ahb", "mmc", "output", "sample";
476 resets = <&mmc_config_ 476 resets = <&mmc_config_clk 0>;
477 reset-names = "ahb"; 477 reset-names = "ahb";
478 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
479 status = "disabled"; 479 status = "disabled";
480 #address-cells = <1>; 480 #address-cells = <1>;
481 #size-cells = <0>; 481 #size-cells = <0>;
482 }; 482 };
483 483
484 mmc1: mmc@1c10000 { 484 mmc1: mmc@1c10000 {
485 compatible = "allwinne 485 compatible = "allwinner,sun9i-a80-mmc";
486 reg = <0x01c10000 0x10 486 reg = <0x01c10000 0x1000>;
487 clocks = <&mmc_config_ 487 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
488 <&ccu CLK_MMC 488 <&ccu CLK_MMC1_OUTPUT>,
489 <&ccu CLK_MMC 489 <&ccu CLK_MMC1_SAMPLE>;
490 clock-names = "ahb", " 490 clock-names = "ahb", "mmc", "output", "sample";
491 resets = <&mmc_config_ 491 resets = <&mmc_config_clk 1>;
492 reset-names = "ahb"; 492 reset-names = "ahb";
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
494 status = "disabled"; 494 status = "disabled";
495 #address-cells = <1>; 495 #address-cells = <1>;
496 #size-cells = <0>; 496 #size-cells = <0>;
497 }; 497 };
498 498
499 mmc2: mmc@1c11000 { 499 mmc2: mmc@1c11000 {
500 compatible = "allwinne 500 compatible = "allwinner,sun9i-a80-mmc";
501 reg = <0x01c11000 0x10 501 reg = <0x01c11000 0x1000>;
502 clocks = <&mmc_config_ 502 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
503 <&ccu CLK_MMC 503 <&ccu CLK_MMC2_OUTPUT>,
504 <&ccu CLK_MMC 504 <&ccu CLK_MMC2_SAMPLE>;
505 clock-names = "ahb", " 505 clock-names = "ahb", "mmc", "output", "sample";
506 resets = <&mmc_config_ 506 resets = <&mmc_config_clk 2>;
507 reset-names = "ahb"; 507 reset-names = "ahb";
508 interrupts = <GIC_SPI 508 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
509 status = "disabled"; 509 status = "disabled";
510 #address-cells = <1>; 510 #address-cells = <1>;
511 #size-cells = <0>; 511 #size-cells = <0>;
512 }; 512 };
513 513
514 mmc3: mmc@1c12000 { 514 mmc3: mmc@1c12000 {
515 compatible = "allwinne 515 compatible = "allwinner,sun9i-a80-mmc";
516 reg = <0x01c12000 0x10 516 reg = <0x01c12000 0x1000>;
517 clocks = <&mmc_config_ 517 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
518 <&ccu CLK_MMC 518 <&ccu CLK_MMC3_OUTPUT>,
519 <&ccu CLK_MMC 519 <&ccu CLK_MMC3_SAMPLE>;
520 clock-names = "ahb", " 520 clock-names = "ahb", "mmc", "output", "sample";
521 resets = <&mmc_config_ 521 resets = <&mmc_config_clk 3>;
522 reset-names = "ahb"; 522 reset-names = "ahb";
523 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
524 status = "disabled"; 524 status = "disabled";
525 #address-cells = <1>; 525 #address-cells = <1>;
526 #size-cells = <0>; 526 #size-cells = <0>;
527 }; 527 };
528 528
529 mmc_config_clk: clk@1c13000 { 529 mmc_config_clk: clk@1c13000 {
530 compatible = "allwinne 530 compatible = "allwinner,sun9i-a80-mmc-config-clk";
531 reg = <0x01c13000 0x10 531 reg = <0x01c13000 0x10>;
532 clocks = <&ccu CLK_BUS 532 clocks = <&ccu CLK_BUS_MMC>;
533 resets = <&ccu RST_BUS 533 resets = <&ccu RST_BUS_MMC>;
534 #clock-cells = <1>; 534 #clock-cells = <1>;
535 #reset-cells = <1>; 535 #reset-cells = <1>;
536 clock-output-names = " 536 clock-output-names = "mmc0_config", "mmc1_config",
537 " 537 "mmc2_config", "mmc3_config";
538 }; 538 };
539 539
540 gic: interrupt-controller@1c41 540 gic: interrupt-controller@1c41000 {
541 compatible = "arm,gic- 541 compatible = "arm,gic-400";
542 reg = <0x01c41000 0x10 542 reg = <0x01c41000 0x1000>,
543 <0x01c42000 0x20 543 <0x01c42000 0x2000>,
544 <0x01c44000 0x20 544 <0x01c44000 0x2000>,
545 <0x01c46000 0x20 545 <0x01c46000 0x2000>;
546 interrupt-controller; 546 interrupt-controller;
547 #interrupt-cells = <3> 547 #interrupt-cells = <3>;
548 interrupts = <GIC_PPI 548 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
549 }; 549 };
550 550
551 cci: cci@1c90000 { 551 cci: cci@1c90000 {
552 compatible = "arm,cci- 552 compatible = "arm,cci-400";
553 #address-cells = <1>; 553 #address-cells = <1>;
554 #size-cells = <1>; 554 #size-cells = <1>;
555 reg = <0x01c90000 0x10 555 reg = <0x01c90000 0x1000>;
556 ranges = <0x0 0x01c900 556 ranges = <0x0 0x01c90000 0x10000>;
557 557
558 cci_control0: slave-if 558 cci_control0: slave-if@4000 {
559 compatible = " 559 compatible = "arm,cci-400-ctrl-if";
560 interface-type 560 interface-type = "ace";
561 reg = <0x4000 561 reg = <0x4000 0x1000>;
562 }; 562 };
563 563
564 cci_control1: slave-if 564 cci_control1: slave-if@5000 {
565 compatible = " 565 compatible = "arm,cci-400-ctrl-if";
566 interface-type 566 interface-type = "ace";
567 reg = <0x5000 567 reg = <0x5000 0x1000>;
568 }; 568 };
569 569
570 pmu@9000 { 570 pmu@9000 {
571 compatible = 571 compatible = "arm,cci-400-pmu,r1";
572 reg = <0x9000 572 reg = <0x9000 0x5000>;
573 interrupts = 573 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
574 574 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
575 575 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
576 576 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
577 577 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
578 }; 578 };
579 }; 579 };
580 580
581 de_clocks: clock@3000000 { 581 de_clocks: clock@3000000 {
582 compatible = "allwinne 582 compatible = "allwinner,sun9i-a80-de-clks";
583 reg = <0x03000000 0x30 583 reg = <0x03000000 0x30>;
584 clocks = <&ccu CLK_DE> 584 clocks = <&ccu CLK_DE>,
585 <&ccu CLK_SDR 585 <&ccu CLK_SDRAM>,
586 <&ccu CLK_BUS 586 <&ccu CLK_BUS_DE>;
587 clock-names = "mod", 587 clock-names = "mod",
588 "dram", 588 "dram",
589 "bus"; 589 "bus";
590 resets = <&ccu RST_BUS 590 resets = <&ccu RST_BUS_DE>;
591 #clock-cells = <1>; 591 #clock-cells = <1>;
592 #reset-cells = <1>; 592 #reset-cells = <1>;
593 }; 593 };
594 594
595 fe0: display-frontend@3100000 595 fe0: display-frontend@3100000 {
596 compatible = "allwinne 596 compatible = "allwinner,sun9i-a80-display-frontend";
597 reg = <0x03100000 0x40 597 reg = <0x03100000 0x40000>;
598 interrupts = <GIC_SPI 598 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&de_clocks C 599 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
600 <&de_clocks C 600 <&de_clocks CLK_DRAM_FE0>;
601 clock-names = "ahb", " 601 clock-names = "ahb", "mod",
602 "ram"; 602 "ram";
603 resets = <&de_clocks R 603 resets = <&de_clocks RST_FE0>;
604 604
605 ports { 605 ports {
606 #address-cells 606 #address-cells = <1>;
607 #size-cells = 607 #size-cells = <0>;
608 608
609 fe0_out: port@ 609 fe0_out: port@1 {
610 reg = 610 reg = <1>;
611 611
612 fe0_ou 612 fe0_out_deu0: endpoint {
613 613 remote-endpoint = <&deu0_in_fe0>;
614 }; 614 };
615 }; 615 };
616 }; 616 };
617 }; 617 };
618 618
619 fe1: display-frontend@3140000 619 fe1: display-frontend@3140000 {
620 compatible = "allwinne 620 compatible = "allwinner,sun9i-a80-display-frontend";
621 reg = <0x03140000 0x40 621 reg = <0x03140000 0x40000>;
622 interrupts = <GIC_SPI 622 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&de_clocks C 623 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
624 <&de_clocks C 624 <&de_clocks CLK_DRAM_FE1>;
625 clock-names = "ahb", " 625 clock-names = "ahb", "mod",
626 "ram"; 626 "ram";
627 resets = <&de_clocks R 627 resets = <&de_clocks RST_FE0>;
628 628
629 ports { 629 ports {
630 #address-cells 630 #address-cells = <1>;
631 #size-cells = 631 #size-cells = <0>;
632 632
633 fe1_out: port@ 633 fe1_out: port@1 {
634 reg = 634 reg = <1>;
635 635
636 fe1_ou 636 fe1_out_deu1: endpoint {
637 637 remote-endpoint = <&deu1_in_fe1>;
638 }; 638 };
639 }; 639 };
640 }; 640 };
641 }; 641 };
642 642
643 be0: display-backend@3200000 { 643 be0: display-backend@3200000 {
644 compatible = "allwinne 644 compatible = "allwinner,sun9i-a80-display-backend";
645 reg = <0x03200000 0x40 645 reg = <0x03200000 0x40000>;
646 interrupts = <GIC_SPI 646 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&de_clocks C 647 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
648 <&de_clocks C 648 <&de_clocks CLK_DRAM_BE0>;
649 clock-names = "ahb", " 649 clock-names = "ahb", "mod",
650 "ram"; 650 "ram";
651 resets = <&de_clocks R 651 resets = <&de_clocks RST_BE0>;
652 652
653 ports { 653 ports {
654 #address-cells 654 #address-cells = <1>;
655 #size-cells = 655 #size-cells = <0>;
656 656
657 be0_in: port@0 657 be0_in: port@0 {
658 #addre 658 #address-cells = <1>;
659 #size- 659 #size-cells = <0>;
660 reg = 660 reg = <0>;
661 661
662 be0_in 662 be0_in_deu0: endpoint@0 {
663 663 reg = <0>;
664 664 remote-endpoint = <&deu0_out_be0>;
665 }; 665 };
666 666
667 be0_in 667 be0_in_deu1: endpoint@1 {
668 668 reg = <1>;
669 669 remote-endpoint = <&deu1_out_be0>;
670 }; 670 };
671 }; 671 };
672 672
673 be0_out: port@ 673 be0_out: port@1 {
674 reg = 674 reg = <1>;
675 675
676 be0_ou 676 be0_out_drc0: endpoint {
677 677 remote-endpoint = <&drc0_in_be0>;
678 }; 678 };
679 }; 679 };
680 }; 680 };
681 }; 681 };
682 682
683 be1: display-backend@3240000 { 683 be1: display-backend@3240000 {
684 compatible = "allwinne 684 compatible = "allwinner,sun9i-a80-display-backend";
685 reg = <0x03240000 0x40 685 reg = <0x03240000 0x40000>;
686 interrupts = <GIC_SPI 686 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&de_clocks C 687 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
688 <&de_clocks C 688 <&de_clocks CLK_DRAM_BE1>;
689 clock-names = "ahb", " 689 clock-names = "ahb", "mod",
690 "ram"; 690 "ram";
691 resets = <&de_clocks R 691 resets = <&de_clocks RST_BE1>;
692 692
693 ports { 693 ports {
694 #address-cells 694 #address-cells = <1>;
695 #size-cells = 695 #size-cells = <0>;
696 696
697 be1_in: port@0 697 be1_in: port@0 {
698 #addre 698 #address-cells = <1>;
699 #size- 699 #size-cells = <0>;
700 reg = 700 reg = <0>;
701 701
702 be1_in 702 be1_in_deu0: endpoint@0 {
703 703 reg = <0>;
704 704 remote-endpoint = <&deu0_out_be1>;
705 }; 705 };
706 706
707 be1_in 707 be1_in_deu1: endpoint@1 {
708 708 reg = <1>;
709 709 remote-endpoint = <&deu1_out_be1>;
710 }; 710 };
711 }; 711 };
712 712
713 be1_out: port@ 713 be1_out: port@1 {
714 reg = 714 reg = <1>;
715 715
716 be1_ou 716 be1_out_drc1: endpoint {
717 717 remote-endpoint = <&drc1_in_be1>;
718 }; 718 };
719 }; 719 };
720 }; 720 };
721 }; 721 };
722 722
723 deu0: deu@3300000 { 723 deu0: deu@3300000 {
724 compatible = "allwinne 724 compatible = "allwinner,sun9i-a80-deu";
725 reg = <0x03300000 0x40 725 reg = <0x03300000 0x40000>;
726 interrupts = <GIC_SPI 726 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&de_clocks C 727 clocks = <&de_clocks CLK_BUS_DEU0>,
728 <&de_clocks C 728 <&de_clocks CLK_IEP_DEU0>,
729 <&de_clocks C 729 <&de_clocks CLK_DRAM_DEU0>;
730 clock-names = "ahb", 730 clock-names = "ahb",
731 "mod", 731 "mod",
732 "ram"; 732 "ram";
733 resets = <&de_clocks R 733 resets = <&de_clocks RST_DEU0>;
734 734
735 ports { 735 ports {
736 #address-cells 736 #address-cells = <1>;
737 #size-cells = 737 #size-cells = <0>;
738 738
739 deu0_in: port@ 739 deu0_in: port@0 {
740 reg = 740 reg = <0>;
741 741
742 deu0_i 742 deu0_in_fe0: endpoint {
743 743 remote-endpoint = <&fe0_out_deu0>;
744 }; 744 };
745 }; 745 };
746 746
747 deu0_out: port 747 deu0_out: port@1 {
748 #addre 748 #address-cells = <1>;
749 #size- 749 #size-cells = <0>;
750 reg = 750 reg = <1>;
751 751
752 deu0_o 752 deu0_out_be0: endpoint@0 {
753 753 reg = <0>;
754 754 remote-endpoint = <&be0_in_deu0>;
755 }; 755 };
756 756
757 deu0_o 757 deu0_out_be1: endpoint@1 {
758 758 reg = <1>;
759 759 remote-endpoint = <&be1_in_deu0>;
760 }; 760 };
761 }; 761 };
762 }; 762 };
763 }; 763 };
764 764
765 deu1: deu@3340000 { 765 deu1: deu@3340000 {
766 compatible = "allwinne 766 compatible = "allwinner,sun9i-a80-deu";
767 reg = <0x03340000 0x40 767 reg = <0x03340000 0x40000>;
768 interrupts = <GIC_SPI 768 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&de_clocks C 769 clocks = <&de_clocks CLK_BUS_DEU1>,
770 <&de_clocks C 770 <&de_clocks CLK_IEP_DEU1>,
771 <&de_clocks C 771 <&de_clocks CLK_DRAM_DEU1>;
772 clock-names = "ahb", 772 clock-names = "ahb",
773 "mod", 773 "mod",
774 "ram"; 774 "ram";
775 resets = <&de_clocks R 775 resets = <&de_clocks RST_DEU1>;
776 776
777 ports { 777 ports {
778 #address-cells 778 #address-cells = <1>;
779 #size-cells = 779 #size-cells = <0>;
780 780
781 deu1_in: port@ 781 deu1_in: port@0 {
782 reg = 782 reg = <0>;
783 783
784 deu1_i 784 deu1_in_fe1: endpoint {
785 785 remote-endpoint = <&fe1_out_deu1>;
786 }; 786 };
787 }; 787 };
788 788
789 deu1_out: port 789 deu1_out: port@1 {
790 #addre 790 #address-cells = <1>;
791 #size- 791 #size-cells = <0>;
792 reg = 792 reg = <1>;
793 793
794 deu1_o 794 deu1_out_be0: endpoint@0 {
795 795 reg = <0>;
796 796 remote-endpoint = <&be0_in_deu1>;
797 }; 797 };
798 798
799 deu1_o 799 deu1_out_be1: endpoint@1 {
800 800 reg = <1>;
801 801 remote-endpoint = <&be1_in_deu1>;
802 }; 802 };
803 }; 803 };
804 }; 804 };
805 }; 805 };
806 806
807 drc0: drc@3400000 { 807 drc0: drc@3400000 {
808 compatible = "allwinne 808 compatible = "allwinner,sun9i-a80-drc";
809 reg = <0x03400000 0x40 809 reg = <0x03400000 0x40000>;
810 interrupts = <GIC_SPI 810 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&de_clocks C 811 clocks = <&de_clocks CLK_BUS_DRC0>,
812 <&de_clocks C 812 <&de_clocks CLK_IEP_DRC0>,
813 <&de_clocks C 813 <&de_clocks CLK_DRAM_DRC0>;
814 clock-names = "ahb", 814 clock-names = "ahb",
815 "mod", 815 "mod",
816 "ram"; 816 "ram";
817 resets = <&de_clocks R 817 resets = <&de_clocks RST_DRC0>;
818 818
819 ports { 819 ports {
820 #address-cells 820 #address-cells = <1>;
821 #size-cells = 821 #size-cells = <0>;
822 822
823 drc0_in: port@ 823 drc0_in: port@0 {
824 reg = 824 reg = <0>;
825 825
826 drc0_i 826 drc0_in_be0: endpoint {
827 827 remote-endpoint = <&be0_out_drc0>;
828 }; 828 };
829 }; 829 };
830 830
831 drc0_out: port 831 drc0_out: port@1 {
832 reg = 832 reg = <1>;
833 833
834 drc0_o 834 drc0_out_tcon0: endpoint {
835 835 remote-endpoint = <&tcon0_in_drc0>;
836 }; 836 };
837 }; 837 };
838 }; 838 };
839 }; 839 };
840 840
841 drc1: drc@3440000 { 841 drc1: drc@3440000 {
842 compatible = "allwinne 842 compatible = "allwinner,sun9i-a80-drc";
843 reg = <0x03440000 0x40 843 reg = <0x03440000 0x40000>;
844 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&de_clocks C 845 clocks = <&de_clocks CLK_BUS_DRC1>,
846 <&de_clocks C 846 <&de_clocks CLK_IEP_DRC1>,
847 <&de_clocks C 847 <&de_clocks CLK_DRAM_DRC1>;
848 clock-names = "ahb", 848 clock-names = "ahb",
849 "mod", 849 "mod",
850 "ram"; 850 "ram";
851 resets = <&de_clocks R 851 resets = <&de_clocks RST_DRC1>;
852 852
853 ports { 853 ports {
854 #address-cells 854 #address-cells = <1>;
855 #size-cells = 855 #size-cells = <0>;
856 856
857 drc1_in: port@ 857 drc1_in: port@0 {
858 reg = 858 reg = <0>;
859 859
860 drc1_i 860 drc1_in_be1: endpoint {
861 861 remote-endpoint = <&be1_out_drc1>;
862 }; 862 };
863 }; 863 };
864 864
865 drc1_out: port 865 drc1_out: port@1 {
866 reg = 866 reg = <1>;
867 867
868 drc1_o 868 drc1_out_tcon1: endpoint {
869 869 remote-endpoint = <&tcon1_in_drc1>;
870 }; 870 };
871 }; 871 };
872 }; 872 };
873 }; 873 };
874 874
875 tcon0: lcd-controller@3c00000 875 tcon0: lcd-controller@3c00000 {
876 compatible = "allwinne 876 compatible = "allwinner,sun9i-a80-tcon-lcd";
877 reg = <0x03c00000 0x10 877 reg = <0x03c00000 0x10000>;
878 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&ccu CLK_BUS 879 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
880 clock-names = "ahb", " 880 clock-names = "ahb", "tcon-ch0";
881 resets = <&ccu RST_BUS 881 resets = <&ccu RST_BUS_LCD0>,
882 <&ccu RST_BUS 882 <&ccu RST_BUS_EDP>,
883 <&ccu RST_BUS 883 <&ccu RST_BUS_LVDS>;
884 reset-names = "lcd", 884 reset-names = "lcd",
885 "edp", 885 "edp",
886 "lvds"; 886 "lvds";
887 clock-output-names = " 887 clock-output-names = "tcon0-pixel-clock";
888 #clock-cells = <0>; 888 #clock-cells = <0>;
889 889
890 ports { 890 ports {
891 #address-cells 891 #address-cells = <1>;
892 #size-cells = 892 #size-cells = <0>;
893 893
894 tcon0_in: port 894 tcon0_in: port@0 {
895 reg = 895 reg = <0>;
896 896
897 tcon0_ 897 tcon0_in_drc0: endpoint {
898 898 remote-endpoint = <&drc0_out_tcon0>;
899 }; 899 };
900 }; 900 };
901 901
902 tcon0_out: por 902 tcon0_out: port@1 {
903 reg = 903 reg = <1>;
904 }; 904 };
905 }; 905 };
906 }; 906 };
907 907
908 tcon1: lcd-controller@3c10000 908 tcon1: lcd-controller@3c10000 {
909 compatible = "allwinne 909 compatible = "allwinner,sun9i-a80-tcon-tv";
910 reg = <0x03c10000 0x10 910 reg = <0x03c10000 0x10000>;
911 interrupts = <GIC_SPI 911 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&ccu CLK_BUS 912 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
913 clock-names = "ahb", " 913 clock-names = "ahb", "tcon-ch1";
914 resets = <&ccu RST_BUS 914 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
915 reset-names = "lcd", " 915 reset-names = "lcd", "edp";
916 916
917 ports { 917 ports {
918 #address-cells 918 #address-cells = <1>;
919 #size-cells = 919 #size-cells = <0>;
920 920
921 tcon1_in: port 921 tcon1_in: port@0 {
922 reg = 922 reg = <0>;
923 923
924 tcon1_ 924 tcon1_in_drc1: endpoint {
925 925 remote-endpoint = <&drc1_out_tcon1>;
926 }; 926 };
927 }; 927 };
928 928
929 tcon1_out: por 929 tcon1_out: port@1 {
930 reg = 930 reg = <1>;
931 }; 931 };
932 }; 932 };
933 }; 933 };
934 934
935 ccu: clock@6000000 { 935 ccu: clock@6000000 {
936 compatible = "allwinne 936 compatible = "allwinner,sun9i-a80-ccu";
937 reg = <0x06000000 0x80 937 reg = <0x06000000 0x800>;
938 clocks = <&osc24M>, <& 938 clocks = <&osc24M>, <&osc32k>;
939 clock-names = "hosc", 939 clock-names = "hosc", "losc";
940 #clock-cells = <1>; 940 #clock-cells = <1>;
941 #reset-cells = <1>; 941 #reset-cells = <1>;
942 }; 942 };
943 943
944 timer@6000c00 { 944 timer@6000c00 {
945 compatible = "allwinne 945 compatible = "allwinner,sun4i-a10-timer";
946 reg = <0x06000c00 0xa0 946 reg = <0x06000c00 0xa0>;
947 interrupts = <GIC_SPI 947 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 948 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 949 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 950 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 951 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 952 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
953 953
954 clocks = <&osc24M>; 954 clocks = <&osc24M>;
955 }; 955 };
956 956
957 wdt: watchdog@6000ca0 { 957 wdt: watchdog@6000ca0 {
958 compatible = "allwinne 958 compatible = "allwinner,sun6i-a31-wdt";
959 reg = <0x06000ca0 0x20 959 reg = <0x06000ca0 0x20>;
960 interrupts = <GIC_SPI 960 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&osc24M>; 961 clocks = <&osc24M>;
962 }; 962 };
963 963
964 pio: pinctrl@6000800 { 964 pio: pinctrl@6000800 {
965 compatible = "allwinne 965 compatible = "allwinner,sun9i-a80-pinctrl";
966 reg = <0x06000800 0x40 966 reg = <0x06000800 0x400>;
967 interrupts = <GIC_SPI 967 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 968 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 969 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 970 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&ccu CLK_BUS 972 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
973 clock-names = "apb", " 973 clock-names = "apb", "hosc", "losc";
974 gpio-controller; 974 gpio-controller;
975 interrupt-controller; 975 interrupt-controller;
976 #interrupt-cells = <3> 976 #interrupt-cells = <3>;
977 #gpio-cells = <3>; 977 #gpio-cells = <3>;
978 978
979 gmac_rgmii_pins: gmac- 979 gmac_rgmii_pins: gmac-rgmii-pins {
980 pins = "PA0", 980 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
981 "PA7", 981 "PA7", "PA8", "PA9", "PA10", "PA12",
982 "PA13", 982 "PA13", "PA15", "PA16", "PA17";
983 function = "gm 983 function = "gmac";
984 /* 984 /*
985 * data lines 985 * data lines in RGMII mode use DDR mode
986 * and need a 986 * and need a higher signal drive strength
987 */ 987 */
988 drive-strength 988 drive-strength = <40>;
989 }; 989 };
990 990
991 i2c3_pins: i2c3-pins { 991 i2c3_pins: i2c3-pins {
992 pins = "PG10", 992 pins = "PG10", "PG11";
993 function = "i2 993 function = "i2c3";
994 }; 994 };
995 995
996 lcd0_rgb888_pins: lcd0 996 lcd0_rgb888_pins: lcd0-rgb888-pins {
997 pins = "PD0", 997 pins = "PD0", "PD1", "PD2", "PD3",
998 "PD4", 998 "PD4", "PD5", "PD6", "PD7",
999 "PD8", 999 "PD8", "PD9", "PD10", "PD11",
1000 "PD12" 1000 "PD12", "PD13", "PD14", "PD15",
1001 "PD16" 1001 "PD16", "PD17", "PD18", "PD19",
1002 "PD20" 1002 "PD20", "PD21", "PD22", "PD23",
1003 "PD24" 1003 "PD24", "PD25", "PD26", "PD27";
1004 function = "l 1004 function = "lcd0";
1005 }; 1005 };
1006 1006
1007 mmc0_pins: mmc0-pins 1007 mmc0_pins: mmc0-pins {
1008 pins = "PF0", 1008 pins = "PF0", "PF1" ,"PF2", "PF3",
1009 "PF4", 1009 "PF4", "PF5";
1010 function = "m 1010 function = "mmc0";
1011 drive-strengt 1011 drive-strength = <30>;
1012 bias-pull-up; 1012 bias-pull-up;
1013 }; 1013 };
1014 1014
1015 mmc1_pins: mmc1-pins 1015 mmc1_pins: mmc1-pins {
1016 pins = "PG0", 1016 pins = "PG0", "PG1" ,"PG2", "PG3",
1017 1017 "PG4", "PG5";
1018 function = "m 1018 function = "mmc1";
1019 drive-strengt 1019 drive-strength = <30>;
1020 bias-pull-up; 1020 bias-pull-up;
1021 }; 1021 };
1022 1022
1023 mmc2_8bit_pins: mmc2- 1023 mmc2_8bit_pins: mmc2-8bit-pins {
1024 pins = "PC6", 1024 pins = "PC6", "PC7", "PC8", "PC9",
1025 "PC10" 1025 "PC10", "PC11", "PC12",
1026 "PC13" 1026 "PC13", "PC14", "PC15",
1027 "PC16" 1027 "PC16";
1028 function = "m 1028 function = "mmc2";
1029 drive-strengt 1029 drive-strength = <30>;
1030 bias-pull-up; 1030 bias-pull-up;
1031 }; 1031 };
1032 1032
1033 uart0_ph_pins: uart0- 1033 uart0_ph_pins: uart0-ph-pins {
1034 pins = "PH12" 1034 pins = "PH12", "PH13";
1035 function = "u 1035 function = "uart0";
1036 }; 1036 };
1037 1037
1038 uart4_pins: uart4-pin 1038 uart4_pins: uart4-pins {
1039 pins = "PG12" 1039 pins = "PG12", "PG13", "PG14", "PG15";
1040 function = "u 1040 function = "uart4";
1041 }; 1041 };
1042 }; 1042 };
1043 1043
1044 uart0: serial@7000000 { 1044 uart0: serial@7000000 {
1045 compatible = "snps,dw 1045 compatible = "snps,dw-apb-uart";
1046 reg = <0x07000000 0x4 1046 reg = <0x07000000 0x400>;
1047 interrupts = <GIC_SPI 1047 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1048 reg-shift = <2>; 1048 reg-shift = <2>;
1049 reg-io-width = <4>; 1049 reg-io-width = <4>;
1050 clocks = <&ccu CLK_BU 1050 clocks = <&ccu CLK_BUS_UART0>;
1051 resets = <&ccu RST_BU 1051 resets = <&ccu RST_BUS_UART0>;
1052 status = "disabled"; 1052 status = "disabled";
1053 }; 1053 };
1054 1054
1055 uart1: serial@7000400 { 1055 uart1: serial@7000400 {
1056 compatible = "snps,dw 1056 compatible = "snps,dw-apb-uart";
1057 reg = <0x07000400 0x4 1057 reg = <0x07000400 0x400>;
1058 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1059 reg-shift = <2>; 1059 reg-shift = <2>;
1060 reg-io-width = <4>; 1060 reg-io-width = <4>;
1061 clocks = <&ccu CLK_BU 1061 clocks = <&ccu CLK_BUS_UART1>;
1062 resets = <&ccu RST_BU 1062 resets = <&ccu RST_BUS_UART1>;
1063 status = "disabled"; 1063 status = "disabled";
1064 }; 1064 };
1065 1065
1066 uart2: serial@7000800 { 1066 uart2: serial@7000800 {
1067 compatible = "snps,dw 1067 compatible = "snps,dw-apb-uart";
1068 reg = <0x07000800 0x4 1068 reg = <0x07000800 0x400>;
1069 interrupts = <GIC_SPI 1069 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1070 reg-shift = <2>; 1070 reg-shift = <2>;
1071 reg-io-width = <4>; 1071 reg-io-width = <4>;
1072 clocks = <&ccu CLK_BU 1072 clocks = <&ccu CLK_BUS_UART2>;
1073 resets = <&ccu RST_BU 1073 resets = <&ccu RST_BUS_UART2>;
1074 status = "disabled"; 1074 status = "disabled";
1075 }; 1075 };
1076 1076
1077 uart3: serial@7000c00 { 1077 uart3: serial@7000c00 {
1078 compatible = "snps,dw 1078 compatible = "snps,dw-apb-uart";
1079 reg = <0x07000c00 0x4 1079 reg = <0x07000c00 0x400>;
1080 interrupts = <GIC_SPI 1080 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1081 reg-shift = <2>; 1081 reg-shift = <2>;
1082 reg-io-width = <4>; 1082 reg-io-width = <4>;
1083 clocks = <&ccu CLK_BU 1083 clocks = <&ccu CLK_BUS_UART3>;
1084 resets = <&ccu RST_BU 1084 resets = <&ccu RST_BUS_UART3>;
1085 status = "disabled"; 1085 status = "disabled";
1086 }; 1086 };
1087 1087
1088 uart4: serial@7001000 { 1088 uart4: serial@7001000 {
1089 compatible = "snps,dw 1089 compatible = "snps,dw-apb-uart";
1090 reg = <0x07001000 0x4 1090 reg = <0x07001000 0x400>;
1091 interrupts = <GIC_SPI 1091 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1092 reg-shift = <2>; 1092 reg-shift = <2>;
1093 reg-io-width = <4>; 1093 reg-io-width = <4>;
1094 clocks = <&ccu CLK_BU 1094 clocks = <&ccu CLK_BUS_UART4>;
1095 resets = <&ccu RST_BU 1095 resets = <&ccu RST_BUS_UART4>;
1096 status = "disabled"; 1096 status = "disabled";
1097 }; 1097 };
1098 1098
1099 uart5: serial@7001400 { 1099 uart5: serial@7001400 {
1100 compatible = "snps,dw 1100 compatible = "snps,dw-apb-uart";
1101 reg = <0x07001400 0x4 1101 reg = <0x07001400 0x400>;
1102 interrupts = <GIC_SPI 1102 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1103 reg-shift = <2>; 1103 reg-shift = <2>;
1104 reg-io-width = <4>; 1104 reg-io-width = <4>;
1105 clocks = <&ccu CLK_BU 1105 clocks = <&ccu CLK_BUS_UART5>;
1106 resets = <&ccu RST_BU 1106 resets = <&ccu RST_BUS_UART5>;
1107 status = "disabled"; 1107 status = "disabled";
1108 }; 1108 };
1109 1109
1110 i2c0: i2c@7002800 { 1110 i2c0: i2c@7002800 {
1111 compatible = "allwinn 1111 compatible = "allwinner,sun6i-a31-i2c";
1112 reg = <0x07002800 0x4 1112 reg = <0x07002800 0x400>;
1113 interrupts = <GIC_SPI 1113 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&ccu CLK_BU 1114 clocks = <&ccu CLK_BUS_I2C0>;
1115 resets = <&ccu RST_BU 1115 resets = <&ccu RST_BUS_I2C0>;
1116 status = "disabled"; 1116 status = "disabled";
1117 #address-cells = <1>; 1117 #address-cells = <1>;
1118 #size-cells = <0>; 1118 #size-cells = <0>;
1119 }; 1119 };
1120 1120
1121 i2c1: i2c@7002c00 { 1121 i2c1: i2c@7002c00 {
1122 compatible = "allwinn 1122 compatible = "allwinner,sun6i-a31-i2c";
1123 reg = <0x07002c00 0x4 1123 reg = <0x07002c00 0x400>;
1124 interrupts = <GIC_SPI 1124 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&ccu CLK_BU 1125 clocks = <&ccu CLK_BUS_I2C1>;
1126 resets = <&ccu RST_BU 1126 resets = <&ccu RST_BUS_I2C1>;
1127 status = "disabled"; 1127 status = "disabled";
1128 #address-cells = <1>; 1128 #address-cells = <1>;
1129 #size-cells = <0>; 1129 #size-cells = <0>;
1130 }; 1130 };
1131 1131
1132 i2c2: i2c@7003000 { 1132 i2c2: i2c@7003000 {
1133 compatible = "allwinn 1133 compatible = "allwinner,sun6i-a31-i2c";
1134 reg = <0x07003000 0x4 1134 reg = <0x07003000 0x400>;
1135 interrupts = <GIC_SPI 1135 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&ccu CLK_BU 1136 clocks = <&ccu CLK_BUS_I2C2>;
1137 resets = <&ccu RST_BU 1137 resets = <&ccu RST_BUS_I2C2>;
1138 status = "disabled"; 1138 status = "disabled";
1139 #address-cells = <1>; 1139 #address-cells = <1>;
1140 #size-cells = <0>; 1140 #size-cells = <0>;
1141 }; 1141 };
1142 1142
1143 i2c3: i2c@7003400 { 1143 i2c3: i2c@7003400 {
1144 compatible = "allwinn 1144 compatible = "allwinner,sun6i-a31-i2c";
1145 reg = <0x07003400 0x4 1145 reg = <0x07003400 0x400>;
1146 interrupts = <GIC_SPI 1146 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&ccu CLK_BU 1147 clocks = <&ccu CLK_BUS_I2C3>;
1148 resets = <&ccu RST_BU 1148 resets = <&ccu RST_BUS_I2C3>;
1149 status = "disabled"; 1149 status = "disabled";
1150 #address-cells = <1>; 1150 #address-cells = <1>;
1151 #size-cells = <0>; 1151 #size-cells = <0>;
1152 }; 1152 };
1153 1153
1154 i2c4: i2c@7003800 { 1154 i2c4: i2c@7003800 {
1155 compatible = "allwinn 1155 compatible = "allwinner,sun6i-a31-i2c";
1156 reg = <0x07003800 0x4 1156 reg = <0x07003800 0x400>;
1157 interrupts = <GIC_SPI 1157 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&ccu CLK_BU 1158 clocks = <&ccu CLK_BUS_I2C4>;
1159 resets = <&ccu RST_BU 1159 resets = <&ccu RST_BUS_I2C4>;
1160 status = "disabled"; 1160 status = "disabled";
1161 #address-cells = <1>; 1161 #address-cells = <1>;
1162 #size-cells = <0>; 1162 #size-cells = <0>;
1163 }; 1163 };
1164 1164
1165 r_wdt: watchdog@8001000 { 1165 r_wdt: watchdog@8001000 {
1166 compatible = "allwinn 1166 compatible = "allwinner,sun6i-a31-wdt";
1167 reg = <0x08001000 0x2 1167 reg = <0x08001000 0x20>;
1168 interrupts = <GIC_SPI 1168 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&osc24M>; 1169 clocks = <&osc24M>;
1170 }; 1170 };
1171 1171
1172 prcm@8001400 { 1172 prcm@8001400 {
1173 compatible = "allwinn 1173 compatible = "allwinner,sun9i-a80-prcm";
1174 reg = <0x08001400 0x2 1174 reg = <0x08001400 0x200>;
1175 }; 1175 };
1176 1176
1177 apbs_rst: reset@80014b0 { 1177 apbs_rst: reset@80014b0 {
1178 reg = <0x080014b0 0x4 1178 reg = <0x080014b0 0x4>;
1179 compatible = "allwinn 1179 compatible = "allwinner,sun6i-a31-clock-reset";
1180 #reset-cells = <1>; 1180 #reset-cells = <1>;
1181 }; 1181 };
1182 1182
1183 nmi_intc: interrupt-controlle 1183 nmi_intc: interrupt-controller@80015a0 {
1184 compatible = "allwinn 1184 compatible = "allwinner,sun9i-a80-nmi";
1185 interrupt-controller; 1185 interrupt-controller;
1186 #interrupt-cells = <2 1186 #interrupt-cells = <2>;
1187 reg = <0x080015a0 0xc 1187 reg = <0x080015a0 0xc>;
1188 interrupts = <GIC_SPI 1188 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1189 }; 1189 };
1190 1190
1191 r_ir: ir@8002000 { 1191 r_ir: ir@8002000 {
1192 compatible = "allwinn 1192 compatible = "allwinner,sun6i-a31-ir";
1193 interrupts = <GIC_SPI 1193 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1194 pinctrl-names = "defa 1194 pinctrl-names = "default";
1195 pinctrl-0 = <&r_ir_pi 1195 pinctrl-0 = <&r_ir_pins>;
1196 clocks = <&apbs_gates 1196 clocks = <&apbs_gates 1>, <&r_ir_clk>;
1197 clock-names = "apb", 1197 clock-names = "apb", "ir";
1198 resets = <&apbs_rst 1 1198 resets = <&apbs_rst 1>;
1199 reg = <0x08002000 0x4 1199 reg = <0x08002000 0x40>;
1200 status = "disabled"; 1200 status = "disabled";
1201 }; 1201 };
1202 1202
1203 r_uart: serial@8002800 { 1203 r_uart: serial@8002800 {
1204 compatible = "snps,dw 1204 compatible = "snps,dw-apb-uart";
1205 reg = <0x08002800 0x4 1205 reg = <0x08002800 0x400>;
1206 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1207 reg-shift = <2>; 1207 reg-shift = <2>;
1208 reg-io-width = <4>; 1208 reg-io-width = <4>;
1209 clocks = <&apbs_gates 1209 clocks = <&apbs_gates 4>;
1210 resets = <&apbs_rst 4 1210 resets = <&apbs_rst 4>;
1211 status = "disabled"; 1211 status = "disabled";
1212 }; 1212 };
1213 1213
1214 r_pio: pinctrl@8002c00 { 1214 r_pio: pinctrl@8002c00 {
1215 compatible = "allwinn 1215 compatible = "allwinner,sun9i-a80-r-pinctrl";
1216 reg = <0x08002c00 0x4 1216 reg = <0x08002c00 0x400>;
1217 interrupts = <GIC_SPI 1217 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 1218 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&apbs_gates 1219 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1220 clock-names = "apb", 1220 clock-names = "apb", "hosc", "losc";
1221 gpio-controller; 1221 gpio-controller;
1222 interrupt-controller; 1222 interrupt-controller;
1223 #interrupt-cells = <3 1223 #interrupt-cells = <3>;
1224 #gpio-cells = <3>; 1224 #gpio-cells = <3>;
1225 1225
1226 r_ir_pins: r-ir-pins 1226 r_ir_pins: r-ir-pins {
1227 pins = "PL6"; 1227 pins = "PL6";
1228 function = "s 1228 function = "s_cir_rx";
1229 }; 1229 };
1230 1230
1231 r_rsb_pins: r-rsb-pin 1231 r_rsb_pins: r-rsb-pins {
1232 pins = "PN0", 1232 pins = "PN0", "PN1";
1233 function = "s 1233 function = "s_rsb";
1234 drive-strengt 1234 drive-strength = <20>;
1235 bias-pull-up; 1235 bias-pull-up;
1236 }; 1236 };
1237 }; 1237 };
1238 1238
1239 r_rsb: rsb@8003400 { 1239 r_rsb: rsb@8003400 {
1240 compatible = "allwinn 1240 compatible = "allwinner,sun8i-a23-rsb";
1241 reg = <0x08003400 0x4 1241 reg = <0x08003400 0x400>;
1242 interrupts = <GIC_SPI 1242 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&apbs_gates 1243 clocks = <&apbs_gates 3>;
1244 clock-frequency = <30 1244 clock-frequency = <3000000>;
1245 resets = <&apbs_rst 3 1245 resets = <&apbs_rst 3>;
1246 pinctrl-names = "defa 1246 pinctrl-names = "default";
1247 pinctrl-0 = <&r_rsb_p 1247 pinctrl-0 = <&r_rsb_pins>;
1248 status = "disabled"; 1248 status = "disabled";
1249 #address-cells = <1>; 1249 #address-cells = <1>;
1250 #size-cells = <0>; 1250 #size-cells = <0>;
1251 }; 1251 };
1252 }; 1252 };
1253 }; 1253 };
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