1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.o 3 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
4 */ 4 */
5 5
6 #include "sunxi-bananapi-m2-plus.dtsi" 6 #include "sunxi-bananapi-m2-plus.dtsi"
7 7
8 / { 8 / {
9 /* 9 /*
10 * Bananapi M2+ v1.2 uses a GPIO line 10 * Bananapi M2+ v1.2 uses a GPIO line to change the effective
11 * resistance on the CPU regulator's f 11 * resistance on the CPU regulator's feedback pin.
12 */ 12 */
13 reg_vdd_cpux: vdd-cpux { 13 reg_vdd_cpux: vdd-cpux {
14 compatible = "regulator-gpio"; 14 compatible = "regulator-gpio";
15 regulator-name = "vdd-cpux"; 15 regulator-name = "vdd-cpux";
16 regulator-type = "voltage"; 16 regulator-type = "voltage";
17 regulator-boot-on; 17 regulator-boot-on;
18 regulator-always-on; 18 regulator-always-on;
19 regulator-min-microvolt = <110 19 regulator-min-microvolt = <1108475>;
20 regulator-max-microvolt = <130 20 regulator-max-microvolt = <1308475>;
21 regulator-ramp-delay = <50>; / 21 regulator-ramp-delay = <50>; /* 4ms */
22 gpios = <&r_pio 0 1 GPIO_ACTIV 22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
23 gpios-states = <0x1>; 23 gpios-states = <0x1>;
24 states = <1108475 0>, <1308475 24 states = <1108475 0>, <1308475 1>;
25 }; 25 };
26 }; 26 };
27 27
28 &cpu0 { 28 &cpu0 {
29 cpu-supply = <®_vdd_cpux>; 29 cpu-supply = <®_vdd_cpux>;
30 }; 30 };
31 31
32 &cpu1 { 32 &cpu1 {
33 cpu-supply = <®_vdd_cpux>; 33 cpu-supply = <®_vdd_cpux>;
34 }; 34 };
35 35
36 &cpu2 { 36 &cpu2 {
37 cpu-supply = <®_vdd_cpux>; 37 cpu-supply = <®_vdd_cpux>;
38 }; 38 };
39 39
40 &cpu3 { 40 &cpu3 {
41 cpu-supply = <®_vdd_cpux>; 41 cpu-supply = <®_vdd_cpux>;
42 }; 42 };
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