1 /*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gma
3 *
4 * This file is dual-licensed: you can use it
5 * of the GPL or the X11 license, at your opti
6 * licensing only applies to this file, and no
7 * whole.
8 *
9 * a) This file is free software; you can red
10 * modify it under the terms of the GNU Ge
11 * published by the Free Software Foundati
12 * License, or (at your option) any later
13 *
14 * This file is distributed in the hope th
15 * but WITHOUT ANY WARRANTY; without even
16 * MERCHANTABILITY or FITNESS FOR A PARTIC
17 * GNU General Public License for more det
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of c
22 * obtaining a copy of this software and a
23 * files (the "Software"), to deal in the
24 * restriction, including without limitati
25 * copy, modify, merge, publish, distribut
26 * sell copies of the Software, and to per
27 * Software is furnished to do so, subject
28 * conditions:
29 *
30 * The above copyright notice and this per
31 * included in all copies or substantial p
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
35 * OF MERCHANTABILITY, FITNESS FOR A PARTI
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
38 * WHETHER IN AN ACTION OF CONTRACT, TORT
39 * FROM, OUT OF OR IN CONNECTION WITH THE
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
51
52 / {
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 chosen {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61
62 framebuffer-hdmi {
63 compatible = "allwinne
64 "simple-f
65 allwinner,pipeline = "
66 clocks = <&display_clo
67 <&ccu CLK_TCO
68 status = "disabled";
69 };
70
71 framebuffer-tve {
72 compatible = "allwinne
73 "simple-f
74 allwinner,pipeline = "
75 clocks = <&display_clo
76 <&ccu CLK_TVE
77 status = "disabled";
78 };
79 };
80
81 clocks {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 osc24M: osc24M-clk {
87 #clock-cells = <0>;
88 compatible = "fixed-cl
89 clock-frequency = <240
90 clock-accuracy = <5000
91 clock-output-names = "
92 };
93
94 osc32k: osc32k-clk {
95 #clock-cells = <0>;
96 compatible = "fixed-cl
97 clock-frequency = <327
98 clock-accuracy = <5000
99 clock-output-names = "
100 };
101 };
102
103 de: display-engine {
104 compatible = "allwinner,sun8i-
105 allwinner,pipelines = <&mixer0
106 status = "disabled";
107 };
108
109 soc {
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 dma-ranges;
114 ranges;
115
116 display_clocks: clock@1000000
117 /* compatible is in pe
118 reg = <0x01000000 0x10
119 clocks = <&ccu CLK_BUS
120 <&ccu CLK_DE>
121 clock-names = "bus",
122 "mod";
123 resets = <&ccu RST_BUS
124 #clock-cells = <1>;
125 #reset-cells = <1>;
126 };
127
128 mixer0: mixer@1100000 {
129 compatible = "allwinne
130 reg = <0x01100000 0x10
131 clocks = <&display_clo
132 <&display_clo
133 clock-names = "bus",
134 "mod";
135 resets = <&display_clo
136
137 ports {
138 #address-cells
139 #size-cells =
140
141 mixer0_out: po
142 reg =
143
144 mixer0
145
146 };
147 };
148 };
149 };
150
151 dma: dma-controller@1c02000 {
152 compatible = "allwinne
153 reg = <0x01c02000 0x10
154 interrupts = <GIC_SPI
155 clocks = <&ccu CLK_BUS
156 resets = <&ccu RST_BUS
157 #dma-cells = <1>;
158 };
159
160 tcon0: lcd-controller@1c0c000
161 compatible = "allwinne
162 "allwinne
163 reg = <0x01c0c000 0x10
164 interrupts = <GIC_SPI
165 clocks = <&ccu CLK_BUS
166 clock-names = "ahb", "
167 resets = <&ccu RST_BUS
168 reset-names = "lcd";
169
170 ports {
171 #address-cells
172 #size-cells =
173
174 tcon0_in: port
175 reg =
176
177 tcon0_
178
179 };
180 };
181
182 tcon0_out: por
183 #addre
184 #size-
185 reg =
186
187 tcon0_
188
189
190 };
191 };
192 };
193 };
194
195 mmc0: mmc@1c0f000 {
196 /* compatible and cloc
197 reg = <0x01c0f000 0x10
198 pinctrl-names = "defau
199 pinctrl-0 = <&mmc0_pin
200 resets = <&ccu RST_BUS
201 reset-names = "ahb";
202 interrupts = <GIC_SPI
203 status = "disabled";
204 #address-cells = <1>;
205 #size-cells = <0>;
206 };
207
208 mmc1: mmc@1c10000 {
209 /* compatible and cloc
210 reg = <0x01c10000 0x10
211 pinctrl-names = "defau
212 pinctrl-0 = <&mmc1_pin
213 resets = <&ccu RST_BUS
214 reset-names = "ahb";
215 interrupts = <GIC_SPI
216 status = "disabled";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 };
220
221 mmc2: mmc@1c11000 {
222 /* compatible and cloc
223 reg = <0x01c11000 0x10
224 resets = <&ccu RST_BUS
225 reset-names = "ahb";
226 interrupts = <GIC_SPI
227 status = "disabled";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
231
232 sid: eeprom@1c14000 {
233 /* compatible is in pe
234 reg = <0x1c14000 0x400
235 #address-cells = <1>;
236 #size-cells = <1>;
237
238 ths_calibration: therm
239 reg = <0x34 4>
240 };
241 };
242
243 msgbox: mailbox@1c17000 {
244 compatible = "allwinne
245 "allwinne
246 reg = <0x01c17000 0x10
247 clocks = <&ccu CLK_BUS
248 resets = <&ccu RST_BUS
249 interrupts = <GIC_SPI
250 #mbox-cells = <1>;
251 };
252
253 usb_otg: usb@1c19000 {
254 compatible = "allwinne
255 reg = <0x01c19000 0x40
256 clocks = <&ccu CLK_BUS
257 resets = <&ccu RST_BUS
258 interrupts = <GIC_SPI
259 interrupt-names = "mc"
260 phys = <&usbphy 0>;
261 phy-names = "usb";
262 extcon = <&usbphy 0>;
263 dr_mode = "otg";
264 status = "disabled";
265 };
266
267 usbphy: phy@1c19400 {
268 compatible = "allwinne
269 reg = <0x01c19400 0x2c
270 <0x01c1a800 0x4>
271 <0x01c1b800 0x4>
272 <0x01c1c800 0x4>
273 <0x01c1d800 0x4>
274 reg-names = "phy_ctrl"
275 "pmu0",
276 "pmu1",
277 "pmu2",
278 "pmu3";
279 clocks = <&ccu CLK_USB
280 <&ccu CLK_USB
281 <&ccu CLK_USB
282 <&ccu CLK_USB
283 clock-names = "usb0_ph
284 "usb1_ph
285 "usb2_ph
286 "usb3_ph
287 resets = <&ccu RST_USB
288 <&ccu RST_USB
289 <&ccu RST_USB
290 <&ccu RST_USB
291 reset-names = "usb0_re
292 "usb1_re
293 "usb2_re
294 "usb3_re
295 status = "disabled";
296 #phy-cells = <1>;
297 };
298
299 ehci0: usb@1c1a000 {
300 compatible = "allwinne
301 reg = <0x01c1a000 0x10
302 interrupts = <GIC_SPI
303 clocks = <&ccu CLK_BUS
304 resets = <&ccu RST_BUS
305 phys = <&usbphy 0>;
306 phy-names = "usb";
307 status = "disabled";
308 };
309
310 ohci0: usb@1c1a400 {
311 compatible = "allwinne
312 reg = <0x01c1a400 0x10
313 interrupts = <GIC_SPI
314 clocks = <&ccu CLK_BUS
315 <&ccu CLK_USB
316 resets = <&ccu RST_BUS
317 phys = <&usbphy 0>;
318 phy-names = "usb";
319 status = "disabled";
320 };
321
322 ehci1: usb@1c1b000 {
323 compatible = "allwinne
324 reg = <0x01c1b000 0x10
325 interrupts = <GIC_SPI
326 clocks = <&ccu CLK_BUS
327 resets = <&ccu RST_BUS
328 phys = <&usbphy 1>;
329 phy-names = "usb";
330 status = "disabled";
331 };
332
333 ohci1: usb@1c1b400 {
334 compatible = "allwinne
335 reg = <0x01c1b400 0x10
336 interrupts = <GIC_SPI
337 clocks = <&ccu CLK_BUS
338 <&ccu CLK_USB
339 resets = <&ccu RST_BUS
340 phys = <&usbphy 1>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ehci2: usb@1c1c000 {
346 compatible = "allwinne
347 reg = <0x01c1c000 0x10
348 interrupts = <GIC_SPI
349 clocks = <&ccu CLK_BUS
350 resets = <&ccu RST_BUS
351 phys = <&usbphy 2>;
352 phy-names = "usb";
353 status = "disabled";
354 };
355
356 ohci2: usb@1c1c400 {
357 compatible = "allwinne
358 reg = <0x01c1c400 0x10
359 interrupts = <GIC_SPI
360 clocks = <&ccu CLK_BUS
361 <&ccu CLK_USB
362 resets = <&ccu RST_BUS
363 phys = <&usbphy 2>;
364 phy-names = "usb";
365 status = "disabled";
366 };
367
368 ehci3: usb@1c1d000 {
369 compatible = "allwinne
370 reg = <0x01c1d000 0x10
371 interrupts = <GIC_SPI
372 clocks = <&ccu CLK_BUS
373 resets = <&ccu RST_BUS
374 phys = <&usbphy 3>;
375 phy-names = "usb";
376 status = "disabled";
377 };
378
379 ohci3: usb@1c1d400 {
380 compatible = "allwinne
381 reg = <0x01c1d400 0x10
382 interrupts = <GIC_SPI
383 clocks = <&ccu CLK_BUS
384 <&ccu CLK_USB
385 resets = <&ccu RST_BUS
386 phys = <&usbphy 3>;
387 phy-names = "usb";
388 status = "disabled";
389 };
390
391 ccu: clock@1c20000 {
392 /* compatible is in pe
393 reg = <0x01c20000 0x40
394 clocks = <&osc24M>, <&
395 clock-names = "hosc",
396 #clock-cells = <1>;
397 #reset-cells = <1>;
398 };
399
400 pio: pinctrl@1c20800 {
401 /* compatible is in pe
402 reg = <0x01c20800 0x40
403 interrupt-parent = <&r
404 interrupts = <GIC_SPI
405 <GIC_SPI
406 clocks = <&ccu CLK_BUS
407 <&rtc CLK_OSC
408 clock-names = "apb", "
409 gpio-controller;
410 #gpio-cells = <3>;
411 interrupt-controller;
412 #interrupt-cells = <3>
413
414 csi_pins: csi-pins {
415 pins = "PE0",
416 "PE6",
417 "PE11";
418 function = "cs
419 };
420
421 emac_rgmii_pins: emac-
422 pins = "PD0",
423 "PD5",
424 "PD12",
425 function = "em
426 drive-strength
427 };
428
429 i2c0_pins: i2c0-pins {
430 pins = "PA11",
431 function = "i2
432 };
433
434 i2c1_pins: i2c1-pins {
435 pins = "PA18",
436 function = "i2
437 };
438
439 i2c2_pins: i2c2-pins {
440 pins = "PE12",
441 function = "i2
442 };
443
444 mmc0_pins: mmc0-pins {
445 pins = "PF0",
446 "PF4",
447 function = "mm
448 drive-strength
449 bias-pull-up;
450 };
451
452 mmc1_pins: mmc1-pins {
453 pins = "PG0",
454 "PG4",
455 function = "mm
456 drive-strength
457 bias-pull-up;
458 };
459
460 mmc2_8bit_pins: mmc2-8
461 pins = "PC5",
462 "PC9",
463 "PC12",
464 "PC15",
465 function = "mm
466 drive-strength
467 bias-pull-up;
468 };
469
470 spdif_tx_pin: spdif-tx
471 pins = "PA17";
472 function = "sp
473 };
474
475 spi0_pins: spi0-pins {
476 pins = "PC0",
477 function = "sp
478 };
479
480 spi1_pins: spi1-pins {
481 pins = "PA15",
482 function = "sp
483 };
484
485 uart0_pa_pins: uart0-p
486 pins = "PA4",
487 function = "ua
488 };
489
490 uart1_pins: uart1-pins
491 pins = "PG6",
492 function = "ua
493 };
494
495 uart1_rts_cts_pins: ua
496 pins = "PG8",
497 function = "ua
498 };
499
500 uart2_pins: uart2-pins
501 pins = "PA0",
502 function = "ua
503 };
504
505 uart2_rts_cts_pins: ua
506 pins = "PA2",
507 function = "ua
508 };
509
510 uart3_pins: uart3-pins
511 pins = "PA13",
512 function = "ua
513 };
514
515 uart3_rts_cts_pins: ua
516 pins = "PA15",
517 function = "ua
518 };
519 };
520
521 timer@1c20c00 {
522 compatible = "allwinne
523 reg = <0x01c20c00 0xa0
524 interrupts = <GIC_SPI
525 <GIC_SPI
526 clocks = <&osc24M>;
527 };
528
529 emac: ethernet@1c30000 {
530 compatible = "allwinne
531 syscon = <&syscon>;
532 reg = <0x01c30000 0x10
533 interrupts = <GIC_SPI
534 interrupt-names = "mac
535 resets = <&ccu RST_BUS
536 reset-names = "stmmace
537 clocks = <&ccu CLK_BUS
538 clock-names = "stmmace
539 status = "disabled";
540
541 mdio: mdio {
542 #address-cells
543 #size-cells =
544 compatible = "
545 };
546
547 mdio-mux {
548 compatible = "
549 #address-cells
550 #size-cells =
551
552 mdio-parent-bu
553 /* Only one MD
554 internal_mdio:
555 compat
556 reg =
557 #addre
558 #size-
559
560 int_mi
561
562
563
564
565 };
566 };
567
568 external_mdio:
569 reg =
570 #addre
571 #size-
572 };
573 };
574 };
575
576 mbus: dram-controller@1c62000
577 /* compatible is in pe
578 reg = <0x01c62000 0x10
579 <0x01c63000 0x10
580 reg-names = "mbus", "d
581 clocks = <&ccu CLK_MBU
582 <&ccu CLK_DRA
583 <&ccu CLK_BUS
584 clock-names = "mbus",
585 #address-cells = <1>;
586 #size-cells = <1>;
587 dma-ranges = <0x000000
588 #interconnect-cells =
589 };
590
591 spi0: spi@1c68000 {
592 compatible = "allwinne
593 reg = <0x01c68000 0x10
594 interrupts = <GIC_SPI
595 clocks = <&ccu CLK_BUS
596 clock-names = "ahb", "
597 dmas = <&dma 23>, <&dm
598 dma-names = "rx", "tx"
599 pinctrl-names = "defau
600 pinctrl-0 = <&spi0_pin
601 resets = <&ccu RST_BUS
602 status = "disabled";
603 #address-cells = <1>;
604 #size-cells = <0>;
605 };
606
607 spi1: spi@1c69000 {
608 compatible = "allwinne
609 reg = <0x01c69000 0x10
610 interrupts = <GIC_SPI
611 clocks = <&ccu CLK_BUS
612 clock-names = "ahb", "
613 dmas = <&dma 24>, <&dm
614 dma-names = "rx", "tx"
615 pinctrl-names = "defau
616 pinctrl-0 = <&spi1_pin
617 resets = <&ccu RST_BUS
618 status = "disabled";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 };
622
623 wdt0: watchdog@1c20ca0 {
624 compatible = "allwinne
625 reg = <0x01c20ca0 0x20
626 interrupts = <GIC_SPI
627 clocks = <&osc24M>;
628 };
629
630 spdif: spdif@1c21000 {
631 #sound-dai-cells = <0>
632 compatible = "allwinne
633 reg = <0x01c21000 0x40
634 interrupts = <GIC_SPI
635 clocks = <&ccu CLK_BUS
636 resets = <&ccu RST_BUS
637 clock-names = "apb", "
638 dmas = <&dma 2>;
639 dma-names = "tx";
640 status = "disabled";
641 };
642
643 pwm: pwm@1c21400 {
644 compatible = "allwinne
645 reg = <0x01c21400 0x8>
646 clocks = <&osc24M>;
647 #pwm-cells = <3>;
648 status = "disabled";
649 };
650
651 i2s0: i2s@1c22000 {
652 #sound-dai-cells = <0>
653 compatible = "allwinne
654 reg = <0x01c22000 0x40
655 interrupts = <GIC_SPI
656 clocks = <&ccu CLK_BUS
657 clock-names = "apb", "
658 dmas = <&dma 3>, <&dma
659 resets = <&ccu RST_BUS
660 dma-names = "rx", "tx"
661 status = "disabled";
662 };
663
664 i2s1: i2s@1c22400 {
665 #sound-dai-cells = <0>
666 compatible = "allwinne
667 reg = <0x01c22400 0x40
668 interrupts = <GIC_SPI
669 clocks = <&ccu CLK_BUS
670 clock-names = "apb", "
671 dmas = <&dma 4>, <&dma
672 resets = <&ccu RST_BUS
673 dma-names = "rx", "tx"
674 status = "disabled";
675 };
676
677 i2s2: i2s@1c22800 {
678 #sound-dai-cells = <0>
679 compatible = "allwinne
680 reg = <0x01c22800 0x40
681 interrupts = <GIC_SPI
682 clocks = <&ccu CLK_BUS
683 clock-names = "apb", "
684 dmas = <&dma 27>;
685 resets = <&ccu RST_BUS
686 dma-names = "tx";
687 status = "disabled";
688 };
689
690 codec: codec@1c22c00 {
691 #sound-dai-cells = <0>
692 compatible = "allwinne
693 reg = <0x01c22c00 0x40
694 interrupts = <GIC_SPI
695 clocks = <&ccu CLK_BUS
696 clock-names = "apb", "
697 resets = <&ccu RST_BUS
698 dmas = <&dma 15>, <&dm
699 dma-names = "rx", "tx"
700 allwinner,codec-analog
701 status = "disabled";
702 };
703
704 uart0: serial@1c28000 {
705 compatible = "snps,dw-
706 reg = <0x01c28000 0x40
707 interrupts = <GIC_SPI
708 reg-shift = <2>;
709 reg-io-width = <4>;
710 clocks = <&ccu CLK_BUS
711 resets = <&ccu RST_BUS
712 dmas = <&dma 6>, <&dma
713 dma-names = "tx", "rx"
714 status = "disabled";
715 };
716
717 uart1: serial@1c28400 {
718 compatible = "snps,dw-
719 reg = <0x01c28400 0x40
720 interrupts = <GIC_SPI
721 reg-shift = <2>;
722 reg-io-width = <4>;
723 clocks = <&ccu CLK_BUS
724 resets = <&ccu RST_BUS
725 dmas = <&dma 7>, <&dma
726 dma-names = "tx", "rx"
727 status = "disabled";
728 };
729
730 uart2: serial@1c28800 {
731 compatible = "snps,dw-
732 reg = <0x01c28800 0x40
733 interrupts = <GIC_SPI
734 reg-shift = <2>;
735 reg-io-width = <4>;
736 clocks = <&ccu CLK_BUS
737 resets = <&ccu RST_BUS
738 dmas = <&dma 8>, <&dma
739 dma-names = "tx", "rx"
740 status = "disabled";
741 };
742
743 uart3: serial@1c28c00 {
744 compatible = "snps,dw-
745 reg = <0x01c28c00 0x40
746 interrupts = <GIC_SPI
747 reg-shift = <2>;
748 reg-io-width = <4>;
749 clocks = <&ccu CLK_BUS
750 resets = <&ccu RST_BUS
751 dmas = <&dma 9>, <&dma
752 dma-names = "tx", "rx"
753 status = "disabled";
754 };
755
756 i2c0: i2c@1c2ac00 {
757 compatible = "allwinne
758 reg = <0x01c2ac00 0x40
759 interrupts = <GIC_SPI
760 clocks = <&ccu CLK_BUS
761 resets = <&ccu RST_BUS
762 pinctrl-names = "defau
763 pinctrl-0 = <&i2c0_pin
764 status = "disabled";
765 #address-cells = <1>;
766 #size-cells = <0>;
767 };
768
769 i2c1: i2c@1c2b000 {
770 compatible = "allwinne
771 reg = <0x01c2b000 0x40
772 interrupts = <GIC_SPI
773 clocks = <&ccu CLK_BUS
774 resets = <&ccu RST_BUS
775 pinctrl-names = "defau
776 pinctrl-0 = <&i2c1_pin
777 status = "disabled";
778 #address-cells = <1>;
779 #size-cells = <0>;
780 };
781
782 i2c2: i2c@1c2b400 {
783 compatible = "allwinne
784 reg = <0x01c2b400 0x40
785 interrupts = <GIC_SPI
786 clocks = <&ccu CLK_BUS
787 resets = <&ccu RST_BUS
788 pinctrl-names = "defau
789 pinctrl-0 = <&i2c2_pin
790 status = "disabled";
791 #address-cells = <1>;
792 #size-cells = <0>;
793 };
794
795 gic: interrupt-controller@1c81
796 compatible = "arm,gic-
797 reg = <0x01c81000 0x10
798 <0x01c82000 0x20
799 <0x01c84000 0x20
800 <0x01c86000 0x20
801 interrupt-controller;
802 #interrupt-cells = <3>
803 interrupts = <GIC_PPI
804 };
805
806 csi: camera@1cb0000 {
807 compatible = "allwinne
808 reg = <0x01cb0000 0x10
809 interrupts = <GIC_SPI
810 clocks = <&ccu CLK_BUS
811 <&ccu CLK_CSI
812 <&ccu CLK_DRA
813 clock-names = "bus", "
814 resets = <&ccu RST_BUS
815 pinctrl-names = "defau
816 pinctrl-0 = <&csi_pins
817 status = "disabled";
818 };
819
820 hdmi: hdmi@1ee0000 {
821 compatible = "allwinne
822 "allwinne
823 reg = <0x01ee0000 0x10
824 reg-io-width = <1>;
825 interrupts = <GIC_SPI
826 clocks = <&ccu CLK_BUS
827 <&ccu CLK_HDM
828 clock-names = "iahb",
829 resets = <&ccu RST_BUS
830 reset-names = "ctrl";
831 phys = <&hdmi_phy>;
832 phy-names = "phy";
833 status = "disabled";
834
835 ports {
836 #address-cells
837 #size-cells =
838
839 hdmi_in: port@
840 reg =
841
842 hdmi_i
843
844 };
845 };
846
847 hdmi_out: port
848 reg =
849 };
850 };
851 };
852
853 hdmi_phy: hdmi-phy@1ef0000 {
854 compatible = "allwinne
855 reg = <0x01ef0000 0x10
856 clocks = <&ccu CLK_BUS
857 <&ccu CLK_PLL
858 clock-names = "bus", "
859 resets = <&ccu RST_BUS
860 reset-names = "phy";
861 #phy-cells = <0>;
862 };
863
864 rtc: rtc@1f00000 {
865 /* compatible is in pe
866 reg = <0x01f00000 0x40
867 interrupt-parent = <&r
868 interrupts = <GIC_SPI
869 <GIC_SPI
870 clock-output-names = "
871 clocks = <&osc32k>;
872 #clock-cells = <1>;
873 };
874
875 r_intc: interrupt-controller@1
876 compatible = "allwinne
877 "allwinne
878 interrupt-controller;
879 #interrupt-cells = <3>
880 reg = <0x01f00c00 0x40
881 interrupts = <GIC_SPI
882 };
883
884 r_ccu: clock@1f01400 {
885 compatible = "allwinne
886 reg = <0x01f01400 0x10
887 clocks = <&osc24M>, <&
888 <&ccu CLK_PLL
889 clock-names = "hosc",
890 #clock-cells = <1>;
891 #reset-cells = <1>;
892 };
893
894 codec_analog: codec-analog@1f0
895 compatible = "allwinne
896 reg = <0x01f015c0 0x4>
897 };
898
899 ir: ir@1f02000 {
900 compatible = "allwinne
901 clocks = <&r_ccu CLK_A
902 clock-names = "apb", "
903 resets = <&r_ccu RST_A
904 interrupts = <GIC_SPI
905 reg = <0x01f02000 0x40
906 status = "disabled";
907 };
908
909 r_i2c: i2c@1f02400 {
910 compatible = "allwinne
911 reg = <0x01f02400 0x40
912 interrupts = <GIC_SPI
913 pinctrl-names = "defau
914 pinctrl-0 = <&r_i2c_pi
915 clocks = <&r_ccu CLK_A
916 resets = <&r_ccu RST_A
917 status = "disabled";
918 #address-cells = <1>;
919 #size-cells = <0>;
920 };
921
922 r_uart: serial@1f02800 {
923 compatible = "snps,dw-
924 reg = <0x01f02800 0x40
925 interrupts = <GIC_SPI
926 reg-shift = <2>;
927 reg-io-width = <4>;
928 clocks = <&r_ccu CLK_A
929 resets = <&r_ccu RST_A
930 pinctrl-names = "defau
931 pinctrl-0 = <&r_uart_p
932 status = "disabled";
933 };
934
935 r_pio: pinctrl@1f02c00 {
936 compatible = "allwinne
937 reg = <0x01f02c00 0x40
938 interrupt-parent = <&r
939 interrupts = <GIC_SPI
940 clocks = <&r_ccu CLK_A
941 <&rtc CLK_OSC
942 clock-names = "apb", "
943 gpio-controller;
944 #gpio-cells = <3>;
945 interrupt-controller;
946 #interrupt-cells = <3>
947
948 r_ir_rx_pin: r-ir-rx-p
949 pins = "PL11";
950 function = "s_
951 };
952
953 r_i2c_pins: r-i2c-pins
954 pins = "PL0",
955 function = "s_
956 };
957
958 r_pwm_pin: r-pwm-pin {
959 pins = "PL10";
960 function = "s_
961 };
962
963 r_uart_pins: r-uart-pi
964 pins = "PL2",
965 function = "s_
966 };
967 };
968
969 r_pwm: pwm@1f03800 {
970 compatible = "allwinne
971 reg = <0x01f03800 0x8>
972 pinctrl-names = "defau
973 pinctrl-0 = <&r_pwm_pi
974 clocks = <&osc24M>;
975 #pwm-cells = <3>;
976 status = "disabled";
977 };
978 };
979 };
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