1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h> 2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/asp 3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
4 4
5 / { 5 / {
6 model = "Aspeed BMC"; 6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2500"; 7 compatible = "aspeed,ast2500";
8 #address-cells = <1>; 8 #address-cells = <1>;
9 #size-cells = <1>; 9 #size-cells = <1>;
10 interrupt-parent = <&vic>; 10 interrupt-parent = <&vic>;
11 11
12 aliases { 12 aliases {
13 i2c0 = &i2c0; 13 i2c0 = &i2c0;
14 i2c1 = &i2c1; 14 i2c1 = &i2c1;
15 i2c2 = &i2c2; 15 i2c2 = &i2c2;
16 i2c3 = &i2c3; 16 i2c3 = &i2c3;
17 i2c4 = &i2c4; 17 i2c4 = &i2c4;
18 i2c5 = &i2c5; 18 i2c5 = &i2c5;
19 i2c6 = &i2c6; 19 i2c6 = &i2c6;
20 i2c7 = &i2c7; 20 i2c7 = &i2c7;
21 i2c8 = &i2c8; 21 i2c8 = &i2c8;
22 i2c9 = &i2c9; 22 i2c9 = &i2c9;
23 i2c10 = &i2c10; 23 i2c10 = &i2c10;
24 i2c11 = &i2c11; 24 i2c11 = &i2c11;
25 i2c12 = &i2c12; 25 i2c12 = &i2c12;
26 i2c13 = &i2c13; 26 i2c13 = &i2c13;
27 serial0 = &uart1; 27 serial0 = &uart1;
28 serial1 = &uart2; 28 serial1 = &uart2;
29 serial2 = &uart3; 29 serial2 = &uart3;
30 serial3 = &uart4; 30 serial3 = &uart4;
31 serial4 = &uart5; 31 serial4 = &uart5;
32 serial5 = &vuart; 32 serial5 = &vuart;
33 }; 33 };
34 34
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 38
39 cpu@0 { 39 cpu@0 {
40 compatible = "arm,arm1 40 compatible = "arm,arm1176jzf-s";
41 device_type = "cpu"; 41 device_type = "cpu";
42 reg = <0>; 42 reg = <0>;
43 }; 43 };
44 }; 44 };
45 45
46 memory@80000000 { 46 memory@80000000 {
47 device_type = "memory"; 47 device_type = "memory";
48 reg = <0x80000000 0>; 48 reg = <0x80000000 0>;
49 }; 49 };
50 50
51 ahb { 51 ahb {
52 compatible = "simple-bus"; 52 compatible = "simple-bus";
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 ranges; 55 ranges;
56 56
57 fmc: spi@1e620000 { 57 fmc: spi@1e620000 {
58 reg = <0x1e620000 0xc4 58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <0>; 60 #size-cells = <0>;
61 compatible = "aspeed,a 61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPE 62 clocks = <&syscon ASPEED_CLK_AHB>;
63 status = "disabled"; 63 status = "disabled";
64 interrupts = <19>; 64 interrupts = <19>;
65 flash@0 { 65 flash@0 {
66 reg = < 0 >; 66 reg = < 0 >;
67 compatible = " 67 compatible = "jedec,spi-nor";
68 spi-max-freque 68 spi-max-frequency = <50000000>;
69 spi-rx-bus-wid 69 spi-rx-bus-width = <2>;
70 status = "disa 70 status = "disabled";
71 }; 71 };
72 flash@1 { 72 flash@1 {
73 reg = < 1 >; 73 reg = < 1 >;
74 compatible = " 74 compatible = "jedec,spi-nor";
75 spi-max-freque 75 spi-max-frequency = <50000000>;
76 spi-rx-bus-wid 76 spi-rx-bus-width = <2>;
77 status = "disa 77 status = "disabled";
78 }; 78 };
79 flash@2 { 79 flash@2 {
80 reg = < 2 >; 80 reg = < 2 >;
81 compatible = " 81 compatible = "jedec,spi-nor";
82 spi-max-freque 82 spi-max-frequency = <50000000>;
83 spi-rx-bus-wid 83 spi-rx-bus-width = <2>;
84 status = "disa 84 status = "disabled";
85 }; 85 };
86 }; 86 };
87 87
88 spi1: spi@1e630000 { 88 spi1: spi@1e630000 {
89 reg = <0x1e630000 0xc4 89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <0>; 91 #size-cells = <0>;
92 compatible = "aspeed,a 92 compatible = "aspeed,ast2500-spi";
93 clocks = <&syscon ASPE 93 clocks = <&syscon ASPEED_CLK_AHB>;
94 status = "disabled"; 94 status = "disabled";
95 flash@0 { 95 flash@0 {
96 reg = < 0 >; 96 reg = < 0 >;
97 compatible = " 97 compatible = "jedec,spi-nor";
98 spi-max-freque 98 spi-max-frequency = <50000000>;
99 spi-rx-bus-wid 99 spi-rx-bus-width = <2>;
100 status = "disa 100 status = "disabled";
101 }; 101 };
102 flash@1 { 102 flash@1 {
103 reg = < 1 >; 103 reg = < 1 >;
104 compatible = " 104 compatible = "jedec,spi-nor";
105 spi-max-freque 105 spi-max-frequency = <50000000>;
106 spi-rx-bus-wid 106 spi-rx-bus-width = <2>;
107 status = "disa 107 status = "disabled";
108 }; 108 };
109 }; 109 };
110 110
111 spi2: spi@1e631000 { 111 spi2: spi@1e631000 {
112 reg = <0x1e631000 0xc4 112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
113 #address-cells = <1>; 113 #address-cells = <1>;
114 #size-cells = <0>; 114 #size-cells = <0>;
115 compatible = "aspeed,a 115 compatible = "aspeed,ast2500-spi";
116 clocks = <&syscon ASPE 116 clocks = <&syscon ASPEED_CLK_AHB>;
117 status = "disabled"; 117 status = "disabled";
118 flash@0 { 118 flash@0 {
119 reg = < 0 >; 119 reg = < 0 >;
120 compatible = " 120 compatible = "jedec,spi-nor";
121 spi-max-freque 121 spi-max-frequency = <50000000>;
122 spi-rx-bus-wid 122 spi-rx-bus-width = <2>;
123 status = "disa 123 status = "disabled";
124 }; 124 };
125 flash@1 { 125 flash@1 {
126 reg = < 1 >; 126 reg = < 1 >;
127 compatible = " 127 compatible = "jedec,spi-nor";
128 spi-max-freque 128 spi-max-frequency = <50000000>;
129 spi-rx-bus-wid 129 spi-rx-bus-width = <2>;
130 status = "disa 130 status = "disabled";
131 }; 131 };
132 }; 132 };
133 133
134 vic: interrupt-controller@1e6c 134 vic: interrupt-controller@1e6c0080 {
135 compatible = "aspeed,a 135 compatible = "aspeed,ast2400-vic";
136 interrupt-controller; 136 interrupt-controller;
137 #interrupt-cells = <1> 137 #interrupt-cells = <1>;
138 valid-sources = <0xfef 138 valid-sources = <0xfefff7ff 0x0807ffff>;
139 reg = <0x1e6c0080 0x80 139 reg = <0x1e6c0080 0x80>;
140 }; 140 };
141 141
142 cvic: interrupt-controller@1e6 !! 142 cvic: copro-interrupt-controller@1e6c2000 {
143 compatible = "aspeed,a !! 143 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
144 valid-sources = <0xfff 144 valid-sources = <0xffffffff>;
145 copro-sw-interrupts = 145 copro-sw-interrupts = <1>;
146 reg = <0x1e6c2000 0x80 146 reg = <0x1e6c2000 0x80>;
147 }; 147 };
148 148
149 mac0: ethernet@1e660000 { 149 mac0: ethernet@1e660000 {
150 compatible = "aspeed,a 150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
151 reg = <0x1e660000 0x18 151 reg = <0x1e660000 0x180>;
152 interrupts = <2>; 152 interrupts = <2>;
153 clocks = <&syscon ASPE 153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
154 status = "disabled"; 154 status = "disabled";
155 }; 155 };
156 156
157 mac1: ethernet@1e680000 { 157 mac1: ethernet@1e680000 {
158 compatible = "aspeed,a 158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
159 reg = <0x1e680000 0x18 159 reg = <0x1e680000 0x180>;
160 interrupts = <3>; 160 interrupts = <3>;
161 clocks = <&syscon ASPE 161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
162 status = "disabled"; 162 status = "disabled";
163 }; 163 };
164 164
165 ehci0: usb@1e6a1000 { 165 ehci0: usb@1e6a1000 {
166 compatible = "aspeed,a 166 compatible = "aspeed,ast2500-ehci", "generic-ehci";
167 reg = <0x1e6a1000 0x10 167 reg = <0x1e6a1000 0x100>;
168 interrupts = <5>; 168 interrupts = <5>;
169 clocks = <&syscon ASPE 169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
170 pinctrl-names = "defau 170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_ 171 pinctrl-0 = <&pinctrl_usb2ah_default>;
172 status = "disabled"; 172 status = "disabled";
173 }; 173 };
174 174
175 ehci1: usb@1e6a3000 { 175 ehci1: usb@1e6a3000 {
176 compatible = "aspeed,a 176 compatible = "aspeed,ast2500-ehci", "generic-ehci";
177 reg = <0x1e6a3000 0x10 177 reg = <0x1e6a3000 0x100>;
178 interrupts = <13>; 178 interrupts = <13>;
179 clocks = <&syscon ASPE 179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
180 pinctrl-names = "defau 180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_ 181 pinctrl-0 = <&pinctrl_usb2bh_default>;
182 status = "disabled"; 182 status = "disabled";
183 }; 183 };
184 184
185 uhci: usb@1e6b0000 { 185 uhci: usb@1e6b0000 {
186 compatible = "aspeed,a 186 compatible = "aspeed,ast2500-uhci", "generic-uhci";
187 reg = <0x1e6b0000 0x10 187 reg = <0x1e6b0000 0x100>;
188 interrupts = <14>; 188 interrupts = <14>;
189 #ports = <2>; 189 #ports = <2>;
190 clocks = <&syscon ASPE 190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
191 status = "disabled"; 191 status = "disabled";
192 /* 192 /*
193 * No default pinmux, 193 * No default pinmux, it will follow EHCI, use an explicit pinmux
194 * override if you don 194 * override if you don't enable EHCI
195 */ 195 */
196 }; 196 };
197 197
198 vhub: usb-vhub@1e6a0000 { 198 vhub: usb-vhub@1e6a0000 {
199 compatible = "aspeed,a 199 compatible = "aspeed,ast2500-usb-vhub";
200 reg = <0x1e6a0000 0x30 200 reg = <0x1e6a0000 0x300>;
201 interrupts = <5>; 201 interrupts = <5>;
202 clocks = <&syscon ASPE 202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
203 aspeed,vhub-downstream 203 aspeed,vhub-downstream-ports = <5>;
204 aspeed,vhub-generic-en 204 aspeed,vhub-generic-endpoints = <15>;
205 pinctrl-names = "defau 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_ 206 pinctrl-0 = <&pinctrl_usb2ad_default>;
207 status = "disabled"; 207 status = "disabled";
208 }; 208 };
209 209
210 apb { 210 apb {
211 compatible = "simple-b 211 compatible = "simple-bus";
212 #address-cells = <1>; 212 #address-cells = <1>;
213 #size-cells = <1>; 213 #size-cells = <1>;
214 ranges; 214 ranges;
215 215
216 edac: memory-controlle 216 edac: memory-controller@1e6e0000 {
217 compatible = " 217 compatible = "aspeed,ast2500-sdram-edac";
218 reg = <0x1e6e0 218 reg = <0x1e6e0000 0x174>;
219 interrupts = < 219 interrupts = <0>;
220 status = "disa 220 status = "disabled";
221 }; 221 };
222 222
223 syscon: syscon@1e6e200 223 syscon: syscon@1e6e2000 {
224 compatible = " 224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
225 reg = <0x1e6e2 225 reg = <0x1e6e2000 0x1a8>;
226 #address-cells 226 #address-cells = <1>;
227 #size-cells = 227 #size-cells = <1>;
228 ranges = <0 0x 228 ranges = <0 0x1e6e2000 0x1000>;
229 #clock-cells = 229 #clock-cells = <1>;
230 #reset-cells = 230 #reset-cells = <1>;
231 231
232 scu_ic: interr 232 scu_ic: interrupt-controller@18 {
233 #inter 233 #interrupt-cells = <1>;
234 compat 234 compatible = "aspeed,ast2500-scu-ic";
235 reg = 235 reg = <0x18 0x4>;
236 interr 236 interrupts = <21>;
237 interr 237 interrupt-controller;
238 }; 238 };
239 239
240 p2a: p2a-contr 240 p2a: p2a-control@2c {
241 compat 241 compatible = "aspeed,ast2500-p2a-ctrl";
242 reg = 242 reg = <0x2c 0x4>;
243 status 243 status = "disabled";
244 }; 244 };
245 245
246 silicon-id@7c 246 silicon-id@7c {
247 compat 247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
248 reg = 248 reg = <0x7c 0x4 0x150 0x8>;
249 }; 249 };
250 250
251 pinctrl: pinct 251 pinctrl: pinctrl@80 {
252 compat 252 compatible = "aspeed,ast2500-pinctrl";
253 reg = 253 reg = <0x80 0x18>, <0xa0 0x10>;
254 aspeed 254 aspeed,external-nodes = <&gfx>, <&lhc>;
255 }; 255 };
256 }; 256 };
257 257
258 rng: hwrng@1e6e2078 { 258 rng: hwrng@1e6e2078 {
259 compatible = " 259 compatible = "timeriomem_rng";
260 reg = <0x1e6e2 260 reg = <0x1e6e2078 0x4>;
261 period = <1>; 261 period = <1>;
262 quality = <100 262 quality = <100>;
263 }; 263 };
264 264
265 hace: crypto@1e6e3000 265 hace: crypto@1e6e3000 {
266 compatible = " 266 compatible = "aspeed,ast2500-hace";
267 reg = <0x1e6e3 267 reg = <0x1e6e3000 0x100>;
268 interrupts = < 268 interrupts = <4>;
269 clocks = <&sys 269 clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
270 resets = <&sys 270 resets = <&syscon ASPEED_RESET_HACE>;
271 }; 271 };
272 272
273 gfx: display@1e6e6000 273 gfx: display@1e6e6000 {
274 compatible = " 274 compatible = "aspeed,ast2500-gfx", "syscon";
275 reg = <0x1e6e6 275 reg = <0x1e6e6000 0x1000>;
276 reg-io-width = 276 reg-io-width = <4>;
277 clocks = <&sys 277 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
278 resets = <&sys 278 resets = <&syscon ASPEED_RESET_CRT1>;
279 syscon = <&sys 279 syscon = <&syscon>;
280 status = "disa 280 status = "disabled";
281 interrupts = < 281 interrupts = <0x19>;
282 }; 282 };
283 283
>> 284 xdma: xdma@1e6e7000 {
>> 285 compatible = "aspeed,ast2500-xdma";
>> 286 reg = <0x1e6e7000 0x100>;
>> 287 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
>> 288 resets = <&syscon ASPEED_RESET_XDMA>;
>> 289 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
>> 290 aspeed,pcie-device = "bmc";
>> 291 aspeed,scu = <&syscon>;
>> 292 status = "disabled";
>> 293 };
>> 294
284 adc: adc@1e6e9000 { 295 adc: adc@1e6e9000 {
285 compatible = " 296 compatible = "aspeed,ast2500-adc";
286 reg = <0x1e6e9 297 reg = <0x1e6e9000 0xb0>;
287 clocks = <&sys 298 clocks = <&syscon ASPEED_CLK_APB>;
288 resets = <&sys 299 resets = <&syscon ASPEED_RESET_ADC>;
289 #io-channel-ce 300 #io-channel-cells = <1>;
290 status = "disa 301 status = "disabled";
291 }; 302 };
292 303
293 video: video@1e700000 304 video: video@1e700000 {
294 compatible = " 305 compatible = "aspeed,ast2500-video-engine";
295 reg = <0x1e700 306 reg = <0x1e700000 0x1000>;
296 clocks = <&sys 307 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
297 <&sys 308 <&syscon ASPEED_CLK_GATE_ECLK>;
298 clock-names = 309 clock-names = "vclk", "eclk";
299 interrupts = < 310 interrupts = <7>;
300 status = "disa 311 status = "disabled";
301 }; 312 };
302 313
303 sram: sram@1e720000 { 314 sram: sram@1e720000 {
304 compatible = " 315 compatible = "mmio-sram";
305 reg = <0x1e720 316 reg = <0x1e720000 0x9000>; // 36K
306 ranges; <<
307 #address-cells <<
308 #size-cells = <<
309 }; 317 };
310 318
311 sdmmc: sd-controller@1 319 sdmmc: sd-controller@1e740000 {
312 compatible = " 320 compatible = "aspeed,ast2500-sd-controller";
313 reg = <0x1e740 321 reg = <0x1e740000 0x100>;
314 #address-cells 322 #address-cells = <1>;
315 #size-cells = 323 #size-cells = <1>;
316 ranges = <0 0x 324 ranges = <0 0x1e740000 0x10000>;
317 clocks = <&sys 325 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
318 status = "disa 326 status = "disabled";
319 327
320 sdhci0: sdhci@ 328 sdhci0: sdhci@100 {
321 compat 329 compatible = "aspeed,ast2500-sdhci";
322 reg = 330 reg = <0x100 0x100>;
323 interr 331 interrupts = <26>;
324 sdhci, 332 sdhci,auto-cmd12;
325 clocks 333 clocks = <&syscon ASPEED_CLK_SDIO>;
326 status 334 status = "disabled";
327 }; 335 };
328 336
329 sdhci1: sdhci@ 337 sdhci1: sdhci@200 {
330 compat 338 compatible = "aspeed,ast2500-sdhci";
331 reg = 339 reg = <0x200 0x100>;
332 interr 340 interrupts = <26>;
333 sdhci, 341 sdhci,auto-cmd12;
334 clocks 342 clocks = <&syscon ASPEED_CLK_SDIO>;
335 status 343 status = "disabled";
336 }; 344 };
337 }; 345 };
338 346
339 gpio: gpio@1e780000 { 347 gpio: gpio@1e780000 {
340 #gpio-cells = 348 #gpio-cells = <2>;
341 gpio-controlle 349 gpio-controller;
342 compatible = " 350 compatible = "aspeed,ast2500-gpio";
343 reg = <0x1e780 351 reg = <0x1e780000 0x200>;
344 interrupts = < 352 interrupts = <20>;
345 gpio-ranges = 353 gpio-ranges = <&pinctrl 0 0 232>;
346 clocks = <&sys 354 clocks = <&syscon ASPEED_CLK_APB>;
347 interrupt-cont 355 interrupt-controller;
348 #interrupt-cel 356 #interrupt-cells = <2>;
349 }; 357 };
350 358
351 sgpio: sgpio@1e780200 359 sgpio: sgpio@1e780200 {
352 #gpio-cells = 360 #gpio-cells = <2>;
353 compatible = " 361 compatible = "aspeed,ast2500-sgpio";
354 gpio-controlle 362 gpio-controller;
355 interrupts = < 363 interrupts = <40>;
356 reg = <0x1e780 364 reg = <0x1e780200 0x0100>;
357 clocks = <&sys 365 clocks = <&syscon ASPEED_CLK_APB>;
358 #interrupt-cel 366 #interrupt-cells = <2>;
359 interrupt-cont 367 interrupt-controller;
360 bus-frequency 368 bus-frequency = <12000000>;
361 pinctrl-names 369 pinctrl-names = "default";
362 pinctrl-0 = <& 370 pinctrl-0 = <&pinctrl_sgpm_default>;
363 status = "disa 371 status = "disabled";
364 }; 372 };
365 373
366 rtc: rtc@1e781000 { 374 rtc: rtc@1e781000 {
367 compatible = " 375 compatible = "aspeed,ast2500-rtc";
368 reg = <0x1e781 376 reg = <0x1e781000 0x18>;
369 status = "disa 377 status = "disabled";
370 }; 378 };
371 379
372 timer: timer@1e782000 380 timer: timer@1e782000 {
373 /* This timer 381 /* This timer is a Faraday FTTMR010 derivative */
374 compatible = " 382 compatible = "aspeed,ast2400-timer";
375 reg = <0x1e782 383 reg = <0x1e782000 0x90>;
376 interrupts = < 384 interrupts = <16 17 18 35 36 37 38 39>;
377 clocks = <&sys 385 clocks = <&syscon ASPEED_CLK_APB>;
378 clock-names = 386 clock-names = "PCLK";
379 }; 387 };
380 388
381 uart1: serial@1e783000 389 uart1: serial@1e783000 {
382 compatible = " 390 compatible = "ns16550a";
383 reg = <0x1e783 391 reg = <0x1e783000 0x20>;
384 reg-shift = <2 392 reg-shift = <2>;
385 interrupts = < 393 interrupts = <9>;
386 clocks = <&sys 394 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
387 resets = <&lpc 395 resets = <&lpc_reset 4>;
388 no-loopback-te 396 no-loopback-test;
389 status = "disa 397 status = "disabled";
390 }; 398 };
391 399
392 uart5: serial@1e784000 400 uart5: serial@1e784000 {
393 compatible = " 401 compatible = "ns16550a";
394 reg = <0x1e784 402 reg = <0x1e784000 0x20>;
395 reg-shift = <2 403 reg-shift = <2>;
396 interrupts = < 404 interrupts = <10>;
397 clocks = <&sys 405 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
398 no-loopback-te 406 no-loopback-test;
399 status = "disa 407 status = "disabled";
400 }; 408 };
401 409
402 wdt1: watchdog@1e78500 410 wdt1: watchdog@1e785000 {
403 compatible = " 411 compatible = "aspeed,ast2500-wdt";
404 reg = <0x1e785 412 reg = <0x1e785000 0x20>;
405 clocks = <&sys 413 clocks = <&syscon ASPEED_CLK_APB>;
406 }; 414 };
407 415
408 wdt2: watchdog@1e78502 416 wdt2: watchdog@1e785020 {
409 compatible = " 417 compatible = "aspeed,ast2500-wdt";
410 reg = <0x1e785 418 reg = <0x1e785020 0x20>;
411 clocks = <&sys 419 clocks = <&syscon ASPEED_CLK_APB>;
412 }; 420 };
413 421
414 wdt3: watchdog@1e78504 422 wdt3: watchdog@1e785040 {
415 compatible = " 423 compatible = "aspeed,ast2500-wdt";
416 reg = <0x1e785 424 reg = <0x1e785040 0x20>;
417 clocks = <&sys 425 clocks = <&syscon ASPEED_CLK_APB>;
418 status = "disa 426 status = "disabled";
419 }; 427 };
420 428
421 pwm_tacho: pwm-tacho-c 429 pwm_tacho: pwm-tacho-controller@1e786000 {
422 compatible = " 430 compatible = "aspeed,ast2500-pwm-tacho";
423 #address-cells 431 #address-cells = <1>;
424 #size-cells = 432 #size-cells = <0>;
425 reg = <0x1e786 433 reg = <0x1e786000 0x1000>;
426 clocks = <&sys 434 clocks = <&syscon ASPEED_CLK_24M>;
427 resets = <&sys 435 resets = <&syscon ASPEED_RESET_PWM>;
428 status = "disa 436 status = "disabled";
429 }; 437 };
430 438
431 vuart: serial@1e787000 439 vuart: serial@1e787000 {
432 compatible = " 440 compatible = "aspeed,ast2500-vuart";
433 reg = <0x1e787 441 reg = <0x1e787000 0x40>;
434 reg-shift = <2 442 reg-shift = <2>;
435 interrupts = < 443 interrupts = <8>;
436 clocks = <&sys 444 clocks = <&syscon ASPEED_CLK_APB>;
437 no-loopback-te 445 no-loopback-test;
438 status = "disa 446 status = "disabled";
439 }; 447 };
440 448
441 lpc: lpc@1e789000 { 449 lpc: lpc@1e789000 {
442 compatible = " 450 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
443 reg = <0x1e789 451 reg = <0x1e789000 0x1000>;
444 reg-io-width = 452 reg-io-width = <4>;
445 453
446 #address-cells 454 #address-cells = <1>;
447 #size-cells = 455 #size-cells = <1>;
448 ranges = <0x0 456 ranges = <0x0 0x1e789000 0x1000>;
449 457
450 kcs1: kcs@24 { 458 kcs1: kcs@24 {
451 compat 459 compatible = "aspeed,ast2500-kcs-bmc-v2";
452 reg = 460 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
453 interr 461 interrupts = <8>;
454 clocks 462 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
455 status 463 status = "disabled";
456 }; 464 };
457 465
458 kcs2: kcs@28 { 466 kcs2: kcs@28 {
459 compat 467 compatible = "aspeed,ast2500-kcs-bmc-v2";
460 reg = 468 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
461 interr 469 interrupts = <8>;
462 clocks 470 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
463 status 471 status = "disabled";
464 }; 472 };
465 473
466 kcs3: kcs@2c { 474 kcs3: kcs@2c {
467 compat 475 compatible = "aspeed,ast2500-kcs-bmc-v2";
468 reg = 476 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
469 interr 477 interrupts = <8>;
470 clocks 478 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
471 status 479 status = "disabled";
472 }; 480 };
473 481
474 kcs4: kcs@114 482 kcs4: kcs@114 {
475 compat 483 compatible = "aspeed,ast2500-kcs-bmc-v2";
476 reg = 484 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
477 interr 485 interrupts = <8>;
478 clocks 486 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
479 status 487 status = "disabled";
480 }; 488 };
481 489
482 lpc_ctrl: lpc- 490 lpc_ctrl: lpc-ctrl@80 {
483 compat 491 compatible = "aspeed,ast2500-lpc-ctrl";
484 reg = 492 reg = <0x80 0x10>;
485 clocks 493 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
486 status 494 status = "disabled";
487 }; 495 };
488 496
489 lpc_snoop: lpc 497 lpc_snoop: lpc-snoop@90 {
490 compat 498 compatible = "aspeed,ast2500-lpc-snoop";
491 reg = 499 reg = <0x90 0x8>;
492 interr 500 interrupts = <8>;
493 clocks 501 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
494 status 502 status = "disabled";
495 }; 503 };
496 504
497 lpc_reset: res 505 lpc_reset: reset-controller@98 {
498 compat 506 compatible = "aspeed,ast2500-lpc-reset";
499 reg = 507 reg = <0x98 0x4>;
500 #reset 508 #reset-cells = <1>;
501 }; 509 };
502 510
503 uart_routing: 511 uart_routing: uart-routing@9c {
504 compat 512 compatible = "aspeed,ast2500-uart-routing";
505 reg = 513 reg = <0x9c 0x4>;
506 status 514 status = "disabled";
507 }; 515 };
508 516
509 lhc: lhc@a0 { 517 lhc: lhc@a0 {
510 compat 518 compatible = "aspeed,ast2500-lhc";
511 reg = 519 reg = <0xa0 0x24 0xc8 0x8>;
512 }; 520 };
513 521
514 522
515 ibt: ibt@140 { 523 ibt: ibt@140 {
516 compat 524 compatible = "aspeed,ast2500-ibt-bmc";
517 reg = 525 reg = <0x140 0x18>;
518 interr 526 interrupts = <8>;
519 clocks 527 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
520 status 528 status = "disabled";
521 }; 529 };
522 }; 530 };
523 531
524 peci0: peci-controller 532 peci0: peci-controller@1e78b000 {
525 compatible = " 533 compatible = "aspeed,ast2500-peci";
526 reg = <0x1e78b 534 reg = <0x1e78b000 0x60>;
527 interrupts = < 535 interrupts = <15>;
528 clocks = <&sys 536 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
529 resets = <&sys 537 resets = <&syscon ASPEED_RESET_PECI>;
530 cmd-timeout-ms 538 cmd-timeout-ms = <1000>;
531 clock-frequenc 539 clock-frequency = <1000000>;
532 status = "disa 540 status = "disabled";
533 }; 541 };
534 542
535 uart2: serial@1e78d000 543 uart2: serial@1e78d000 {
536 compatible = " 544 compatible = "ns16550a";
537 reg = <0x1e78d 545 reg = <0x1e78d000 0x20>;
538 reg-shift = <2 546 reg-shift = <2>;
539 interrupts = < 547 interrupts = <32>;
540 clocks = <&sys 548 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
541 resets = <&lpc 549 resets = <&lpc_reset 5>;
542 no-loopback-te 550 no-loopback-test;
543 status = "disa 551 status = "disabled";
544 }; 552 };
545 553
546 uart3: serial@1e78e000 554 uart3: serial@1e78e000 {
547 compatible = " 555 compatible = "ns16550a";
548 reg = <0x1e78e 556 reg = <0x1e78e000 0x20>;
549 reg-shift = <2 557 reg-shift = <2>;
550 interrupts = < 558 interrupts = <33>;
551 clocks = <&sys 559 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
552 resets = <&lpc 560 resets = <&lpc_reset 6>;
553 no-loopback-te 561 no-loopback-test;
554 status = "disa 562 status = "disabled";
555 }; 563 };
556 564
557 uart4: serial@1e78f000 565 uart4: serial@1e78f000 {
558 compatible = " 566 compatible = "ns16550a";
559 reg = <0x1e78f 567 reg = <0x1e78f000 0x20>;
560 reg-shift = <2 568 reg-shift = <2>;
561 interrupts = < 569 interrupts = <34>;
562 clocks = <&sys 570 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
563 resets = <&lpc 571 resets = <&lpc_reset 7>;
564 no-loopback-te 572 no-loopback-test;
565 status = "disa 573 status = "disabled";
566 }; 574 };
567 575
568 i2c: bus@1e78a000 { 576 i2c: bus@1e78a000 {
569 compatible = " 577 compatible = "simple-bus";
570 #address-cells 578 #address-cells = <1>;
571 #size-cells = 579 #size-cells = <1>;
572 ranges = <0 0x 580 ranges = <0 0x1e78a000 0x1000>;
573 }; 581 };
574 }; 582 };
575 }; 583 };
576 }; 584 };
577 585
578 &i2c { 586 &i2c {
579 i2c_ic: interrupt-controller@0 { 587 i2c_ic: interrupt-controller@0 {
580 #interrupt-cells = <1>; 588 #interrupt-cells = <1>;
581 compatible = "aspeed,ast2500-i 589 compatible = "aspeed,ast2500-i2c-ic";
582 reg = <0x0 0x40>; 590 reg = <0x0 0x40>;
583 interrupts = <12>; 591 interrupts = <12>;
584 interrupt-controller; 592 interrupt-controller;
585 }; 593 };
586 594
587 i2c0: i2c@40 { !! 595 i2c0: i2c-bus@40 {
588 #address-cells = <1>; 596 #address-cells = <1>;
589 #size-cells = <0>; 597 #size-cells = <0>;
590 598
591 reg = <0x40 0x40>; 599 reg = <0x40 0x40>;
592 compatible = "aspeed,ast2500-i 600 compatible = "aspeed,ast2500-i2c-bus";
593 clocks = <&syscon ASPEED_CLK_A 601 clocks = <&syscon ASPEED_CLK_APB>;
594 resets = <&syscon ASPEED_RESET 602 resets = <&syscon ASPEED_RESET_I2C>;
595 bus-frequency = <100000>; 603 bus-frequency = <100000>;
596 interrupts = <0>; 604 interrupts = <0>;
597 interrupt-parent = <&i2c_ic>; 605 interrupt-parent = <&i2c_ic>;
598 status = "disabled"; 606 status = "disabled";
599 /* Does not need pinctrl prope 607 /* Does not need pinctrl properties */
600 }; 608 };
601 609
602 i2c1: i2c@80 { !! 610 i2c1: i2c-bus@80 {
603 #address-cells = <1>; 611 #address-cells = <1>;
604 #size-cells = <0>; 612 #size-cells = <0>;
605 613
606 reg = <0x80 0x40>; 614 reg = <0x80 0x40>;
607 compatible = "aspeed,ast2500-i 615 compatible = "aspeed,ast2500-i2c-bus";
608 clocks = <&syscon ASPEED_CLK_A 616 clocks = <&syscon ASPEED_CLK_APB>;
609 resets = <&syscon ASPEED_RESET 617 resets = <&syscon ASPEED_RESET_I2C>;
610 bus-frequency = <100000>; 618 bus-frequency = <100000>;
611 interrupts = <1>; 619 interrupts = <1>;
612 interrupt-parent = <&i2c_ic>; 620 interrupt-parent = <&i2c_ic>;
613 status = "disabled"; 621 status = "disabled";
614 /* Does not need pinctrl prope 622 /* Does not need pinctrl properties */
615 }; 623 };
616 624
617 i2c2: i2c@c0 { !! 625 i2c2: i2c-bus@c0 {
618 #address-cells = <1>; 626 #address-cells = <1>;
619 #size-cells = <0>; 627 #size-cells = <0>;
620 628
621 reg = <0xc0 0x40>; 629 reg = <0xc0 0x40>;
622 compatible = "aspeed,ast2500-i 630 compatible = "aspeed,ast2500-i2c-bus";
623 clocks = <&syscon ASPEED_CLK_A 631 clocks = <&syscon ASPEED_CLK_APB>;
624 resets = <&syscon ASPEED_RESET 632 resets = <&syscon ASPEED_RESET_I2C>;
625 bus-frequency = <100000>; 633 bus-frequency = <100000>;
626 interrupts = <2>; 634 interrupts = <2>;
627 interrupt-parent = <&i2c_ic>; 635 interrupt-parent = <&i2c_ic>;
628 pinctrl-names = "default"; 636 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_i2c3_def 637 pinctrl-0 = <&pinctrl_i2c3_default>;
630 status = "disabled"; 638 status = "disabled";
631 }; 639 };
632 640
633 i2c3: i2c@100 { !! 641 i2c3: i2c-bus@100 {
634 #address-cells = <1>; 642 #address-cells = <1>;
635 #size-cells = <0>; 643 #size-cells = <0>;
636 644
637 reg = <0x100 0x40>; 645 reg = <0x100 0x40>;
638 compatible = "aspeed,ast2500-i 646 compatible = "aspeed,ast2500-i2c-bus";
639 clocks = <&syscon ASPEED_CLK_A 647 clocks = <&syscon ASPEED_CLK_APB>;
640 resets = <&syscon ASPEED_RESET 648 resets = <&syscon ASPEED_RESET_I2C>;
641 bus-frequency = <100000>; 649 bus-frequency = <100000>;
642 interrupts = <3>; 650 interrupts = <3>;
643 interrupt-parent = <&i2c_ic>; 651 interrupt-parent = <&i2c_ic>;
644 pinctrl-names = "default"; 652 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_i2c4_def 653 pinctrl-0 = <&pinctrl_i2c4_default>;
646 status = "disabled"; 654 status = "disabled";
647 }; 655 };
648 656
649 i2c4: i2c@140 { !! 657 i2c4: i2c-bus@140 {
650 #address-cells = <1>; 658 #address-cells = <1>;
651 #size-cells = <0>; 659 #size-cells = <0>;
652 660
653 reg = <0x140 0x40>; 661 reg = <0x140 0x40>;
654 compatible = "aspeed,ast2500-i 662 compatible = "aspeed,ast2500-i2c-bus";
655 clocks = <&syscon ASPEED_CLK_A 663 clocks = <&syscon ASPEED_CLK_APB>;
656 resets = <&syscon ASPEED_RESET 664 resets = <&syscon ASPEED_RESET_I2C>;
657 bus-frequency = <100000>; 665 bus-frequency = <100000>;
658 interrupts = <4>; 666 interrupts = <4>;
659 interrupt-parent = <&i2c_ic>; 667 interrupt-parent = <&i2c_ic>;
660 pinctrl-names = "default"; 668 pinctrl-names = "default";
661 pinctrl-0 = <&pinctrl_i2c5_def 669 pinctrl-0 = <&pinctrl_i2c5_default>;
662 status = "disabled"; 670 status = "disabled";
663 }; 671 };
664 672
665 i2c5: i2c@180 { !! 673 i2c5: i2c-bus@180 {
666 #address-cells = <1>; 674 #address-cells = <1>;
667 #size-cells = <0>; 675 #size-cells = <0>;
668 676
669 reg = <0x180 0x40>; 677 reg = <0x180 0x40>;
670 compatible = "aspeed,ast2500-i 678 compatible = "aspeed,ast2500-i2c-bus";
671 clocks = <&syscon ASPEED_CLK_A 679 clocks = <&syscon ASPEED_CLK_APB>;
672 resets = <&syscon ASPEED_RESET 680 resets = <&syscon ASPEED_RESET_I2C>;
673 bus-frequency = <100000>; 681 bus-frequency = <100000>;
674 interrupts = <5>; 682 interrupts = <5>;
675 interrupt-parent = <&i2c_ic>; 683 interrupt-parent = <&i2c_ic>;
676 pinctrl-names = "default"; 684 pinctrl-names = "default";
677 pinctrl-0 = <&pinctrl_i2c6_def 685 pinctrl-0 = <&pinctrl_i2c6_default>;
678 status = "disabled"; 686 status = "disabled";
679 }; 687 };
680 688
681 i2c6: i2c@1c0 { !! 689 i2c6: i2c-bus@1c0 {
682 #address-cells = <1>; 690 #address-cells = <1>;
683 #size-cells = <0>; 691 #size-cells = <0>;
684 692
685 reg = <0x1c0 0x40>; 693 reg = <0x1c0 0x40>;
686 compatible = "aspeed,ast2500-i 694 compatible = "aspeed,ast2500-i2c-bus";
687 clocks = <&syscon ASPEED_CLK_A 695 clocks = <&syscon ASPEED_CLK_APB>;
688 resets = <&syscon ASPEED_RESET 696 resets = <&syscon ASPEED_RESET_I2C>;
689 bus-frequency = <100000>; 697 bus-frequency = <100000>;
690 interrupts = <6>; 698 interrupts = <6>;
691 interrupt-parent = <&i2c_ic>; 699 interrupt-parent = <&i2c_ic>;
692 pinctrl-names = "default"; 700 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_i2c7_def 701 pinctrl-0 = <&pinctrl_i2c7_default>;
694 status = "disabled"; 702 status = "disabled";
695 }; 703 };
696 704
697 i2c7: i2c@300 { !! 705 i2c7: i2c-bus@300 {
698 #address-cells = <1>; 706 #address-cells = <1>;
699 #size-cells = <0>; 707 #size-cells = <0>;
700 708
701 reg = <0x300 0x40>; 709 reg = <0x300 0x40>;
702 compatible = "aspeed,ast2500-i 710 compatible = "aspeed,ast2500-i2c-bus";
703 clocks = <&syscon ASPEED_CLK_A 711 clocks = <&syscon ASPEED_CLK_APB>;
704 resets = <&syscon ASPEED_RESET 712 resets = <&syscon ASPEED_RESET_I2C>;
705 bus-frequency = <100000>; 713 bus-frequency = <100000>;
706 interrupts = <7>; 714 interrupts = <7>;
707 interrupt-parent = <&i2c_ic>; 715 interrupt-parent = <&i2c_ic>;
708 pinctrl-names = "default"; 716 pinctrl-names = "default";
709 pinctrl-0 = <&pinctrl_i2c8_def 717 pinctrl-0 = <&pinctrl_i2c8_default>;
710 status = "disabled"; 718 status = "disabled";
711 }; 719 };
712 720
713 i2c8: i2c@340 { !! 721 i2c8: i2c-bus@340 {
714 #address-cells = <1>; 722 #address-cells = <1>;
715 #size-cells = <0>; 723 #size-cells = <0>;
716 724
717 reg = <0x340 0x40>; 725 reg = <0x340 0x40>;
718 compatible = "aspeed,ast2500-i 726 compatible = "aspeed,ast2500-i2c-bus";
719 clocks = <&syscon ASPEED_CLK_A 727 clocks = <&syscon ASPEED_CLK_APB>;
720 resets = <&syscon ASPEED_RESET 728 resets = <&syscon ASPEED_RESET_I2C>;
721 bus-frequency = <100000>; 729 bus-frequency = <100000>;
722 interrupts = <8>; 730 interrupts = <8>;
723 interrupt-parent = <&i2c_ic>; 731 interrupt-parent = <&i2c_ic>;
724 pinctrl-names = "default"; 732 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_i2c9_def 733 pinctrl-0 = <&pinctrl_i2c9_default>;
726 status = "disabled"; 734 status = "disabled";
727 }; 735 };
728 736
729 i2c9: i2c@380 { !! 737 i2c9: i2c-bus@380 {
730 #address-cells = <1>; 738 #address-cells = <1>;
731 #size-cells = <0>; 739 #size-cells = <0>;
732 740
733 reg = <0x380 0x40>; 741 reg = <0x380 0x40>;
734 compatible = "aspeed,ast2500-i 742 compatible = "aspeed,ast2500-i2c-bus";
735 clocks = <&syscon ASPEED_CLK_A 743 clocks = <&syscon ASPEED_CLK_APB>;
736 resets = <&syscon ASPEED_RESET 744 resets = <&syscon ASPEED_RESET_I2C>;
737 bus-frequency = <100000>; 745 bus-frequency = <100000>;
738 interrupts = <9>; 746 interrupts = <9>;
739 interrupt-parent = <&i2c_ic>; 747 interrupt-parent = <&i2c_ic>;
740 pinctrl-names = "default"; 748 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_i2c10_de 749 pinctrl-0 = <&pinctrl_i2c10_default>;
742 status = "disabled"; 750 status = "disabled";
743 }; 751 };
744 752
745 i2c10: i2c@3c0 { !! 753 i2c10: i2c-bus@3c0 {
746 #address-cells = <1>; 754 #address-cells = <1>;
747 #size-cells = <0>; 755 #size-cells = <0>;
748 756
749 reg = <0x3c0 0x40>; 757 reg = <0x3c0 0x40>;
750 compatible = "aspeed,ast2500-i 758 compatible = "aspeed,ast2500-i2c-bus";
751 clocks = <&syscon ASPEED_CLK_A 759 clocks = <&syscon ASPEED_CLK_APB>;
752 resets = <&syscon ASPEED_RESET 760 resets = <&syscon ASPEED_RESET_I2C>;
753 bus-frequency = <100000>; 761 bus-frequency = <100000>;
754 interrupts = <10>; 762 interrupts = <10>;
755 interrupt-parent = <&i2c_ic>; 763 interrupt-parent = <&i2c_ic>;
756 pinctrl-names = "default"; 764 pinctrl-names = "default";
757 pinctrl-0 = <&pinctrl_i2c11_de 765 pinctrl-0 = <&pinctrl_i2c11_default>;
758 status = "disabled"; 766 status = "disabled";
759 }; 767 };
760 768
761 i2c11: i2c@400 { !! 769 i2c11: i2c-bus@400 {
762 #address-cells = <1>; 770 #address-cells = <1>;
763 #size-cells = <0>; 771 #size-cells = <0>;
764 772
765 reg = <0x400 0x40>; 773 reg = <0x400 0x40>;
766 compatible = "aspeed,ast2500-i 774 compatible = "aspeed,ast2500-i2c-bus";
767 clocks = <&syscon ASPEED_CLK_A 775 clocks = <&syscon ASPEED_CLK_APB>;
768 resets = <&syscon ASPEED_RESET 776 resets = <&syscon ASPEED_RESET_I2C>;
769 bus-frequency = <100000>; 777 bus-frequency = <100000>;
770 interrupts = <11>; 778 interrupts = <11>;
771 interrupt-parent = <&i2c_ic>; 779 interrupt-parent = <&i2c_ic>;
772 pinctrl-names = "default"; 780 pinctrl-names = "default";
773 pinctrl-0 = <&pinctrl_i2c12_de 781 pinctrl-0 = <&pinctrl_i2c12_default>;
774 status = "disabled"; 782 status = "disabled";
775 }; 783 };
776 784
777 i2c12: i2c@440 { !! 785 i2c12: i2c-bus@440 {
778 #address-cells = <1>; 786 #address-cells = <1>;
779 #size-cells = <0>; 787 #size-cells = <0>;
780 788
781 reg = <0x440 0x40>; 789 reg = <0x440 0x40>;
782 compatible = "aspeed,ast2500-i 790 compatible = "aspeed,ast2500-i2c-bus";
783 clocks = <&syscon ASPEED_CLK_A 791 clocks = <&syscon ASPEED_CLK_APB>;
784 resets = <&syscon ASPEED_RESET 792 resets = <&syscon ASPEED_RESET_I2C>;
785 bus-frequency = <100000>; 793 bus-frequency = <100000>;
786 interrupts = <12>; 794 interrupts = <12>;
787 interrupt-parent = <&i2c_ic>; 795 interrupt-parent = <&i2c_ic>;
788 pinctrl-names = "default"; 796 pinctrl-names = "default";
789 pinctrl-0 = <&pinctrl_i2c13_de 797 pinctrl-0 = <&pinctrl_i2c13_default>;
790 status = "disabled"; 798 status = "disabled";
791 }; 799 };
792 800
793 i2c13: i2c@480 { !! 801 i2c13: i2c-bus@480 {
794 #address-cells = <1>; 802 #address-cells = <1>;
795 #size-cells = <0>; 803 #size-cells = <0>;
796 804
797 reg = <0x480 0x40>; 805 reg = <0x480 0x40>;
798 compatible = "aspeed,ast2500-i 806 compatible = "aspeed,ast2500-i2c-bus";
799 clocks = <&syscon ASPEED_CLK_A 807 clocks = <&syscon ASPEED_CLK_APB>;
800 resets = <&syscon ASPEED_RESET 808 resets = <&syscon ASPEED_RESET_I2C>;
801 bus-frequency = <100000>; 809 bus-frequency = <100000>;
802 interrupts = <13>; 810 interrupts = <13>;
803 interrupt-parent = <&i2c_ic>; 811 interrupt-parent = <&i2c_ic>;
804 pinctrl-names = "default"; 812 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_i2c14_de 813 pinctrl-0 = <&pinctrl_i2c14_default>;
806 status = "disabled"; 814 status = "disabled";
807 }; 815 };
808 }; 816 };
809 817
810 &pinctrl { 818 &pinctrl {
811 pinctrl_acpi_default: acpi_default { 819 pinctrl_acpi_default: acpi_default {
812 function = "ACPI"; 820 function = "ACPI";
813 groups = "ACPI"; 821 groups = "ACPI";
814 }; 822 };
815 823
816 pinctrl_adc0_default: adc0_default { 824 pinctrl_adc0_default: adc0_default {
817 function = "ADC0"; 825 function = "ADC0";
818 groups = "ADC0"; 826 groups = "ADC0";
819 }; 827 };
820 828
821 pinctrl_adc1_default: adc1_default { 829 pinctrl_adc1_default: adc1_default {
822 function = "ADC1"; 830 function = "ADC1";
823 groups = "ADC1"; 831 groups = "ADC1";
824 }; 832 };
825 833
826 pinctrl_adc10_default: adc10_default { 834 pinctrl_adc10_default: adc10_default {
827 function = "ADC10"; 835 function = "ADC10";
828 groups = "ADC10"; 836 groups = "ADC10";
829 }; 837 };
830 838
831 pinctrl_adc11_default: adc11_default { 839 pinctrl_adc11_default: adc11_default {
832 function = "ADC11"; 840 function = "ADC11";
833 groups = "ADC11"; 841 groups = "ADC11";
834 }; 842 };
835 843
836 pinctrl_adc12_default: adc12_default { 844 pinctrl_adc12_default: adc12_default {
837 function = "ADC12"; 845 function = "ADC12";
838 groups = "ADC12"; 846 groups = "ADC12";
839 }; 847 };
840 848
841 pinctrl_adc13_default: adc13_default { 849 pinctrl_adc13_default: adc13_default {
842 function = "ADC13"; 850 function = "ADC13";
843 groups = "ADC13"; 851 groups = "ADC13";
844 }; 852 };
845 853
846 pinctrl_adc14_default: adc14_default { 854 pinctrl_adc14_default: adc14_default {
847 function = "ADC14"; 855 function = "ADC14";
848 groups = "ADC14"; 856 groups = "ADC14";
849 }; 857 };
850 858
851 pinctrl_adc15_default: adc15_default { 859 pinctrl_adc15_default: adc15_default {
852 function = "ADC15"; 860 function = "ADC15";
853 groups = "ADC15"; 861 groups = "ADC15";
854 }; 862 };
855 863
856 pinctrl_adc2_default: adc2_default { 864 pinctrl_adc2_default: adc2_default {
857 function = "ADC2"; 865 function = "ADC2";
858 groups = "ADC2"; 866 groups = "ADC2";
859 }; 867 };
860 868
861 pinctrl_adc3_default: adc3_default { 869 pinctrl_adc3_default: adc3_default {
862 function = "ADC3"; 870 function = "ADC3";
863 groups = "ADC3"; 871 groups = "ADC3";
864 }; 872 };
865 873
866 pinctrl_adc4_default: adc4_default { 874 pinctrl_adc4_default: adc4_default {
867 function = "ADC4"; 875 function = "ADC4";
868 groups = "ADC4"; 876 groups = "ADC4";
869 }; 877 };
870 878
871 pinctrl_adc5_default: adc5_default { 879 pinctrl_adc5_default: adc5_default {
872 function = "ADC5"; 880 function = "ADC5";
873 groups = "ADC5"; 881 groups = "ADC5";
874 }; 882 };
875 883
876 pinctrl_adc6_default: adc6_default { 884 pinctrl_adc6_default: adc6_default {
877 function = "ADC6"; 885 function = "ADC6";
878 groups = "ADC6"; 886 groups = "ADC6";
879 }; 887 };
880 888
881 pinctrl_adc7_default: adc7_default { 889 pinctrl_adc7_default: adc7_default {
882 function = "ADC7"; 890 function = "ADC7";
883 groups = "ADC7"; 891 groups = "ADC7";
884 }; 892 };
885 893
886 pinctrl_adc8_default: adc8_default { 894 pinctrl_adc8_default: adc8_default {
887 function = "ADC8"; 895 function = "ADC8";
888 groups = "ADC8"; 896 groups = "ADC8";
889 }; 897 };
890 898
891 pinctrl_adc9_default: adc9_default { 899 pinctrl_adc9_default: adc9_default {
892 function = "ADC9"; 900 function = "ADC9";
893 groups = "ADC9"; 901 groups = "ADC9";
894 }; 902 };
895 903
896 pinctrl_bmcint_default: bmcint_default 904 pinctrl_bmcint_default: bmcint_default {
897 function = "BMCINT"; 905 function = "BMCINT";
898 groups = "BMCINT"; 906 groups = "BMCINT";
899 }; 907 };
900 908
901 pinctrl_ddcclk_default: ddcclk_default 909 pinctrl_ddcclk_default: ddcclk_default {
902 function = "DDCCLK"; 910 function = "DDCCLK";
903 groups = "DDCCLK"; 911 groups = "DDCCLK";
904 }; 912 };
905 913
906 pinctrl_ddcdat_default: ddcdat_default 914 pinctrl_ddcdat_default: ddcdat_default {
907 function = "DDCDAT"; 915 function = "DDCDAT";
908 groups = "DDCDAT"; 916 groups = "DDCDAT";
909 }; 917 };
910 918
911 pinctrl_espi_default: espi_default { 919 pinctrl_espi_default: espi_default {
912 function = "ESPI"; 920 function = "ESPI";
913 groups = "ESPI"; 921 groups = "ESPI";
914 }; 922 };
915 923
916 pinctrl_fwspics1_default: fwspics1_def 924 pinctrl_fwspics1_default: fwspics1_default {
917 function = "FWSPICS1"; 925 function = "FWSPICS1";
918 groups = "FWSPICS1"; 926 groups = "FWSPICS1";
919 }; 927 };
920 928
921 pinctrl_fwspics2_default: fwspics2_def 929 pinctrl_fwspics2_default: fwspics2_default {
922 function = "FWSPICS2"; 930 function = "FWSPICS2";
923 groups = "FWSPICS2"; 931 groups = "FWSPICS2";
924 }; 932 };
925 933
926 pinctrl_gpid0_default: gpid0_default { 934 pinctrl_gpid0_default: gpid0_default {
927 function = "GPID0"; 935 function = "GPID0";
928 groups = "GPID0"; 936 groups = "GPID0";
929 }; 937 };
930 938
931 pinctrl_gpid2_default: gpid2_default { 939 pinctrl_gpid2_default: gpid2_default {
932 function = "GPID2"; 940 function = "GPID2";
933 groups = "GPID2"; 941 groups = "GPID2";
934 }; 942 };
935 943
936 pinctrl_gpid4_default: gpid4_default { 944 pinctrl_gpid4_default: gpid4_default {
937 function = "GPID4"; 945 function = "GPID4";
938 groups = "GPID4"; 946 groups = "GPID4";
939 }; 947 };
940 948
941 pinctrl_gpid6_default: gpid6_default { 949 pinctrl_gpid6_default: gpid6_default {
942 function = "GPID6"; 950 function = "GPID6";
943 groups = "GPID6"; 951 groups = "GPID6";
944 }; 952 };
945 953
946 pinctrl_gpie0_default: gpie0_default { 954 pinctrl_gpie0_default: gpie0_default {
947 function = "GPIE0"; 955 function = "GPIE0";
948 groups = "GPIE0"; 956 groups = "GPIE0";
949 }; 957 };
950 958
951 pinctrl_gpie2_default: gpie2_default { 959 pinctrl_gpie2_default: gpie2_default {
952 function = "GPIE2"; 960 function = "GPIE2";
953 groups = "GPIE2"; 961 groups = "GPIE2";
954 }; 962 };
955 963
956 pinctrl_gpie4_default: gpie4_default { 964 pinctrl_gpie4_default: gpie4_default {
957 function = "GPIE4"; 965 function = "GPIE4";
958 groups = "GPIE4"; 966 groups = "GPIE4";
959 }; 967 };
960 968
961 pinctrl_gpie6_default: gpie6_default { 969 pinctrl_gpie6_default: gpie6_default {
962 function = "GPIE6"; 970 function = "GPIE6";
963 groups = "GPIE6"; 971 groups = "GPIE6";
964 }; 972 };
965 973
966 pinctrl_i2c10_default: i2c10_default { 974 pinctrl_i2c10_default: i2c10_default {
967 function = "I2C10"; 975 function = "I2C10";
968 groups = "I2C10"; 976 groups = "I2C10";
969 }; 977 };
970 978
971 pinctrl_i2c11_default: i2c11_default { 979 pinctrl_i2c11_default: i2c11_default {
972 function = "I2C11"; 980 function = "I2C11";
973 groups = "I2C11"; 981 groups = "I2C11";
974 }; 982 };
975 983
976 pinctrl_i2c12_default: i2c12_default { 984 pinctrl_i2c12_default: i2c12_default {
977 function = "I2C12"; 985 function = "I2C12";
978 groups = "I2C12"; 986 groups = "I2C12";
979 }; 987 };
980 988
981 pinctrl_i2c13_default: i2c13_default { 989 pinctrl_i2c13_default: i2c13_default {
982 function = "I2C13"; 990 function = "I2C13";
983 groups = "I2C13"; 991 groups = "I2C13";
984 }; 992 };
985 993
986 pinctrl_i2c14_default: i2c14_default { 994 pinctrl_i2c14_default: i2c14_default {
987 function = "I2C14"; 995 function = "I2C14";
988 groups = "I2C14"; 996 groups = "I2C14";
989 }; 997 };
990 998
991 pinctrl_i2c3_default: i2c3_default { 999 pinctrl_i2c3_default: i2c3_default {
992 function = "I2C3"; 1000 function = "I2C3";
993 groups = "I2C3"; 1001 groups = "I2C3";
994 }; 1002 };
995 1003
996 pinctrl_i2c4_default: i2c4_default { 1004 pinctrl_i2c4_default: i2c4_default {
997 function = "I2C4"; 1005 function = "I2C4";
998 groups = "I2C4"; 1006 groups = "I2C4";
999 }; 1007 };
1000 1008
1001 pinctrl_i2c5_default: i2c5_default { 1009 pinctrl_i2c5_default: i2c5_default {
1002 function = "I2C5"; 1010 function = "I2C5";
1003 groups = "I2C5"; 1011 groups = "I2C5";
1004 }; 1012 };
1005 1013
1006 pinctrl_i2c6_default: i2c6_default { 1014 pinctrl_i2c6_default: i2c6_default {
1007 function = "I2C6"; 1015 function = "I2C6";
1008 groups = "I2C6"; 1016 groups = "I2C6";
1009 }; 1017 };
1010 1018
1011 pinctrl_i2c7_default: i2c7_default { 1019 pinctrl_i2c7_default: i2c7_default {
1012 function = "I2C7"; 1020 function = "I2C7";
1013 groups = "I2C7"; 1021 groups = "I2C7";
1014 }; 1022 };
1015 1023
1016 pinctrl_i2c8_default: i2c8_default { 1024 pinctrl_i2c8_default: i2c8_default {
1017 function = "I2C8"; 1025 function = "I2C8";
1018 groups = "I2C8"; 1026 groups = "I2C8";
1019 }; 1027 };
1020 1028
1021 pinctrl_i2c9_default: i2c9_default { 1029 pinctrl_i2c9_default: i2c9_default {
1022 function = "I2C9"; 1030 function = "I2C9";
1023 groups = "I2C9"; 1031 groups = "I2C9";
1024 }; 1032 };
1025 1033
1026 pinctrl_lad0_default: lad0_default { 1034 pinctrl_lad0_default: lad0_default {
1027 function = "LAD0"; 1035 function = "LAD0";
1028 groups = "LAD0"; 1036 groups = "LAD0";
1029 }; 1037 };
1030 1038
1031 pinctrl_lad1_default: lad1_default { 1039 pinctrl_lad1_default: lad1_default {
1032 function = "LAD1"; 1040 function = "LAD1";
1033 groups = "LAD1"; 1041 groups = "LAD1";
1034 }; 1042 };
1035 1043
1036 pinctrl_lad2_default: lad2_default { 1044 pinctrl_lad2_default: lad2_default {
1037 function = "LAD2"; 1045 function = "LAD2";
1038 groups = "LAD2"; 1046 groups = "LAD2";
1039 }; 1047 };
1040 1048
1041 pinctrl_lad3_default: lad3_default { 1049 pinctrl_lad3_default: lad3_default {
1042 function = "LAD3"; 1050 function = "LAD3";
1043 groups = "LAD3"; 1051 groups = "LAD3";
1044 }; 1052 };
1045 1053
1046 pinctrl_lclk_default: lclk_default { 1054 pinctrl_lclk_default: lclk_default {
1047 function = "LCLK"; 1055 function = "LCLK";
1048 groups = "LCLK"; 1056 groups = "LCLK";
1049 }; 1057 };
1050 1058
1051 pinctrl_lframe_default: lframe_defaul 1059 pinctrl_lframe_default: lframe_default {
1052 function = "LFRAME"; 1060 function = "LFRAME";
1053 groups = "LFRAME"; 1061 groups = "LFRAME";
1054 }; 1062 };
1055 1063
1056 pinctrl_lpchc_default: lpchc_default 1064 pinctrl_lpchc_default: lpchc_default {
1057 function = "LPCHC"; 1065 function = "LPCHC";
1058 groups = "LPCHC"; 1066 groups = "LPCHC";
1059 }; 1067 };
1060 1068
1061 pinctrl_lpcpd_default: lpcpd_default 1069 pinctrl_lpcpd_default: lpcpd_default {
1062 function = "LPCPD"; 1070 function = "LPCPD";
1063 groups = "LPCPD"; 1071 groups = "LPCPD";
1064 }; 1072 };
1065 1073
1066 pinctrl_lpcplus_default: lpcplus_defa 1074 pinctrl_lpcplus_default: lpcplus_default {
1067 function = "LPCPLUS"; 1075 function = "LPCPLUS";
1068 groups = "LPCPLUS"; 1076 groups = "LPCPLUS";
1069 }; 1077 };
1070 1078
1071 pinctrl_lpcpme_default: lpcpme_defaul 1079 pinctrl_lpcpme_default: lpcpme_default {
1072 function = "LPCPME"; 1080 function = "LPCPME";
1073 groups = "LPCPME"; 1081 groups = "LPCPME";
1074 }; 1082 };
1075 1083
1076 pinctrl_lpcrst_default: lpcrst_defaul 1084 pinctrl_lpcrst_default: lpcrst_default {
1077 function = "LPCRST"; 1085 function = "LPCRST";
1078 groups = "LPCRST"; 1086 groups = "LPCRST";
1079 }; 1087 };
1080 1088
1081 pinctrl_lpcsmi_default: lpcsmi_defaul 1089 pinctrl_lpcsmi_default: lpcsmi_default {
1082 function = "LPCSMI"; 1090 function = "LPCSMI";
1083 groups = "LPCSMI"; 1091 groups = "LPCSMI";
1084 }; 1092 };
1085 1093
1086 pinctrl_lsirq_default: lsirq_default 1094 pinctrl_lsirq_default: lsirq_default {
1087 function = "LSIRQ"; 1095 function = "LSIRQ";
1088 groups = "LSIRQ"; 1096 groups = "LSIRQ";
1089 }; 1097 };
1090 1098
1091 pinctrl_mac1link_default: mac1link_de 1099 pinctrl_mac1link_default: mac1link_default {
1092 function = "MAC1LINK"; 1100 function = "MAC1LINK";
1093 groups = "MAC1LINK"; 1101 groups = "MAC1LINK";
1094 }; 1102 };
1095 1103
1096 pinctrl_mac2link_default: mac2link_de 1104 pinctrl_mac2link_default: mac2link_default {
1097 function = "MAC2LINK"; 1105 function = "MAC2LINK";
1098 groups = "MAC2LINK"; 1106 groups = "MAC2LINK";
1099 }; 1107 };
1100 1108
1101 pinctrl_mdio1_default: mdio1_default 1109 pinctrl_mdio1_default: mdio1_default {
1102 function = "MDIO1"; 1110 function = "MDIO1";
1103 groups = "MDIO1"; 1111 groups = "MDIO1";
1104 }; 1112 };
1105 1113
1106 pinctrl_mdio2_default: mdio2_default 1114 pinctrl_mdio2_default: mdio2_default {
1107 function = "MDIO2"; 1115 function = "MDIO2";
1108 groups = "MDIO2"; 1116 groups = "MDIO2";
1109 }; 1117 };
1110 1118
1111 pinctrl_ncts1_default: ncts1_default 1119 pinctrl_ncts1_default: ncts1_default {
1112 function = "NCTS1"; 1120 function = "NCTS1";
1113 groups = "NCTS1"; 1121 groups = "NCTS1";
1114 }; 1122 };
1115 1123
1116 pinctrl_ncts2_default: ncts2_default 1124 pinctrl_ncts2_default: ncts2_default {
1117 function = "NCTS2"; 1125 function = "NCTS2";
1118 groups = "NCTS2"; 1126 groups = "NCTS2";
1119 }; 1127 };
1120 1128
1121 pinctrl_ncts3_default: ncts3_default 1129 pinctrl_ncts3_default: ncts3_default {
1122 function = "NCTS3"; 1130 function = "NCTS3";
1123 groups = "NCTS3"; 1131 groups = "NCTS3";
1124 }; 1132 };
1125 1133
1126 pinctrl_ncts4_default: ncts4_default 1134 pinctrl_ncts4_default: ncts4_default {
1127 function = "NCTS4"; 1135 function = "NCTS4";
1128 groups = "NCTS4"; 1136 groups = "NCTS4";
1129 }; 1137 };
1130 1138
1131 pinctrl_ndcd1_default: ndcd1_default 1139 pinctrl_ndcd1_default: ndcd1_default {
1132 function = "NDCD1"; 1140 function = "NDCD1";
1133 groups = "NDCD1"; 1141 groups = "NDCD1";
1134 }; 1142 };
1135 1143
1136 pinctrl_ndcd2_default: ndcd2_default 1144 pinctrl_ndcd2_default: ndcd2_default {
1137 function = "NDCD2"; 1145 function = "NDCD2";
1138 groups = "NDCD2"; 1146 groups = "NDCD2";
1139 }; 1147 };
1140 1148
1141 pinctrl_ndcd3_default: ndcd3_default 1149 pinctrl_ndcd3_default: ndcd3_default {
1142 function = "NDCD3"; 1150 function = "NDCD3";
1143 groups = "NDCD3"; 1151 groups = "NDCD3";
1144 }; 1152 };
1145 1153
1146 pinctrl_ndcd4_default: ndcd4_default 1154 pinctrl_ndcd4_default: ndcd4_default {
1147 function = "NDCD4"; 1155 function = "NDCD4";
1148 groups = "NDCD4"; 1156 groups = "NDCD4";
1149 }; 1157 };
1150 1158
1151 pinctrl_ndsr1_default: ndsr1_default 1159 pinctrl_ndsr1_default: ndsr1_default {
1152 function = "NDSR1"; 1160 function = "NDSR1";
1153 groups = "NDSR1"; 1161 groups = "NDSR1";
1154 }; 1162 };
1155 1163
1156 pinctrl_ndsr2_default: ndsr2_default 1164 pinctrl_ndsr2_default: ndsr2_default {
1157 function = "NDSR2"; 1165 function = "NDSR2";
1158 groups = "NDSR2"; 1166 groups = "NDSR2";
1159 }; 1167 };
1160 1168
1161 pinctrl_ndsr3_default: ndsr3_default 1169 pinctrl_ndsr3_default: ndsr3_default {
1162 function = "NDSR3"; 1170 function = "NDSR3";
1163 groups = "NDSR3"; 1171 groups = "NDSR3";
1164 }; 1172 };
1165 1173
1166 pinctrl_ndsr4_default: ndsr4_default 1174 pinctrl_ndsr4_default: ndsr4_default {
1167 function = "NDSR4"; 1175 function = "NDSR4";
1168 groups = "NDSR4"; 1176 groups = "NDSR4";
1169 }; 1177 };
1170 1178
1171 pinctrl_ndtr1_default: ndtr1_default 1179 pinctrl_ndtr1_default: ndtr1_default {
1172 function = "NDTR1"; 1180 function = "NDTR1";
1173 groups = "NDTR1"; 1181 groups = "NDTR1";
1174 }; 1182 };
1175 1183
1176 pinctrl_ndtr2_default: ndtr2_default 1184 pinctrl_ndtr2_default: ndtr2_default {
1177 function = "NDTR2"; 1185 function = "NDTR2";
1178 groups = "NDTR2"; 1186 groups = "NDTR2";
1179 }; 1187 };
1180 1188
1181 pinctrl_ndtr3_default: ndtr3_default 1189 pinctrl_ndtr3_default: ndtr3_default {
1182 function = "NDTR3"; 1190 function = "NDTR3";
1183 groups = "NDTR3"; 1191 groups = "NDTR3";
1184 }; 1192 };
1185 1193
1186 pinctrl_ndtr4_default: ndtr4_default 1194 pinctrl_ndtr4_default: ndtr4_default {
1187 function = "NDTR4"; 1195 function = "NDTR4";
1188 groups = "NDTR4"; 1196 groups = "NDTR4";
1189 }; 1197 };
1190 1198
1191 pinctrl_nri1_default: nri1_default { 1199 pinctrl_nri1_default: nri1_default {
1192 function = "NRI1"; 1200 function = "NRI1";
1193 groups = "NRI1"; 1201 groups = "NRI1";
1194 }; 1202 };
1195 1203
1196 pinctrl_nri2_default: nri2_default { 1204 pinctrl_nri2_default: nri2_default {
1197 function = "NRI2"; 1205 function = "NRI2";
1198 groups = "NRI2"; 1206 groups = "NRI2";
1199 }; 1207 };
1200 1208
1201 pinctrl_nri3_default: nri3_default { 1209 pinctrl_nri3_default: nri3_default {
1202 function = "NRI3"; 1210 function = "NRI3";
1203 groups = "NRI3"; 1211 groups = "NRI3";
1204 }; 1212 };
1205 1213
1206 pinctrl_nri4_default: nri4_default { 1214 pinctrl_nri4_default: nri4_default {
1207 function = "NRI4"; 1215 function = "NRI4";
1208 groups = "NRI4"; 1216 groups = "NRI4";
1209 }; 1217 };
1210 1218
1211 pinctrl_nrts1_default: nrts1_default 1219 pinctrl_nrts1_default: nrts1_default {
1212 function = "NRTS1"; 1220 function = "NRTS1";
1213 groups = "NRTS1"; 1221 groups = "NRTS1";
1214 }; 1222 };
1215 1223
1216 pinctrl_nrts2_default: nrts2_default 1224 pinctrl_nrts2_default: nrts2_default {
1217 function = "NRTS2"; 1225 function = "NRTS2";
1218 groups = "NRTS2"; 1226 groups = "NRTS2";
1219 }; 1227 };
1220 1228
1221 pinctrl_nrts3_default: nrts3_default 1229 pinctrl_nrts3_default: nrts3_default {
1222 function = "NRTS3"; 1230 function = "NRTS3";
1223 groups = "NRTS3"; 1231 groups = "NRTS3";
1224 }; 1232 };
1225 1233
1226 pinctrl_nrts4_default: nrts4_default 1234 pinctrl_nrts4_default: nrts4_default {
1227 function = "NRTS4"; 1235 function = "NRTS4";
1228 groups = "NRTS4"; 1236 groups = "NRTS4";
1229 }; 1237 };
1230 1238
1231 pinctrl_oscclk_default: oscclk_defaul 1239 pinctrl_oscclk_default: oscclk_default {
1232 function = "OSCCLK"; 1240 function = "OSCCLK";
1233 groups = "OSCCLK"; 1241 groups = "OSCCLK";
1234 }; 1242 };
1235 1243
1236 pinctrl_pewake_default: pewake_defaul 1244 pinctrl_pewake_default: pewake_default {
1237 function = "PEWAKE"; 1245 function = "PEWAKE";
1238 groups = "PEWAKE"; 1246 groups = "PEWAKE";
1239 }; 1247 };
1240 1248
1241 pinctrl_pnor_default: pnor_default { 1249 pinctrl_pnor_default: pnor_default {
1242 function = "PNOR"; 1250 function = "PNOR";
1243 groups = "PNOR"; 1251 groups = "PNOR";
1244 }; 1252 };
1245 1253
1246 pinctrl_pwm0_default: pwm0_default { 1254 pinctrl_pwm0_default: pwm0_default {
1247 function = "PWM0"; 1255 function = "PWM0";
1248 groups = "PWM0"; 1256 groups = "PWM0";
1249 }; 1257 };
1250 1258
1251 pinctrl_pwm1_default: pwm1_default { 1259 pinctrl_pwm1_default: pwm1_default {
1252 function = "PWM1"; 1260 function = "PWM1";
1253 groups = "PWM1"; 1261 groups = "PWM1";
1254 }; 1262 };
1255 1263
1256 pinctrl_pwm2_default: pwm2_default { 1264 pinctrl_pwm2_default: pwm2_default {
1257 function = "PWM2"; 1265 function = "PWM2";
1258 groups = "PWM2"; 1266 groups = "PWM2";
1259 }; 1267 };
1260 1268
1261 pinctrl_pwm3_default: pwm3_default { 1269 pinctrl_pwm3_default: pwm3_default {
1262 function = "PWM3"; 1270 function = "PWM3";
1263 groups = "PWM3"; 1271 groups = "PWM3";
1264 }; 1272 };
1265 1273
1266 pinctrl_pwm4_default: pwm4_default { 1274 pinctrl_pwm4_default: pwm4_default {
1267 function = "PWM4"; 1275 function = "PWM4";
1268 groups = "PWM4"; 1276 groups = "PWM4";
1269 }; 1277 };
1270 1278
1271 pinctrl_pwm5_default: pwm5_default { 1279 pinctrl_pwm5_default: pwm5_default {
1272 function = "PWM5"; 1280 function = "PWM5";
1273 groups = "PWM5"; 1281 groups = "PWM5";
1274 }; 1282 };
1275 1283
1276 pinctrl_pwm6_default: pwm6_default { 1284 pinctrl_pwm6_default: pwm6_default {
1277 function = "PWM6"; 1285 function = "PWM6";
1278 groups = "PWM6"; 1286 groups = "PWM6";
1279 }; 1287 };
1280 1288
1281 pinctrl_pwm7_default: pwm7_default { 1289 pinctrl_pwm7_default: pwm7_default {
1282 function = "PWM7"; 1290 function = "PWM7";
1283 groups = "PWM7"; 1291 groups = "PWM7";
1284 }; 1292 };
1285 1293
1286 pinctrl_rgmii1_default: rgmii1_defaul 1294 pinctrl_rgmii1_default: rgmii1_default {
1287 function = "RGMII1"; 1295 function = "RGMII1";
1288 groups = "RGMII1"; 1296 groups = "RGMII1";
1289 }; 1297 };
1290 1298
1291 pinctrl_rgmii2_default: rgmii2_defaul 1299 pinctrl_rgmii2_default: rgmii2_default {
1292 function = "RGMII2"; 1300 function = "RGMII2";
1293 groups = "RGMII2"; 1301 groups = "RGMII2";
1294 }; 1302 };
1295 1303
1296 pinctrl_rmii1_default: rmii1_default 1304 pinctrl_rmii1_default: rmii1_default {
1297 function = "RMII1"; 1305 function = "RMII1";
1298 groups = "RMII1"; 1306 groups = "RMII1";
1299 }; 1307 };
1300 1308
1301 pinctrl_rmii2_default: rmii2_default 1309 pinctrl_rmii2_default: rmii2_default {
1302 function = "RMII2"; 1310 function = "RMII2";
1303 groups = "RMII2"; 1311 groups = "RMII2";
1304 }; 1312 };
1305 1313
1306 pinctrl_rxd1_default: rxd1_default { 1314 pinctrl_rxd1_default: rxd1_default {
1307 function = "RXD1"; 1315 function = "RXD1";
1308 groups = "RXD1"; 1316 groups = "RXD1";
1309 }; 1317 };
1310 1318
1311 pinctrl_rxd2_default: rxd2_default { 1319 pinctrl_rxd2_default: rxd2_default {
1312 function = "RXD2"; 1320 function = "RXD2";
1313 groups = "RXD2"; 1321 groups = "RXD2";
1314 }; 1322 };
1315 1323
1316 pinctrl_rxd3_default: rxd3_default { 1324 pinctrl_rxd3_default: rxd3_default {
1317 function = "RXD3"; 1325 function = "RXD3";
1318 groups = "RXD3"; 1326 groups = "RXD3";
1319 }; 1327 };
1320 1328
1321 pinctrl_rxd4_default: rxd4_default { 1329 pinctrl_rxd4_default: rxd4_default {
1322 function = "RXD4"; 1330 function = "RXD4";
1323 groups = "RXD4"; 1331 groups = "RXD4";
1324 }; 1332 };
1325 1333
1326 pinctrl_salt1_default: salt1_default 1334 pinctrl_salt1_default: salt1_default {
1327 function = "SALT1"; 1335 function = "SALT1";
1328 groups = "SALT1"; 1336 groups = "SALT1";
1329 }; 1337 };
1330 1338
1331 pinctrl_salt10_default: salt10_defaul 1339 pinctrl_salt10_default: salt10_default {
1332 function = "SALT10"; 1340 function = "SALT10";
1333 groups = "SALT10"; 1341 groups = "SALT10";
1334 }; 1342 };
1335 1343
1336 pinctrl_salt11_default: salt11_defaul 1344 pinctrl_salt11_default: salt11_default {
1337 function = "SALT11"; 1345 function = "SALT11";
1338 groups = "SALT11"; 1346 groups = "SALT11";
1339 }; 1347 };
1340 1348
1341 pinctrl_salt12_default: salt12_defaul 1349 pinctrl_salt12_default: salt12_default {
1342 function = "SALT12"; 1350 function = "SALT12";
1343 groups = "SALT12"; 1351 groups = "SALT12";
1344 }; 1352 };
1345 1353
1346 pinctrl_salt13_default: salt13_defaul 1354 pinctrl_salt13_default: salt13_default {
1347 function = "SALT13"; 1355 function = "SALT13";
1348 groups = "SALT13"; 1356 groups = "SALT13";
1349 }; 1357 };
1350 1358
1351 pinctrl_salt14_default: salt14_defaul 1359 pinctrl_salt14_default: salt14_default {
1352 function = "SALT14"; 1360 function = "SALT14";
1353 groups = "SALT14"; 1361 groups = "SALT14";
1354 }; 1362 };
1355 1363
1356 pinctrl_salt2_default: salt2_default 1364 pinctrl_salt2_default: salt2_default {
1357 function = "SALT2"; 1365 function = "SALT2";
1358 groups = "SALT2"; 1366 groups = "SALT2";
1359 }; 1367 };
1360 1368
1361 pinctrl_salt3_default: salt3_default 1369 pinctrl_salt3_default: salt3_default {
1362 function = "SALT3"; 1370 function = "SALT3";
1363 groups = "SALT3"; 1371 groups = "SALT3";
1364 }; 1372 };
1365 1373
1366 pinctrl_salt4_default: salt4_default 1374 pinctrl_salt4_default: salt4_default {
1367 function = "SALT4"; 1375 function = "SALT4";
1368 groups = "SALT4"; 1376 groups = "SALT4";
1369 }; 1377 };
1370 1378
1371 pinctrl_salt5_default: salt5_default 1379 pinctrl_salt5_default: salt5_default {
1372 function = "SALT5"; 1380 function = "SALT5";
1373 groups = "SALT5"; 1381 groups = "SALT5";
1374 }; 1382 };
1375 1383
1376 pinctrl_salt6_default: salt6_default 1384 pinctrl_salt6_default: salt6_default {
1377 function = "SALT6"; 1385 function = "SALT6";
1378 groups = "SALT6"; 1386 groups = "SALT6";
1379 }; 1387 };
1380 1388
1381 pinctrl_salt7_default: salt7_default 1389 pinctrl_salt7_default: salt7_default {
1382 function = "SALT7"; 1390 function = "SALT7";
1383 groups = "SALT7"; 1391 groups = "SALT7";
1384 }; 1392 };
1385 1393
1386 pinctrl_salt8_default: salt8_default 1394 pinctrl_salt8_default: salt8_default {
1387 function = "SALT8"; 1395 function = "SALT8";
1388 groups = "SALT8"; 1396 groups = "SALT8";
1389 }; 1397 };
1390 1398
1391 pinctrl_salt9_default: salt9_default 1399 pinctrl_salt9_default: salt9_default {
1392 function = "SALT9"; 1400 function = "SALT9";
1393 groups = "SALT9"; 1401 groups = "SALT9";
1394 }; 1402 };
1395 1403
1396 pinctrl_scl1_default: scl1_default { 1404 pinctrl_scl1_default: scl1_default {
1397 function = "SCL1"; 1405 function = "SCL1";
1398 groups = "SCL1"; 1406 groups = "SCL1";
1399 }; 1407 };
1400 1408
1401 pinctrl_scl2_default: scl2_default { 1409 pinctrl_scl2_default: scl2_default {
1402 function = "SCL2"; 1410 function = "SCL2";
1403 groups = "SCL2"; 1411 groups = "SCL2";
1404 }; 1412 };
1405 1413
1406 pinctrl_sd1_default: sd1_default { 1414 pinctrl_sd1_default: sd1_default {
1407 function = "SD1"; 1415 function = "SD1";
1408 groups = "SD1"; 1416 groups = "SD1";
1409 }; 1417 };
1410 1418
1411 pinctrl_sd2_default: sd2_default { 1419 pinctrl_sd2_default: sd2_default {
1412 function = "SD2"; 1420 function = "SD2";
1413 groups = "SD2"; 1421 groups = "SD2";
1414 }; 1422 };
1415 1423
1416 pinctrl_sda1_default: sda1_default { 1424 pinctrl_sda1_default: sda1_default {
1417 function = "SDA1"; 1425 function = "SDA1";
1418 groups = "SDA1"; 1426 groups = "SDA1";
1419 }; 1427 };
1420 1428
1421 pinctrl_sda2_default: sda2_default { 1429 pinctrl_sda2_default: sda2_default {
1422 function = "SDA2"; 1430 function = "SDA2";
1423 groups = "SDA2"; 1431 groups = "SDA2";
1424 }; 1432 };
1425 1433
1426 pinctrl_sgpm_default: sgpm_default { 1434 pinctrl_sgpm_default: sgpm_default {
1427 function = "SGPM"; 1435 function = "SGPM";
1428 groups = "SGPM"; 1436 groups = "SGPM";
1429 }; 1437 };
1430 1438
1431 pinctrl_sgps1_default: sgps1_default 1439 pinctrl_sgps1_default: sgps1_default {
1432 function = "SGPS1"; 1440 function = "SGPS1";
1433 groups = "SGPS1"; 1441 groups = "SGPS1";
1434 }; 1442 };
1435 1443
1436 pinctrl_sgps2_default: sgps2_default 1444 pinctrl_sgps2_default: sgps2_default {
1437 function = "SGPS2"; 1445 function = "SGPS2";
1438 groups = "SGPS2"; 1446 groups = "SGPS2";
1439 }; 1447 };
1440 1448
1441 pinctrl_sioonctrl_default: sioonctrl_ 1449 pinctrl_sioonctrl_default: sioonctrl_default {
1442 function = "SIOONCTRL"; 1450 function = "SIOONCTRL";
1443 groups = "SIOONCTRL"; 1451 groups = "SIOONCTRL";
1444 }; 1452 };
1445 1453
1446 pinctrl_siopbi_default: siopbi_defaul 1454 pinctrl_siopbi_default: siopbi_default {
1447 function = "SIOPBI"; 1455 function = "SIOPBI";
1448 groups = "SIOPBI"; 1456 groups = "SIOPBI";
1449 }; 1457 };
1450 1458
1451 pinctrl_siopbo_default: siopbo_defaul 1459 pinctrl_siopbo_default: siopbo_default {
1452 function = "SIOPBO"; 1460 function = "SIOPBO";
1453 groups = "SIOPBO"; 1461 groups = "SIOPBO";
1454 }; 1462 };
1455 1463
1456 pinctrl_siopwreq_default: siopwreq_de 1464 pinctrl_siopwreq_default: siopwreq_default {
1457 function = "SIOPWREQ"; 1465 function = "SIOPWREQ";
1458 groups = "SIOPWREQ"; 1466 groups = "SIOPWREQ";
1459 }; 1467 };
1460 1468
1461 pinctrl_siopwrgd_default: siopwrgd_de 1469 pinctrl_siopwrgd_default: siopwrgd_default {
1462 function = "SIOPWRGD"; 1470 function = "SIOPWRGD";
1463 groups = "SIOPWRGD"; 1471 groups = "SIOPWRGD";
1464 }; 1472 };
1465 1473
1466 pinctrl_sios3_default: sios3_default 1474 pinctrl_sios3_default: sios3_default {
1467 function = "SIOS3"; 1475 function = "SIOS3";
1468 groups = "SIOS3"; 1476 groups = "SIOS3";
1469 }; 1477 };
1470 1478
1471 pinctrl_sios5_default: sios5_default 1479 pinctrl_sios5_default: sios5_default {
1472 function = "SIOS5"; 1480 function = "SIOS5";
1473 groups = "SIOS5"; 1481 groups = "SIOS5";
1474 }; 1482 };
1475 1483
1476 pinctrl_siosci_default: siosci_defaul 1484 pinctrl_siosci_default: siosci_default {
1477 function = "SIOSCI"; 1485 function = "SIOSCI";
1478 groups = "SIOSCI"; 1486 groups = "SIOSCI";
1479 }; 1487 };
1480 1488
1481 pinctrl_spi1_default: spi1_default { 1489 pinctrl_spi1_default: spi1_default {
1482 function = "SPI1"; 1490 function = "SPI1";
1483 groups = "SPI1"; 1491 groups = "SPI1";
1484 }; 1492 };
1485 1493
1486 pinctrl_spi1cs1_default: spi1cs1_defa 1494 pinctrl_spi1cs1_default: spi1cs1_default {
1487 function = "SPI1CS1"; 1495 function = "SPI1CS1";
1488 groups = "SPI1CS1"; 1496 groups = "SPI1CS1";
1489 }; 1497 };
1490 1498
1491 pinctrl_spi1debug_default: spi1debug_ 1499 pinctrl_spi1debug_default: spi1debug_default {
1492 function = "SPI1DEBUG"; 1500 function = "SPI1DEBUG";
1493 groups = "SPI1DEBUG"; 1501 groups = "SPI1DEBUG";
1494 }; 1502 };
1495 1503
1496 pinctrl_spi1passthru_default: spi1pas 1504 pinctrl_spi1passthru_default: spi1passthru_default {
1497 function = "SPI1PASSTHRU"; 1505 function = "SPI1PASSTHRU";
1498 groups = "SPI1PASSTHRU"; 1506 groups = "SPI1PASSTHRU";
1499 }; 1507 };
1500 1508
1501 pinctrl_spi2ck_default: spi2ck_defaul 1509 pinctrl_spi2ck_default: spi2ck_default {
1502 function = "SPI2CK"; 1510 function = "SPI2CK";
1503 groups = "SPI2CK"; 1511 groups = "SPI2CK";
1504 }; 1512 };
1505 1513
1506 pinctrl_spi2cs0_default: spi2cs0_defa 1514 pinctrl_spi2cs0_default: spi2cs0_default {
1507 function = "SPI2CS0"; 1515 function = "SPI2CS0";
1508 groups = "SPI2CS0"; 1516 groups = "SPI2CS0";
1509 }; 1517 };
1510 1518
1511 pinctrl_spi2cs1_default: spi2cs1_defa 1519 pinctrl_spi2cs1_default: spi2cs1_default {
1512 function = "SPI2CS1"; 1520 function = "SPI2CS1";
1513 groups = "SPI2CS1"; 1521 groups = "SPI2CS1";
1514 }; 1522 };
1515 1523
1516 pinctrl_spi2miso_default: spi2miso_de 1524 pinctrl_spi2miso_default: spi2miso_default {
1517 function = "SPI2MISO"; 1525 function = "SPI2MISO";
1518 groups = "SPI2MISO"; 1526 groups = "SPI2MISO";
1519 }; 1527 };
1520 1528
1521 pinctrl_spi2mosi_default: spi2mosi_de 1529 pinctrl_spi2mosi_default: spi2mosi_default {
1522 function = "SPI2MOSI"; 1530 function = "SPI2MOSI";
1523 groups = "SPI2MOSI"; 1531 groups = "SPI2MOSI";
1524 }; 1532 };
1525 1533
1526 pinctrl_timer3_default: timer3_defaul 1534 pinctrl_timer3_default: timer3_default {
1527 function = "TIMER3"; 1535 function = "TIMER3";
1528 groups = "TIMER3"; 1536 groups = "TIMER3";
1529 }; 1537 };
1530 1538
1531 pinctrl_timer4_default: timer4_defaul 1539 pinctrl_timer4_default: timer4_default {
1532 function = "TIMER4"; 1540 function = "TIMER4";
1533 groups = "TIMER4"; 1541 groups = "TIMER4";
1534 }; 1542 };
1535 1543
1536 pinctrl_timer5_default: timer5_defaul 1544 pinctrl_timer5_default: timer5_default {
1537 function = "TIMER5"; 1545 function = "TIMER5";
1538 groups = "TIMER5"; 1546 groups = "TIMER5";
1539 }; 1547 };
1540 1548
1541 pinctrl_timer6_default: timer6_defaul 1549 pinctrl_timer6_default: timer6_default {
1542 function = "TIMER6"; 1550 function = "TIMER6";
1543 groups = "TIMER6"; 1551 groups = "TIMER6";
1544 }; 1552 };
1545 1553
1546 pinctrl_timer7_default: timer7_defaul 1554 pinctrl_timer7_default: timer7_default {
1547 function = "TIMER7"; 1555 function = "TIMER7";
1548 groups = "TIMER7"; 1556 groups = "TIMER7";
1549 }; 1557 };
1550 1558
1551 pinctrl_timer8_default: timer8_defaul 1559 pinctrl_timer8_default: timer8_default {
1552 function = "TIMER8"; 1560 function = "TIMER8";
1553 groups = "TIMER8"; 1561 groups = "TIMER8";
1554 }; 1562 };
1555 1563
1556 pinctrl_txd1_default: txd1_default { 1564 pinctrl_txd1_default: txd1_default {
1557 function = "TXD1"; 1565 function = "TXD1";
1558 groups = "TXD1"; 1566 groups = "TXD1";
1559 }; 1567 };
1560 1568
1561 pinctrl_txd2_default: txd2_default { 1569 pinctrl_txd2_default: txd2_default {
1562 function = "TXD2"; 1570 function = "TXD2";
1563 groups = "TXD2"; 1571 groups = "TXD2";
1564 }; 1572 };
1565 1573
1566 pinctrl_txd3_default: txd3_default { 1574 pinctrl_txd3_default: txd3_default {
1567 function = "TXD3"; 1575 function = "TXD3";
1568 groups = "TXD3"; 1576 groups = "TXD3";
1569 }; 1577 };
1570 1578
1571 pinctrl_txd4_default: txd4_default { 1579 pinctrl_txd4_default: txd4_default {
1572 function = "TXD4"; 1580 function = "TXD4";
1573 groups = "TXD4"; 1581 groups = "TXD4";
1574 }; 1582 };
1575 1583
1576 pinctrl_uart6_default: uart6_default 1584 pinctrl_uart6_default: uart6_default {
1577 function = "UART6"; 1585 function = "UART6";
1578 groups = "UART6"; 1586 groups = "UART6";
1579 }; 1587 };
1580 1588
1581 pinctrl_usbcki_default: usbcki_defaul 1589 pinctrl_usbcki_default: usbcki_default {
1582 function = "USBCKI"; 1590 function = "USBCKI";
1583 groups = "USBCKI"; 1591 groups = "USBCKI";
1584 }; 1592 };
1585 1593
1586 pinctrl_usb2ah_default: usb2ah_defaul 1594 pinctrl_usb2ah_default: usb2ah_default {
1587 function = "USB2AH"; 1595 function = "USB2AH";
1588 groups = "USB2AH"; 1596 groups = "USB2AH";
1589 }; 1597 };
1590 1598
1591 pinctrl_usb2ad_default: usb2ad_defaul 1599 pinctrl_usb2ad_default: usb2ad_default {
1592 function = "USB2AD"; 1600 function = "USB2AD";
1593 groups = "USB2AD"; 1601 groups = "USB2AD";
1594 }; 1602 };
1595 1603
1596 pinctrl_usb11bhid_default: usb11bhid_ 1604 pinctrl_usb11bhid_default: usb11bhid_default {
1597 function = "USB11BHID"; 1605 function = "USB11BHID";
1598 groups = "USB11BHID"; 1606 groups = "USB11BHID";
1599 }; 1607 };
1600 1608
1601 pinctrl_usb2bh_default: usb2bh_defaul 1609 pinctrl_usb2bh_default: usb2bh_default {
1602 function = "USB2BH"; 1610 function = "USB2BH";
1603 groups = "USB2BH"; 1611 groups = "USB2BH";
1604 }; 1612 };
1605 1613
1606 pinctrl_vgabiosrom_default: vgabiosro 1614 pinctrl_vgabiosrom_default: vgabiosrom_default {
1607 function = "VGABIOSROM"; 1615 function = "VGABIOSROM";
1608 groups = "VGABIOSROM"; 1616 groups = "VGABIOSROM";
1609 }; 1617 };
1610 1618
1611 pinctrl_vgahs_default: vgahs_default 1619 pinctrl_vgahs_default: vgahs_default {
1612 function = "VGAHS"; 1620 function = "VGAHS";
1613 groups = "VGAHS"; 1621 groups = "VGAHS";
1614 }; 1622 };
1615 1623
1616 pinctrl_vgavs_default: vgavs_default 1624 pinctrl_vgavs_default: vgavs_default {
1617 function = "VGAVS"; 1625 function = "VGAVS";
1618 groups = "VGAVS"; 1626 groups = "VGAVS";
1619 }; 1627 };
1620 1628
1621 pinctrl_vpi24_default: vpi24_default 1629 pinctrl_vpi24_default: vpi24_default {
1622 function = "VPI24"; 1630 function = "VPI24";
1623 groups = "VPI24"; 1631 groups = "VPI24";
1624 }; 1632 };
1625 1633
1626 pinctrl_vpo_default: vpo_default { 1634 pinctrl_vpo_default: vpo_default {
1627 function = "VPO"; 1635 function = "VPO";
1628 groups = "VPO"; 1636 groups = "VPO";
1629 }; 1637 };
1630 1638
1631 pinctrl_wdtrst1_default: wdtrst1_defa 1639 pinctrl_wdtrst1_default: wdtrst1_default {
1632 function = "WDTRST1"; 1640 function = "WDTRST1";
1633 groups = "WDTRST1"; 1641 groups = "WDTRST1";
1634 }; 1642 };
1635 1643
1636 pinctrl_wdtrst2_default: wdtrst2_defa 1644 pinctrl_wdtrst2_default: wdtrst2_default {
1637 function = "WDTRST2"; 1645 function = "WDTRST2";
1638 groups = "WDTRST2"; 1646 groups = "WDTRST2";
1639 }; 1647 };
1640 }; 1648 };
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