1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. A
5 *
6 * Redistribution and use in source and binar
7 * modification, are permitted provided that
8 * are met:
9 *
10 * * Redistributions of source code must re
11 * notice, this list of conditions and th
12 * * Redistributions in binary form must re
13 * notice, this list of conditions and th
14 * the documentation and/or other materia
15 * distribution.
16 * * Neither the name of Broadcom Corporati
17 * contributors may be used to endorse or
18 * from this software without specific pr
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE PO
31 */
32
33 #include <dt-bindings/interrupt-controller/arm
34 #include <dt-bindings/interrupt-controller/irq
35 #include <dt-bindings/clock/bcm-cygnus.h>
36
37 / {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,cygnus";
41 model = "Broadcom Cygnus SoC";
42 interrupt-parent = <&gic>;
43
44 aliases {
45 ethernet0 = ð0;
46 };
47
48 memory@0 {
49 device_type = "memory";
50 reg = <0 0>;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cort
60 next-level-cache = <&L
61 reg = <0x0>;
62 };
63 };
64
65 /include/ "bcm-cygnus-clock.dtsi"
66
67 pmu {
68 compatible = "arm,cortex-a9-pm
69 interrupts = <GIC_SPI 8 IRQ_TY
70 };
71
72 core@19000000 {
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x1900000
75 #address-cells = <1>;
76 #size-cells = <1>;
77
78 timer@20200 {
79 compatible = "arm,cort
80 reg = <0x20200 0x100>;
81 interrupts = <GIC_PPI
82 clocks = <&periph_clk>
83 };
84
85 gic: interrupt-controller@2100
86 compatible = "arm,cort
87 #interrupt-cells = <3>
88 #address-cells = <0>;
89 interrupt-controller;
90 reg = <0x21000 0x1000>
91 <0x20100 0x100>;
92 };
93
94 L2: cache-controller@22000 {
95 compatible = "arm,pl31
96 reg = <0x22000 0x1000>
97 cache-unified;
98 cache-level = <2>;
99 };
100 };
101
102 axi {
103 compatible = "simple-bus";
104 ranges;
105 #address-cells = <1>;
106 #size-cells = <1>;
107
108 otp: otp@301c800 {
109 compatible = "brcm,oco
110 reg = <0x0301c800 0x2c
111 brcm,ocotp-size = <204
112 status = "disabled";
113 };
114
115 pcie_phy: pcie_phy@301d0a0 {
116 compatible = "brcm,cyg
117 reg = <0x0301d0a0 0x14
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 pcie0_phy: pcie-phy@0
122 reg = <0>;
123 #phy-cells = <
124 };
125
126 pcie1_phy: pcie-phy@1
127 reg = <1>;
128 #phy-cells = <
129 };
130 };
131
132 pinctrl: pinctrl@301d0c8 {
133 compatible = "brcm,cyg
134 reg = <0x0301d0c8 0x30
135 <0x0301d24c 0x2c
136
137 spi_0: spi_0 {
138 function = "sp
139 groups = "spi0
140 };
141
142 spi_1: spi_1 {
143 function = "sp
144 groups = "spi1
145 };
146
147 spi_2: spi_2 {
148 function = "sp
149 groups = "spi2
150 };
151 };
152
153 mailbox: mailbox@3024024 {
154 compatible = "brcm,ipr
155 reg = <0x03024024 0x40
156 interrupts = <GIC_SPI
157 #interrupt-cells = <1>
158 interrupt-controller;
159 #mbox-cells = <1>;
160 };
161
162 gpio_crmu: gpio@3024800 {
163 compatible = "brcm,cyg
164 reg = <0x03024800 0x50
165 <0x03024008 0x18
166 ngpios = <6>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 interrupt-controller;
170 #interrupt-cells = <2>
171 interrupt-parent = <&m
172 interrupts = <0>;
173 };
174
175 mdio: mdio@18002000 {
176 compatible = "brcm,ipr
177 reg = <0x18002000 0x8>
178 #size-cells = <0>;
179 #address-cells = <1>;
180 status = "disabled";
181
182 gphy0: ethernet-phy@0
183 reg = <0>;
184 };
185
186 gphy1: ethernet-phy@1
187 reg = <1>;
188 };
189 };
190
191 switch: switch@18007000 {
192 compatible = "brcm,bcm
193 reg = <0x18007000 0x10
194 status = "disabled";
195
196 ports {
197 #address-cells
198 #size-cells =
199
200 port@0 {
201 reg =
202 phy-ha
203 phy-mo
204 };
205
206 port@1 {
207 reg =
208 phy-ha
209 phy-mo
210 };
211
212 port@8 {
213 reg =
214 label
215 ethern
216 fixed-
217
218
219 };
220 };
221 };
222 };
223
224 i2c0: i2c@18008000 {
225 compatible = "brcm,cyg
226 reg = <0x18008000 0x10
227 #address-cells = <1>;
228 #size-cells = <0>;
229 interrupts = <GIC_SPI
230 clock-frequency = <100
231 status = "disabled";
232 };
233
234 wdt0: wdt@18009000 {
235 compatible = "arm,sp80
236 reg = <0x18009000 0x10
237 interrupts = <GIC_SPI
238 clocks = <&axi81_clk>,
239 clock-names = "wdog_cl
240 };
241
242 gpio_ccm: gpio@1800a000 {
243 compatible = "brcm,cyg
244 reg = <0x1800a000 0x50
245 <0x0301d164 0x20
246 ngpios = <24>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 interrupts = <GIC_SPI
250 interrupt-controller;
251 #interrupt-cells = <2>
252 };
253
254 i2c1: i2c@1800b000 {
255 compatible = "brcm,cyg
256 reg = <0x1800b000 0x10
257 #address-cells = <1>;
258 #size-cells = <0>;
259 interrupts = <GIC_SPI
260 clock-frequency = <100
261 status = "disabled";
262 };
263
264 pcie0: pcie@18012000 {
265 compatible = "brcm,ipr
266 reg = <0x18012000 0x10
267
268 #interrupt-cells = <1>
269 interrupt-map-mask = <
270 interrupt-map = <0 0 0
271
272 linux,pci-domain = <0>
273
274 bus-range = <0x00 0xff
275
276 #address-cells = <3>;
277 #size-cells = <2>;
278 device_type = "pci";
279 ranges = <0x81000000 0
280 <0x82000000 0
281
282 phys = <&pcie0_phy>;
283 phy-names = "pcie-phy"
284
285 status = "disabled";
286
287 msi-parent = <&msi0>;
288 msi0: msi {
289 compatible = "
290 msi-controller
291 interrupt-pare
292 interrupts = <
293 <
294 <
295 <
296 };
297 };
298
299 pcie1: pcie@18013000 {
300 compatible = "brcm,ipr
301 reg = <0x18013000 0x10
302
303 #interrupt-cells = <1>
304 interrupt-map-mask = <
305 interrupt-map = <0 0 0
306
307 linux,pci-domain = <1>
308
309 bus-range = <0x00 0xff
310
311 #address-cells = <3>;
312 #size-cells = <2>;
313 device_type = "pci";
314 ranges = <0x81000000 0
315 <0x82000000 0
316
317 phys = <&pcie1_phy>;
318 phy-names = "pcie-phy"
319
320 status = "disabled";
321
322 msi-parent = <&msi1>;
323 msi1: msi {
324 compatible = "
325 msi-controller
326 interrupt-pare
327 interrupts = <
328 <
329 <
330 <
331 };
332 };
333
334 dma0: dma@18018000 {
335 compatible = "arm,pl33
336 reg = <0x18018000 0x10
337 interrupts = <GIC_SPI
338 <GIC_SPI
339 <GIC_SPI
340 <GIC_SPI
341 <GIC_SPI
342 <GIC_SPI
343 <GIC_SPI
344 <GIC_SPI
345 <GIC_SPI
346 clocks = <&apb_clk>;
347 clock-names = "apb_pcl
348 #dma-cells = <1>;
349 };
350
351 uart0: serial@18020000 {
352 compatible = "snps,dw-
353 reg = <0x18020000 0x10
354 reg-shift = <2>;
355 reg-io-width = <4>;
356 interrupts = <GIC_SPI
357 clocks = <&axi81_clk>;
358 clock-frequency = <100
359 status = "disabled";
360 };
361
362 uart1: serial@18021000 {
363 compatible = "snps,dw-
364 reg = <0x18021000 0x10
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 interrupts = <GIC_SPI
368 clocks = <&axi81_clk>;
369 clock-frequency = <100
370 status = "disabled";
371 };
372
373 uart2: serial@18022000 {
374 compatible = "snps,dw-
375 reg = <0x18022000 0x10
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 interrupts = <GIC_SPI
379 clocks = <&axi81_clk>;
380 clock-frequency = <100
381 status = "disabled";
382 };
383
384 uart3: serial@18023000 {
385 compatible = "snps,dw-
386 reg = <0x18023000 0x10
387 reg-shift = <2>;
388 reg-io-width = <4>;
389 interrupts = <GIC_SPI
390 clocks = <&axi81_clk>;
391 clock-frequency = <100
392 status = "disabled";
393 };
394
395 spi0: spi@18028000 {
396 compatible = "arm,pl02
397 reg = <0x18028000 0x10
398 #address-cells = <1>;
399 #size-cells = <0>;
400 interrupts = <GIC_SPI
401 pinctrl-0 = <&spi_0>;
402 clocks = <&axi81_clk>,
403 clock-names = "sspclk"
404 status = "disabled";
405 };
406
407 spi1: spi@18029000 {
408 compatible = "arm,pl02
409 reg = <0x18029000 0x10
410 #address-cells = <1>;
411 #size-cells = <0>;
412 interrupts = <GIC_SPI
413 pinctrl-0 = <&spi_1>;
414 clocks = <&axi81_clk>,
415 clock-names = "sspclk"
416 status = "disabled";
417 };
418
419 spi2: spi@1802a000 {
420 compatible = "arm,pl02
421 reg = <0x1802a000 0x10
422 #address-cells = <1>;
423 #size-cells = <0>;
424 interrupts = <GIC_SPI
425 pinctrl-0 = <&spi_2>;
426 clocks = <&axi81_clk>,
427 clock-names = "sspclk"
428 status = "disabled";
429 };
430
431 rng: rng@18032000 {
432 compatible = "brcm,ipr
433 reg = <0x18032000 0x28
434 };
435
436 sdhci0: sdhci@18041000 {
437 compatible = "brcm,sdh
438 reg = <0x18041000 0x10
439 interrupts = <GIC_SPI
440 clocks = <&lcpll0 BCM_
441 bus-width = <4>;
442 sdhci,auto-cmd12;
443 status = "disabled";
444 };
445
446 eth0: ethernet@18042000 {
447 compatible = "brcm,ama
448 reg = <0x18042000 0x10
449 <0x18110000 0x10
450 reg-names = "amac_base
451 interrupts = <GIC_SPI
452 status = "disabled";
453 };
454
455 sdhci1: sdhci@18043000 {
456 compatible = "brcm,sdh
457 reg = <0x18043000 0x10
458 interrupts = <GIC_SPI
459 clocks = <&lcpll0 BCM_
460 bus-width = <4>;
461 sdhci,auto-cmd12;
462 status = "disabled";
463 };
464
465 nand_controller: nand-controll
466 compatible = "brcm,nan
467 reg = <0x18046000 0x60
468 <0x18046f00 0x20
469 reg-names = "nand", "i
470 interrupts = <GIC_SPI
471
472 #address-cells = <1>;
473 #size-cells = <0>;
474
475 brcm,nand-has-wp;
476 };
477
478 ehci0: usb@18048000 {
479 compatible = "generic-
480 reg = <0x18048000 0x10
481 interrupts = <GIC_SPI
482 status = "disabled";
483 };
484
485 ohci0: usb@18048800 {
486 compatible = "generic-
487 reg = <0x18048800 0x10
488 interrupts = <GIC_SPI
489 status = "disabled";
490 };
491
492 clcd: clcd@180a0000 {
493 compatible = "arm,pl11
494 reg = <0x180a0000 0x10
495 interrupts = <GIC_SPI
496 interrupt-names = "com
497 clocks = <&axi41_clk>,
498 clock-names = "clcdclk
499 status = "disabled";
500 };
501
502 v3d: v3d@180a2000 {
503 compatible = "brcm,cyg
504 reg = <0x180a2000 0x10
505 clocks = <&mipipll BCM
506 clock-names = "v3d_clk
507 interrupts = <GIC_SPI
508 status = "disabled";
509 };
510
511 vc4: gpu {
512 compatible = "brcm,cyg
513 };
514
515 gpio_asiu: gpio@180a5000 {
516 compatible = "brcm,cyg
517 reg = <0x180a5000 0x66
518 ngpios = <146>;
519 #gpio-cells = <2>;
520 gpio-controller;
521
522 interrupt-controller;
523 #interrupt-cells = <2>
524 interrupts = <GIC_SPI
525 gpio-ranges = <&pinctr
526 <&pinc
527 <&pinc
528 <&pinc
529 <&pinc
530 <&pinc
531 <&pinc
532 <&pinc
533 <&pinc
534 <&pinc
535 <&pinc
536 <&pinc
537 <&pinc
538 <&pinc
539 <&pinc
540 <&pinc
541 <&pinc
542 <&pinc
543 <&pinc
544 <&pinc
545 <&pinc
546 <&pinc
547 <&pinc
548 <&pinc
549 <&pinc
550 <&pinc
551 <&pinc
552 <&pinc
553 <&pinc
554 <&pinc
555 <&pinc
556 <&pinc
557 <&pinc
558 <&pinc
559 <&pinc
560 <&pinc
561 <&pinc
562 <&pinc
563 <&pinc
564 <&pinc
565 <&pinc
566 <&pinc
567 <&pinc
568 <&pinc
569 <&pinc
570 <&pinc
571 <&pinc
572 <&pinc
573 <&pinc
574 <&pinc
575 <&pinc
576 };
577
578 ts_adc_syscon: ts_adc_syscon@1
579 compatible = "brcm,ipr
580 reg = <0x180a6000 0xc3
581 };
582
583 touchscreen: touchscreen@180a6
584 compatible = "brcm,ipr
585 #address-cells = <1>;
586 #size-cells = <1>;
587 ts_syscon = <&ts_adc_s
588 clocks = <&asiu_clks B
589 clock-names = "tsc_clk
590 interrupts = <GIC_SPI
591 status = "disabled";
592 };
593
594 adc: adc@180a6000 {
595 compatible = "brcm,ipr
596 #io-channel-cells = <1
597 adc-syscon = <&ts_adc_
598 clocks = <&asiu_clks B
599 clock-names = "tsc_clk
600 interrupts = <GIC_SPI
601 status = "disabled";
602 };
603
604 pwm: pwm@180aa500 {
605 compatible = "brcm,kon
606 reg = <0x180aa500 0xc4
607 #pwm-cells = <3>;
608 clocks = <&asiu_clks B
609 status = "disabled";
610 };
611
612 keypad: keypad@180ac000 {
613 compatible = "brcm,bcm
614 reg = <0x180ac000 0x14
615 interrupts = <GIC_SPI
616 clocks = <&asiu_clks B
617 clock-names = "peri_cl
618 clock-frequency = <312
619 pull-up-enabled;
620 col-debounce-filter-pe
621 status-debounce-filter
622 row-output-enabled;
623 status = "disabled";
624 };
625 };
626 };
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