1 /* 1 /*
2 * BSD LICENSE 2 * BSD LICENSE
3 * 3 *
4 * Copyright(c) 2014 Broadcom Corporation. A 4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binar 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 9 *
10 * * Redistributions of source code must re 10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and th 11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must re 12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and th 13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materia 14 * the documentation and/or other materials provided with the
15 * distribution. 15 * distribution.
16 * * Neither the name of Broadcom Corporati 16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or 17 * contributors may be used to endorse or promote products derived
18 * from this software without specific pr 18 * from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE PO 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33 #include <dt-bindings/interrupt-controller/arm 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq 34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h> 35 #include <dt-bindings/clock/bcm-cygnus.h>
36 36
37 / { 37 / {
38 #address-cells = <1>; 38 #address-cells = <1>;
39 #size-cells = <1>; 39 #size-cells = <1>;
40 compatible = "brcm,cygnus"; 40 compatible = "brcm,cygnus";
41 model = "Broadcom Cygnus SoC"; 41 model = "Broadcom Cygnus SoC";
42 interrupt-parent = <&gic>; 42 interrupt-parent = <&gic>;
43 43
44 aliases { 44 aliases {
45 ethernet0 = ð0; 45 ethernet0 = ð0;
46 }; 46 };
47 47
48 memory@0 { 48 memory@0 {
49 device_type = "memory"; 49 device_type = "memory";
50 reg = <0 0>; 50 reg = <0 0>;
51 }; 51 };
52 52
53 cpus { 53 cpus {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 56
57 cpu@0 { 57 cpu@0 {
58 device_type = "cpu"; 58 device_type = "cpu";
59 compatible = "arm,cort 59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L 60 next-level-cache = <&L2>;
61 reg = <0x0>; 61 reg = <0x0>;
62 }; 62 };
63 }; 63 };
64 64
65 /include/ "bcm-cygnus-clock.dtsi" 65 /include/ "bcm-cygnus-clock.dtsi"
66 66
67 pmu { 67 pmu {
68 compatible = "arm,cortex-a9-pm 68 compatible = "arm,cortex-a9-pmu";
69 interrupts = <GIC_SPI 8 IRQ_TY 69 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
70 }; 70 };
71 71
72 core@19000000 { 72 core@19000000 {
73 compatible = "simple-bus"; 73 compatible = "simple-bus";
74 ranges = <0x00000000 0x1900000 74 ranges = <0x00000000 0x19000000 0x1000000>;
75 #address-cells = <1>; 75 #address-cells = <1>;
76 #size-cells = <1>; 76 #size-cells = <1>;
77 77
78 timer@20200 { 78 timer@20200 {
79 compatible = "arm,cort 79 compatible = "arm,cortex-a9-global-timer";
80 reg = <0x20200 0x100>; 80 reg = <0x20200 0x100>;
81 interrupts = <GIC_PPI 81 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
82 clocks = <&periph_clk> 82 clocks = <&periph_clk>;
83 }; 83 };
84 84
85 gic: interrupt-controller@2100 85 gic: interrupt-controller@21000 {
86 compatible = "arm,cort 86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3> 87 #interrupt-cells = <3>;
88 #address-cells = <0>; 88 #address-cells = <0>;
89 interrupt-controller; 89 interrupt-controller;
90 reg = <0x21000 0x1000> 90 reg = <0x21000 0x1000>,
91 <0x20100 0x100>; 91 <0x20100 0x100>;
92 }; 92 };
93 93
94 L2: cache-controller@22000 { 94 L2: cache-controller@22000 {
95 compatible = "arm,pl31 95 compatible = "arm,pl310-cache";
96 reg = <0x22000 0x1000> 96 reg = <0x22000 0x1000>;
97 cache-unified; 97 cache-unified;
98 cache-level = <2>; 98 cache-level = <2>;
99 }; 99 };
100 }; 100 };
101 101
102 axi { 102 axi {
103 compatible = "simple-bus"; 103 compatible = "simple-bus";
104 ranges; 104 ranges;
105 #address-cells = <1>; 105 #address-cells = <1>;
106 #size-cells = <1>; 106 #size-cells = <1>;
107 107
108 otp: otp@301c800 { 108 otp: otp@301c800 {
109 compatible = "brcm,oco 109 compatible = "brcm,ocotp";
110 reg = <0x0301c800 0x2c 110 reg = <0x0301c800 0x2c>;
111 brcm,ocotp-size = <204 111 brcm,ocotp-size = <2048>;
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 114
115 pcie_phy: pcie_phy@301d0a0 { 115 pcie_phy: pcie_phy@301d0a0 {
116 compatible = "brcm,cyg 116 compatible = "brcm,cygnus-pcie-phy";
117 reg = <0x0301d0a0 0x14 117 reg = <0x0301d0a0 0x14>;
118 #address-cells = <1>; 118 #address-cells = <1>;
119 #size-cells = <0>; 119 #size-cells = <0>;
120 120
121 pcie0_phy: pcie-phy@0 121 pcie0_phy: pcie-phy@0 {
122 reg = <0>; 122 reg = <0>;
123 #phy-cells = < 123 #phy-cells = <0>;
124 }; 124 };
125 125
126 pcie1_phy: pcie-phy@1 126 pcie1_phy: pcie-phy@1 {
127 reg = <1>; 127 reg = <1>;
128 #phy-cells = < 128 #phy-cells = <0>;
129 }; 129 };
130 }; 130 };
131 131
132 pinctrl: pinctrl@301d0c8 { 132 pinctrl: pinctrl@301d0c8 {
133 compatible = "brcm,cyg 133 compatible = "brcm,cygnus-pinmux";
134 reg = <0x0301d0c8 0x30 134 reg = <0x0301d0c8 0x30>,
135 <0x0301d24c 0x2c 135 <0x0301d24c 0x2c>;
136 136
137 spi_0: spi_0 { 137 spi_0: spi_0 {
138 function = "sp 138 function = "spi0";
139 groups = "spi0 139 groups = "spi0_grp";
140 }; 140 };
141 141
142 spi_1: spi_1 { 142 spi_1: spi_1 {
143 function = "sp 143 function = "spi1";
144 groups = "spi1 144 groups = "spi1_grp";
145 }; 145 };
146 146
147 spi_2: spi_2 { 147 spi_2: spi_2 {
148 function = "sp 148 function = "spi2";
149 groups = "spi2 149 groups = "spi2_grp";
150 }; 150 };
151 }; 151 };
152 152
153 mailbox: mailbox@3024024 { 153 mailbox: mailbox@3024024 {
154 compatible = "brcm,ipr 154 compatible = "brcm,iproc-mailbox";
155 reg = <0x03024024 0x40 155 reg = <0x03024024 0x40>;
156 interrupts = <GIC_SPI 156 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
157 #interrupt-cells = <1> 157 #interrupt-cells = <1>;
158 interrupt-controller; 158 interrupt-controller;
159 #mbox-cells = <1>; 159 #mbox-cells = <1>;
160 }; 160 };
161 161
162 gpio_crmu: gpio@3024800 { 162 gpio_crmu: gpio@3024800 {
163 compatible = "brcm,cyg 163 compatible = "brcm,cygnus-crmu-gpio";
164 reg = <0x03024800 0x50 164 reg = <0x03024800 0x50>,
165 <0x03024008 0x18 165 <0x03024008 0x18>;
166 ngpios = <6>; 166 ngpios = <6>;
167 #gpio-cells = <2>; 167 #gpio-cells = <2>;
168 gpio-controller; 168 gpio-controller;
169 interrupt-controller; 169 interrupt-controller;
170 #interrupt-cells = <2> <<
171 interrupt-parent = <&m 170 interrupt-parent = <&mailbox>;
172 interrupts = <0>; 171 interrupts = <0>;
173 }; 172 };
174 173
175 mdio: mdio@18002000 { 174 mdio: mdio@18002000 {
176 compatible = "brcm,ipr 175 compatible = "brcm,iproc-mdio";
177 reg = <0x18002000 0x8> 176 reg = <0x18002000 0x8>;
178 #size-cells = <0>; 177 #size-cells = <0>;
179 #address-cells = <1>; 178 #address-cells = <1>;
180 status = "disabled"; 179 status = "disabled";
181 180
182 gphy0: ethernet-phy@0 181 gphy0: ethernet-phy@0 {
183 reg = <0>; 182 reg = <0>;
184 }; 183 };
185 184
186 gphy1: ethernet-phy@1 185 gphy1: ethernet-phy@1 {
187 reg = <1>; 186 reg = <1>;
188 }; 187 };
189 }; 188 };
190 189
191 switch: switch@18007000 { 190 switch: switch@18007000 {
192 compatible = "brcm,bcm 191 compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
193 reg = <0x18007000 0x10 192 reg = <0x18007000 0x1000>;
194 status = "disabled"; 193 status = "disabled";
195 194
196 ports { 195 ports {
197 #address-cells 196 #address-cells = <1>;
198 #size-cells = 197 #size-cells = <0>;
199 198
200 port@0 { 199 port@0 {
201 reg = 200 reg = <0>;
202 phy-ha 201 phy-handle = <&gphy0>;
203 phy-mo 202 phy-mode = "rgmii";
204 }; 203 };
205 204
206 port@1 { 205 port@1 {
207 reg = 206 reg = <1>;
208 phy-ha 207 phy-handle = <&gphy1>;
209 phy-mo 208 phy-mode = "rgmii";
210 }; 209 };
211 210
212 port@8 { 211 port@8 {
213 reg = 212 reg = <8>;
214 label 213 label = "cpu";
215 ethern 214 ethernet = <ð0>;
216 fixed- 215 fixed-link {
217 216 speed = <1000>;
218 217 full-duplex;
219 }; 218 };
220 }; 219 };
221 }; 220 };
222 }; 221 };
223 222
224 i2c0: i2c@18008000 { 223 i2c0: i2c@18008000 {
225 compatible = "brcm,cyg 224 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
226 reg = <0x18008000 0x10 225 reg = <0x18008000 0x100>;
227 #address-cells = <1>; 226 #address-cells = <1>;
228 #size-cells = <0>; 227 #size-cells = <0>;
229 interrupts = <GIC_SPI 228 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
230 clock-frequency = <100 229 clock-frequency = <100000>;
231 status = "disabled"; 230 status = "disabled";
232 }; 231 };
233 232
234 wdt0: wdt@18009000 { 233 wdt0: wdt@18009000 {
235 compatible = "arm,sp80 234 compatible = "arm,sp805" , "arm,primecell";
236 reg = <0x18009000 0x10 235 reg = <0x18009000 0x1000>;
237 interrupts = <GIC_SPI 236 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&axi81_clk>, 237 clocks = <&axi81_clk>, <&axi81_clk>;
239 clock-names = "wdog_cl 238 clock-names = "wdog_clk", "apb_pclk";
240 }; 239 };
241 240
242 gpio_ccm: gpio@1800a000 { 241 gpio_ccm: gpio@1800a000 {
243 compatible = "brcm,cyg 242 compatible = "brcm,cygnus-ccm-gpio";
244 reg = <0x1800a000 0x50 243 reg = <0x1800a000 0x50>,
245 <0x0301d164 0x20 244 <0x0301d164 0x20>;
246 ngpios = <24>; 245 ngpios = <24>;
247 #gpio-cells = <2>; 246 #gpio-cells = <2>;
248 gpio-controller; 247 gpio-controller;
249 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-controller; 249 interrupt-controller;
251 #interrupt-cells = <2> <<
252 }; 250 };
253 251
254 i2c1: i2c@1800b000 { 252 i2c1: i2c@1800b000 {
255 compatible = "brcm,cyg 253 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
256 reg = <0x1800b000 0x10 254 reg = <0x1800b000 0x100>;
257 #address-cells = <1>; 255 #address-cells = <1>;
258 #size-cells = <0>; 256 #size-cells = <0>;
259 interrupts = <GIC_SPI 257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
260 clock-frequency = <100 258 clock-frequency = <100000>;
261 status = "disabled"; 259 status = "disabled";
262 }; 260 };
263 261
264 pcie0: pcie@18012000 { 262 pcie0: pcie@18012000 {
265 compatible = "brcm,ipr 263 compatible = "brcm,iproc-pcie";
266 reg = <0x18012000 0x10 264 reg = <0x18012000 0x1000>;
267 265
268 #interrupt-cells = <1> 266 #interrupt-cells = <1>;
269 interrupt-map-mask = < 267 interrupt-map-mask = <0 0 0 0>;
270 interrupt-map = <0 0 0 268 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
271 269
272 linux,pci-domain = <0> 270 linux,pci-domain = <0>;
273 271
274 bus-range = <0x00 0xff 272 bus-range = <0x00 0xff>;
275 273
276 #address-cells = <3>; 274 #address-cells = <3>;
277 #size-cells = <2>; 275 #size-cells = <2>;
278 device_type = "pci"; 276 device_type = "pci";
279 ranges = <0x81000000 0 277 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
280 <0x82000000 0 278 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
281 279
282 phys = <&pcie0_phy>; 280 phys = <&pcie0_phy>;
283 phy-names = "pcie-phy" 281 phy-names = "pcie-phy";
284 282
285 status = "disabled"; 283 status = "disabled";
286 284
287 msi-parent = <&msi0>; 285 msi-parent = <&msi0>;
288 msi0: msi { 286 msi0: msi {
289 compatible = " 287 compatible = "brcm,iproc-msi";
290 msi-controller 288 msi-controller;
291 interrupt-pare 289 interrupt-parent = <&gic>;
292 interrupts = < 290 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
293 < 291 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
294 < 292 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
295 < 293 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
296 }; 294 };
297 }; 295 };
298 296
299 pcie1: pcie@18013000 { 297 pcie1: pcie@18013000 {
300 compatible = "brcm,ipr 298 compatible = "brcm,iproc-pcie";
301 reg = <0x18013000 0x10 299 reg = <0x18013000 0x1000>;
302 300
303 #interrupt-cells = <1> 301 #interrupt-cells = <1>;
304 interrupt-map-mask = < 302 interrupt-map-mask = <0 0 0 0>;
305 interrupt-map = <0 0 0 303 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
306 304
307 linux,pci-domain = <1> 305 linux,pci-domain = <1>;
308 306
309 bus-range = <0x00 0xff 307 bus-range = <0x00 0xff>;
310 308
311 #address-cells = <3>; 309 #address-cells = <3>;
312 #size-cells = <2>; 310 #size-cells = <2>;
313 device_type = "pci"; 311 device_type = "pci";
314 ranges = <0x81000000 0 312 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
315 <0x82000000 0 313 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
316 314
317 phys = <&pcie1_phy>; 315 phys = <&pcie1_phy>;
318 phy-names = "pcie-phy" 316 phy-names = "pcie-phy";
319 317
320 status = "disabled"; 318 status = "disabled";
321 319
322 msi-parent = <&msi1>; 320 msi-parent = <&msi1>;
323 msi1: msi { 321 msi1: msi {
324 compatible = " 322 compatible = "brcm,iproc-msi";
325 msi-controller 323 msi-controller;
326 interrupt-pare 324 interrupt-parent = <&gic>;
327 interrupts = < 325 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
328 < 326 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
329 < 327 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
330 < 328 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
331 }; 329 };
332 }; 330 };
333 331
334 dma0: dma@18018000 { 332 dma0: dma@18018000 {
335 compatible = "arm,pl33 333 compatible = "arm,pl330", "arm,primecell";
336 reg = <0x18018000 0x10 334 reg = <0x18018000 0x1000>;
337 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 336 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 337 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 338 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 339 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 340 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 341 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 342 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 343 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&apb_clk>; 344 clocks = <&apb_clk>;
347 clock-names = "apb_pcl 345 clock-names = "apb_pclk";
348 #dma-cells = <1>; 346 #dma-cells = <1>;
349 }; 347 };
350 348
351 uart0: serial@18020000 { 349 uart0: serial@18020000 {
352 compatible = "snps,dw- 350 compatible = "snps,dw-apb-uart";
353 reg = <0x18020000 0x10 351 reg = <0x18020000 0x100>;
354 reg-shift = <2>; 352 reg-shift = <2>;
355 reg-io-width = <4>; 353 reg-io-width = <4>;
356 interrupts = <GIC_SPI 354 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&axi81_clk>; 355 clocks = <&axi81_clk>;
358 clock-frequency = <100 356 clock-frequency = <100000000>;
359 status = "disabled"; 357 status = "disabled";
360 }; 358 };
361 359
362 uart1: serial@18021000 { 360 uart1: serial@18021000 {
363 compatible = "snps,dw- 361 compatible = "snps,dw-apb-uart";
364 reg = <0x18021000 0x10 362 reg = <0x18021000 0x100>;
365 reg-shift = <2>; 363 reg-shift = <2>;
366 reg-io-width = <4>; 364 reg-io-width = <4>;
367 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&axi81_clk>; 366 clocks = <&axi81_clk>;
369 clock-frequency = <100 367 clock-frequency = <100000000>;
370 status = "disabled"; 368 status = "disabled";
371 }; 369 };
372 370
373 uart2: serial@18022000 { 371 uart2: serial@18022000 {
374 compatible = "snps,dw- 372 compatible = "snps,dw-apb-uart";
375 reg = <0x18022000 0x10 373 reg = <0x18022000 0x100>;
376 reg-shift = <2>; 374 reg-shift = <2>;
377 reg-io-width = <4>; 375 reg-io-width = <4>;
378 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&axi81_clk>; 377 clocks = <&axi81_clk>;
380 clock-frequency = <100 378 clock-frequency = <100000000>;
381 status = "disabled"; 379 status = "disabled";
382 }; 380 };
383 381
384 uart3: serial@18023000 { 382 uart3: serial@18023000 {
385 compatible = "snps,dw- 383 compatible = "snps,dw-apb-uart";
386 reg = <0x18023000 0x10 384 reg = <0x18023000 0x100>;
387 reg-shift = <2>; 385 reg-shift = <2>;
388 reg-io-width = <4>; 386 reg-io-width = <4>;
389 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&axi81_clk>; 388 clocks = <&axi81_clk>;
391 clock-frequency = <100 389 clock-frequency = <100000000>;
392 status = "disabled"; 390 status = "disabled";
393 }; 391 };
394 392
395 spi0: spi@18028000 { 393 spi0: spi@18028000 {
396 compatible = "arm,pl02 394 compatible = "arm,pl022", "arm,primecell";
397 reg = <0x18028000 0x10 395 reg = <0x18028000 0x1000>;
398 #address-cells = <1>; 396 #address-cells = <1>;
399 #size-cells = <0>; 397 #size-cells = <0>;
400 interrupts = <GIC_SPI 398 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
401 pinctrl-0 = <&spi_0>; 399 pinctrl-0 = <&spi_0>;
402 clocks = <&axi81_clk>, 400 clocks = <&axi81_clk>, <&axi81_clk>;
403 clock-names = "sspclk" 401 clock-names = "sspclk", "apb_pclk";
404 status = "disabled"; 402 status = "disabled";
405 }; 403 };
406 404
407 spi1: spi@18029000 { 405 spi1: spi@18029000 {
408 compatible = "arm,pl02 406 compatible = "arm,pl022", "arm,primecell";
409 reg = <0x18029000 0x10 407 reg = <0x18029000 0x1000>;
410 #address-cells = <1>; 408 #address-cells = <1>;
411 #size-cells = <0>; 409 #size-cells = <0>;
412 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
413 pinctrl-0 = <&spi_1>; 411 pinctrl-0 = <&spi_1>;
414 clocks = <&axi81_clk>, 412 clocks = <&axi81_clk>, <&axi81_clk>;
415 clock-names = "sspclk" 413 clock-names = "sspclk", "apb_pclk";
416 status = "disabled"; 414 status = "disabled";
417 }; 415 };
418 416
419 spi2: spi@1802a000 { 417 spi2: spi@1802a000 {
420 compatible = "arm,pl02 418 compatible = "arm,pl022", "arm,primecell";
421 reg = <0x1802a000 0x10 419 reg = <0x1802a000 0x1000>;
422 #address-cells = <1>; 420 #address-cells = <1>;
423 #size-cells = <0>; 421 #size-cells = <0>;
424 interrupts = <GIC_SPI 422 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
425 pinctrl-0 = <&spi_2>; 423 pinctrl-0 = <&spi_2>;
426 clocks = <&axi81_clk>, 424 clocks = <&axi81_clk>, <&axi81_clk>;
427 clock-names = "sspclk" 425 clock-names = "sspclk", "apb_pclk";
428 status = "disabled"; 426 status = "disabled";
429 }; 427 };
430 428
431 rng: rng@18032000 { 429 rng: rng@18032000 {
432 compatible = "brcm,ipr 430 compatible = "brcm,iproc-rng200";
433 reg = <0x18032000 0x28 431 reg = <0x18032000 0x28>;
434 }; 432 };
435 433
436 sdhci0: sdhci@18041000 { 434 sdhci0: sdhci@18041000 {
437 compatible = "brcm,sdh 435 compatible = "brcm,sdhci-iproc-cygnus";
438 reg = <0x18041000 0x10 436 reg = <0x18041000 0x100>;
439 interrupts = <GIC_SPI 437 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&lcpll0 BCM_ 438 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
441 bus-width = <4>; 439 bus-width = <4>;
442 sdhci,auto-cmd12; 440 sdhci,auto-cmd12;
443 status = "disabled"; 441 status = "disabled";
444 }; 442 };
445 443
446 eth0: ethernet@18042000 { 444 eth0: ethernet@18042000 {
447 compatible = "brcm,ama 445 compatible = "brcm,amac";
448 reg = <0x18042000 0x10 446 reg = <0x18042000 0x1000>,
449 <0x18110000 0x10 447 <0x18110000 0x1000>;
450 reg-names = "amac_base 448 reg-names = "amac_base", "idm_base";
451 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
452 status = "disabled"; 450 status = "disabled";
453 }; 451 };
454 452
455 sdhci1: sdhci@18043000 { 453 sdhci1: sdhci@18043000 {
456 compatible = "brcm,sdh 454 compatible = "brcm,sdhci-iproc-cygnus";
457 reg = <0x18043000 0x10 455 reg = <0x18043000 0x100>;
458 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&lcpll0 BCM_ 457 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
460 bus-width = <4>; 458 bus-width = <4>;
461 sdhci,auto-cmd12; 459 sdhci,auto-cmd12;
462 status = "disabled"; 460 status = "disabled";
463 }; 461 };
464 462
465 nand_controller: nand-controll 463 nand_controller: nand-controller@18046000 {
466 compatible = "brcm,nan 464 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
467 reg = <0x18046000 0x60 465 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
468 <0x18046f00 0x20 466 <0x18046f00 0x20>;
469 reg-names = "nand", "i 467 reg-names = "nand", "iproc-idm", "iproc-ext";
470 interrupts = <GIC_SPI 468 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
471 469
472 #address-cells = <1>; 470 #address-cells = <1>;
473 #size-cells = <0>; 471 #size-cells = <0>;
474 472
475 brcm,nand-has-wp; 473 brcm,nand-has-wp;
476 }; 474 };
477 475
478 ehci0: usb@18048000 { 476 ehci0: usb@18048000 {
479 compatible = "generic- 477 compatible = "generic-ehci";
480 reg = <0x18048000 0x10 478 reg = <0x18048000 0x100>;
481 interrupts = <GIC_SPI 479 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
482 status = "disabled"; 480 status = "disabled";
483 }; 481 };
484 482
485 ohci0: usb@18048800 { 483 ohci0: usb@18048800 {
486 compatible = "generic- 484 compatible = "generic-ohci";
487 reg = <0x18048800 0x10 485 reg = <0x18048800 0x100>;
488 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
489 status = "disabled"; 487 status = "disabled";
490 }; 488 };
491 489
492 clcd: clcd@180a0000 { 490 clcd: clcd@180a0000 {
493 compatible = "arm,pl11 491 compatible = "arm,pl111", "arm,primecell";
494 reg = <0x180a0000 0x10 492 reg = <0x180a0000 0x1000>;
495 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "com 494 interrupt-names = "combined";
497 clocks = <&axi41_clk>, 495 clocks = <&axi41_clk>, <&apb_clk>;
498 clock-names = "clcdclk 496 clock-names = "clcdclk", "apb_pclk";
499 status = "disabled"; 497 status = "disabled";
500 }; 498 };
501 499
502 v3d: v3d@180a2000 { 500 v3d: v3d@180a2000 {
503 compatible = "brcm,cyg 501 compatible = "brcm,cygnus-v3d";
504 reg = <0x180a2000 0x10 502 reg = <0x180a2000 0x1000>;
505 clocks = <&mipipll BCM 503 clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
506 clock-names = "v3d_clk 504 clock-names = "v3d_clk";
507 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
508 status = "disabled"; 506 status = "disabled";
509 }; 507 };
510 508
511 vc4: gpu { 509 vc4: gpu {
512 compatible = "brcm,cyg 510 compatible = "brcm,cygnus-vc4";
513 }; 511 };
514 512
515 gpio_asiu: gpio@180a5000 { 513 gpio_asiu: gpio@180a5000 {
516 compatible = "brcm,cyg 514 compatible = "brcm,cygnus-asiu-gpio";
517 reg = <0x180a5000 0x66 515 reg = <0x180a5000 0x668>;
518 ngpios = <146>; 516 ngpios = <146>;
519 #gpio-cells = <2>; 517 #gpio-cells = <2>;
520 gpio-controller; 518 gpio-controller;
521 519
522 interrupt-controller; 520 interrupt-controller;
523 #interrupt-cells = <2> <<
524 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
525 gpio-ranges = <&pinctr 522 gpio-ranges = <&pinctrl 0 42 1>,
526 <&pinc 523 <&pinctrl 1 44 3>,
527 <&pinc 524 <&pinctrl 4 48 1>,
528 <&pinc 525 <&pinctrl 5 50 3>,
529 <&pinc 526 <&pinctrl 8 126 1>,
530 <&pinc 527 <&pinctrl 9 155 1>,
531 <&pinc 528 <&pinctrl 10 152 1>,
532 <&pinc 529 <&pinctrl 11 154 1>,
533 <&pinc 530 <&pinctrl 12 153 1>,
534 <&pinc 531 <&pinctrl 13 127 3>,
535 <&pinc 532 <&pinctrl 16 140 1>,
536 <&pinc 533 <&pinctrl 17 145 7>,
537 <&pinc 534 <&pinctrl 24 130 10>,
538 <&pinc 535 <&pinctrl 34 141 4>,
539 <&pinc 536 <&pinctrl 38 54 1>,
540 <&pinc 537 <&pinctrl 39 56 3>,
541 <&pinc 538 <&pinctrl 42 60 3>,
542 <&pinc 539 <&pinctrl 45 64 3>,
543 <&pinc 540 <&pinctrl 48 68 2>,
544 <&pinc 541 <&pinctrl 50 84 6>,
545 <&pinc 542 <&pinctrl 56 94 6>,
546 <&pinc 543 <&pinctrl 62 72 1>,
547 <&pinc 544 <&pinctrl 63 70 1>,
548 <&pinc 545 <&pinctrl 64 80 1>,
549 <&pinc 546 <&pinctrl 65 74 3>,
550 <&pinc 547 <&pinctrl 68 78 1>,
551 <&pinc 548 <&pinctrl 69 82 1>,
552 <&pinc 549 <&pinctrl 70 156 17>,
553 <&pinc 550 <&pinctrl 87 104 12>,
554 <&pinc 551 <&pinctrl 99 102 2>,
555 <&pinc 552 <&pinctrl 101 90 4>,
556 <&pinc 553 <&pinctrl 105 116 6>,
557 <&pinc 554 <&pinctrl 111 100 2>,
558 <&pinc 555 <&pinctrl 113 122 4>,
559 <&pinc 556 <&pinctrl 123 11 1>,
560 <&pinc 557 <&pinctrl 124 38 4>,
561 <&pinc 558 <&pinctrl 128 43 1>,
562 <&pinc 559 <&pinctrl 129 47 1>,
563 <&pinc 560 <&pinctrl 130 49 1>,
564 <&pinc 561 <&pinctrl 131 53 1>,
565 <&pinc 562 <&pinctrl 132 55 1>,
566 <&pinc 563 <&pinctrl 133 59 1>,
567 <&pinc 564 <&pinctrl 134 63 1>,
568 <&pinc 565 <&pinctrl 135 67 1>,
569 <&pinc 566 <&pinctrl 136 71 1>,
570 <&pinc 567 <&pinctrl 137 73 1>,
571 <&pinc 568 <&pinctrl 138 77 1>,
572 <&pinc 569 <&pinctrl 139 79 1>,
573 <&pinc 570 <&pinctrl 140 81 1>,
574 <&pinc 571 <&pinctrl 141 83 1>,
575 <&pinc 572 <&pinctrl 142 10 1>;
576 }; 573 };
577 574
578 ts_adc_syscon: ts_adc_syscon@1 575 ts_adc_syscon: ts_adc_syscon@180a6000 {
579 compatible = "brcm,ipr 576 compatible = "brcm,iproc-ts-adc-syscon", "syscon";
580 reg = <0x180a6000 0xc3 577 reg = <0x180a6000 0xc30>;
581 }; 578 };
582 579
583 touchscreen: touchscreen@180a6 580 touchscreen: touchscreen@180a6000 {
584 compatible = "brcm,ipr 581 compatible = "brcm,iproc-touchscreen";
585 #address-cells = <1>; 582 #address-cells = <1>;
586 #size-cells = <1>; 583 #size-cells = <1>;
587 ts_syscon = <&ts_adc_s 584 ts_syscon = <&ts_adc_syscon>;
588 clocks = <&asiu_clks B 585 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
589 clock-names = "tsc_clk 586 clock-names = "tsc_clk";
590 interrupts = <GIC_SPI 587 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
591 status = "disabled"; 588 status = "disabled";
592 }; 589 };
593 590
594 adc: adc@180a6000 { 591 adc: adc@180a6000 {
595 compatible = "brcm,ipr 592 compatible = "brcm,iproc-static-adc";
596 #io-channel-cells = <1 593 #io-channel-cells = <1>;
597 adc-syscon = <&ts_adc_ 594 adc-syscon = <&ts_adc_syscon>;
598 clocks = <&asiu_clks B 595 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
599 clock-names = "tsc_clk 596 clock-names = "tsc_clk";
600 interrupts = <GIC_SPI 597 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
601 status = "disabled"; 598 status = "disabled";
602 }; 599 };
603 600
604 pwm: pwm@180aa500 { 601 pwm: pwm@180aa500 {
605 compatible = "brcm,kon 602 compatible = "brcm,kona-pwm";
606 reg = <0x180aa500 0xc4 603 reg = <0x180aa500 0xc4>;
607 #pwm-cells = <3>; 604 #pwm-cells = <3>;
608 clocks = <&asiu_clks B 605 clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;
609 status = "disabled"; 606 status = "disabled";
610 }; 607 };
611 608
612 keypad: keypad@180ac000 { 609 keypad: keypad@180ac000 {
613 compatible = "brcm,bcm 610 compatible = "brcm,bcm-keypad";
614 reg = <0x180ac000 0x14 611 reg = <0x180ac000 0x14c>;
615 interrupts = <GIC_SPI 612 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&asiu_clks B 613 clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
617 clock-names = "peri_cl 614 clock-names = "peri_clk";
618 clock-frequency = <312 615 clock-frequency = <31250>;
619 pull-up-enabled; 616 pull-up-enabled;
620 col-debounce-filter-pe 617 col-debounce-filter-period = <0>;
621 status-debounce-filter 618 status-debounce-filter-period = <0>;
622 row-output-enabled; 619 row-output-enabled;
623 status = "disabled"; 620 status = "disabled";
624 }; 621 };
625 }; 622 };
626 }; 623 };
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