1 /* 1 /*
2 * BSD LICENSE 2 * BSD LICENSE
3 * 3 *
4 * Copyright(c) 2017 Broadcom. All rights re 4 * Copyright(c) 2017 Broadcom. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binar 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 9 *
10 * * Redistributions of source code must re 10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and th 11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must re 12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and th 13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materia 14 * the documentation and/or other materials provided with the
15 * distribution. 15 * distribution.
16 * * Neither the name of Broadcom Corporati 16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or 17 * contributors may be used to endorse or promote products derived
18 * from this software without specific pr 18 * from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE P 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33 #include <dt-bindings/interrupt-controller/arm 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq 34 #include <dt-bindings/interrupt-controller/irq.h>
35 35
36 / { 36 / {
37 compatible = "brcm,hr2"; 37 compatible = "brcm,hr2";
38 model = "Broadcom Hurricane 2 SoC"; 38 model = "Broadcom Hurricane 2 SoC";
39 interrupt-parent = <&gic>; 39 interrupt-parent = <&gic>;
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <1>; 41 #size-cells = <1>;
42 42
43 cpus { 43 cpus {
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <0>; 45 #size-cells = <0>;
46 46
47 cpu0: cpu@0 { 47 cpu0: cpu@0 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L 50 next-level-cache = <&L2>;
51 reg = <0x0>; 51 reg = <0x0>;
52 }; 52 };
53 }; 53 };
54 54
55 pmu { 55 pmu {
56 compatible = "arm,cortex-a9-pm 56 compatible = "arm,cortex-a9-pmu";
57 interrupts = <GIC_SPI 8 IRQ_TY !! 57 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
58 <GIC_SPI 9 IRQ_TY !! 58 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-affinity = <&cpu0>; 59 interrupt-affinity = <&cpu0>;
60 }; 60 };
61 61
62 mpcore@19000000 { 62 mpcore@19000000 {
63 compatible = "simple-bus"; 63 compatible = "simple-bus";
64 ranges = <0x00000000 0x1900000 64 ranges = <0x00000000 0x19000000 0x00023000>;
65 #address-cells = <1>; 65 #address-cells = <1>;
66 #size-cells = <1>; 66 #size-cells = <1>;
67 67
68 a9pll: arm_clk@0 { 68 a9pll: arm_clk@0 {
69 #clock-cells = <0>; 69 #clock-cells = <0>;
70 compatible = "brcm,hr2 70 compatible = "brcm,hr2-armpll";
71 clocks = <&osc>; 71 clocks = <&osc>;
72 reg = <0x0 0x1000>; 72 reg = <0x0 0x1000>;
73 }; 73 };
74 74
75 timer@20200 { 75 timer@20200 {
76 compatible = "arm,cort 76 compatible = "arm,cortex-a9-global-timer";
77 reg = <0x20200 0x100>; 77 reg = <0x20200 0x100>;
78 interrupts = <GIC_PPI 78 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
79 clocks = <&periph_clk> 79 clocks = <&periph_clk>;
80 }; 80 };
81 81
82 twd-timer@20600 { 82 twd-timer@20600 {
83 compatible = "arm,cort 83 compatible = "arm,cortex-a9-twd-timer";
84 reg = <0x20600 0x20>; 84 reg = <0x20600 0x20>;
85 interrupts = <GIC_PPI 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
86 86 IRQ_TYPE_EDGE_RISING)>;
87 clocks = <&periph_clk> 87 clocks = <&periph_clk>;
88 }; 88 };
89 89
90 twd-watchdog@20620 { 90 twd-watchdog@20620 {
91 compatible = "arm,cort 91 compatible = "arm,cortex-a9-twd-wdt";
92 reg = <0x20620 0x20>; 92 reg = <0x20620 0x20>;
93 interrupts = <GIC_PPI 93 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
94 94 IRQ_TYPE_EDGE_RISING)>;
95 clocks = <&periph_clk> 95 clocks = <&periph_clk>;
96 }; 96 };
97 97
98 gic: interrupt-controller@2100 98 gic: interrupt-controller@21000 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3> 100 #interrupt-cells = <3>;
101 #address-cells = <0>; 101 #address-cells = <0>;
102 interrupt-controller; 102 interrupt-controller;
103 reg = <0x21000 0x1000> 103 reg = <0x21000 0x1000>,
104 <0x20100 0x100>; 104 <0x20100 0x100>;
105 }; 105 };
106 106
107 L2: cache-controller@22000 { 107 L2: cache-controller@22000 {
108 compatible = "arm,pl31 108 compatible = "arm,pl310-cache";
109 reg = <0x22000 0x1000> 109 reg = <0x22000 0x1000>;
110 cache-unified; 110 cache-unified;
111 cache-level = <2>; 111 cache-level = <2>;
112 }; 112 };
113 }; 113 };
114 114
115 clocks { 115 clocks {
116 #address-cells = <1>; 116 #address-cells = <1>;
117 #size-cells = <1>; 117 #size-cells = <1>;
118 ranges; 118 ranges;
119 119
120 osc: oscillator { 120 osc: oscillator {
121 #clock-cells = <0>; 121 #clock-cells = <0>;
122 compatible = "fixed-cl 122 compatible = "fixed-clock";
123 clock-frequency = <250 123 clock-frequency = <25000000>;
124 }; 124 };
125 125
126 periph_clk: periph_clk { 126 periph_clk: periph_clk {
127 #clock-cells = <0>; 127 #clock-cells = <0>;
128 compatible = "fixed-fa 128 compatible = "fixed-factor-clock";
129 clocks = <&a9pll>; 129 clocks = <&a9pll>;
130 clock-div = <2>; 130 clock-div = <2>;
131 clock-mult = <1>; 131 clock-mult = <1>;
132 }; 132 };
133 }; 133 };
134 134
135 axi@18000000 { 135 axi@18000000 {
136 compatible = "simple-bus"; 136 compatible = "simple-bus";
137 ranges = <0x00000000 0x1800000 137 ranges = <0x00000000 0x18000000 0x0011c40c>;
138 #address-cells = <1>; 138 #address-cells = <1>;
139 #size-cells = <1>; 139 #size-cells = <1>;
140 140
141 uart0: serial@300 { 141 uart0: serial@300 {
142 compatible = "ns16550a 142 compatible = "ns16550a";
143 reg = <0x0300 0x100>; 143 reg = <0x0300 0x100>;
144 interrupts = <GIC_SPI 144 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&osc>; 145 clocks = <&osc>;
146 status = "disabled"; 146 status = "disabled";
147 }; 147 };
148 148
149 uart1: serial@400 { 149 uart1: serial@400 {
150 compatible = "ns16550a 150 compatible = "ns16550a";
151 reg = <0x0400 0x100>; 151 reg = <0x0400 0x100>;
152 interrupts = <GIC_SPI 152 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&osc>; 153 clocks = <&osc>;
154 status = "disabled"; 154 status = "disabled";
155 }; 155 };
156 156
157 dma@20000 { 157 dma@20000 {
158 compatible = "arm,pl33 158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0x20000 0x1000> 159 reg = <0x20000 0x1000>;
160 interrupts = <GIC_SPI 160 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 161 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 162 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 163 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 164 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 165 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 166 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 167 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 168 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
169 #dma-cells = <1>; 169 #dma-cells = <1>;
170 status = "disabled"; 170 status = "disabled";
171 }; 171 };
172 172
173 amac0: ethernet@22000 { 173 amac0: ethernet@22000 {
174 compatible = "brcm,nsp 174 compatible = "brcm,nsp-amac";
175 reg = <0x22000 0x1000> 175 reg = <0x22000 0x1000>,
176 <0x110000 0x1000 176 <0x110000 0x1000>;
177 reg-names = "amac_base 177 reg-names = "amac_base", "idm_base";
178 interrupts = <GIC_SPI 178 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
179 status = "disabled"; 179 status = "disabled";
180 }; 180 };
181 181
182 nand_controller: nand-controll 182 nand_controller: nand-controller@26000 {
183 compatible = "brcm,nan 183 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
184 reg = <0x26000 0x600>, 184 reg = <0x26000 0x600>,
185 <0x11b408 0x600> 185 <0x11b408 0x600>,
186 <0x026f00 0x20>; 186 <0x026f00 0x20>;
187 reg-names = "nand", "i 187 reg-names = "nand", "iproc-idm", "iproc-ext";
188 interrupts = <GIC_SPI 188 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
189 189
190 #address-cells = <1>; 190 #address-cells = <1>;
191 #size-cells = <0>; 191 #size-cells = <0>;
192 192
193 brcm,nand-has-wp; 193 brcm,nand-has-wp;
194 }; 194 };
195 195
196 gpiob: gpio@30000 { 196 gpiob: gpio@30000 {
197 compatible = "brcm,ipr 197 compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
198 reg = <0x30000 0x50>; 198 reg = <0x30000 0x50>;
199 #gpio-cells = <2>; 199 #gpio-cells = <2>;
200 gpio-controller; 200 gpio-controller;
201 ngpios = <4>; 201 ngpios = <4>;
202 interrupt-controller; 202 interrupt-controller;
203 #interrupt-cells = <2> <<
204 interrupts = <GIC_SPI 203 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
205 }; 204 };
206 205
207 pwm: pwm@31000 { 206 pwm: pwm@31000 {
208 compatible = "brcm,ipr 207 compatible = "brcm,iproc-pwm";
209 reg = <0x31000 0x28>; 208 reg = <0x31000 0x28>;
210 clocks = <&osc>; 209 clocks = <&osc>;
211 #pwm-cells = <3>; 210 #pwm-cells = <3>;
212 status = "disabled"; 211 status = "disabled";
213 }; 212 };
214 213
215 rng: rng@33000 { 214 rng: rng@33000 {
216 compatible = "brcm,bcm 215 compatible = "brcm,bcm-nsp-rng";
217 reg = <0x33000 0x14>; 216 reg = <0x33000 0x14>;
218 }; 217 };
219 218
220 qspi: spi@27200 { 219 qspi: spi@27200 {
221 compatible = "brcm,spi 220 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
222 reg = <0x027200 0x184> 221 reg = <0x027200 0x184>,
223 <0x027000 0x124> 222 <0x027000 0x124>,
224 <0x11c408 0x004> 223 <0x11c408 0x004>,
225 <0x0273a0 0x01c> 224 <0x0273a0 0x01c>;
226 reg-names = "mspi", "b 225 reg-names = "mspi", "bspi", "intr_regs",
227 "intr_stat 226 "intr_status_reg";
228 interrupts = <GIC_SPI 227 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 228 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 229 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 230 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 231 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 232 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 233 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "spi 234 interrupt-names = "spi_lr_fullness_reached",
236 "spi 235 "spi_lr_session_aborted",
237 "spi 236 "spi_lr_impatient",
238 "spi 237 "spi_lr_session_done",
239 "spi 238 "spi_lr_overhead",
240 "msp 239 "mspi_done",
241 "msp 240 "mspi_halted";
242 num-cs = <2>; 241 num-cs = <2>;
243 #address-cells = <1>; 242 #address-cells = <1>;
244 #size-cells = <0>; 243 #size-cells = <0>;
245 244
246 /* partitions defined 245 /* partitions defined in board DTS */
247 }; 246 };
248 247
249 ccbtimer0: timer@34000 { 248 ccbtimer0: timer@34000 {
250 compatible = "arm,sp80 249 compatible = "arm,sp804";
251 reg = <0x34000 0x1000> 250 reg = <0x34000 0x1000>;
252 interrupts = <GIC_SPI 251 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 252 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
254 }; 253 };
255 254
256 ccbtimer1: timer@35000 { 255 ccbtimer1: timer@35000 {
257 compatible = "arm,sp80 256 compatible = "arm,sp804";
258 reg = <0x35000 0x1000> 257 reg = <0x35000 0x1000>;
259 interrupts = <GIC_SPI 258 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 259 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
261 }; 260 };
262 261
263 i2c0: i2c@38000 { 262 i2c0: i2c@38000 {
264 compatible = "brcm,ipr 263 compatible = "brcm,iproc-i2c";
265 reg = <0x38000 0x50>; 264 reg = <0x38000 0x50>;
266 #address-cells = <1>; 265 #address-cells = <1>;
267 #size-cells = <0>; 266 #size-cells = <0>;
268 interrupts = <GIC_SPI 267 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
269 clock-frequency = <100 268 clock-frequency = <100000>;
270 }; 269 };
271 270
272 watchdog: watchdog@39000 { 271 watchdog: watchdog@39000 {
273 compatible = "arm,sp80 272 compatible = "arm,sp805", "arm,primecell";
274 reg = <0x39000 0x1000> 273 reg = <0x39000 0x1000>;
275 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
276 }; 275 };
277 276
278 i2c1: i2c@3b000 { 277 i2c1: i2c@3b000 {
279 compatible = "brcm,ipr 278 compatible = "brcm,iproc-i2c";
280 reg = <0x3b000 0x50>; 279 reg = <0x3b000 0x50>;
281 #address-cells = <1>; 280 #address-cells = <1>;
282 #size-cells = <0>; 281 #size-cells = <0>;
283 interrupts = <GIC_SPI 282 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
284 clock-frequency = <100 283 clock-frequency = <100000>;
285 }; 284 };
286 }; 285 };
287 286
288 pflash: nor@20000000 { 287 pflash: nor@20000000 {
289 compatible = "cfi-flash", "jed 288 compatible = "cfi-flash", "jedec-flash";
290 reg = <0x20000000 0x04000000>; 289 reg = <0x20000000 0x04000000>;
291 status = "disabled"; 290 status = "disabled";
292 #address-cells = <1>; 291 #address-cells = <1>;
293 #size-cells = <1>; 292 #size-cells = <1>;
294 293
295 /* partitions defined in board 294 /* partitions defined in board DTS */
296 }; 295 };
297 296
298 pcie0: pcie@18012000 { 297 pcie0: pcie@18012000 {
299 compatible = "brcm,iproc-pcie" 298 compatible = "brcm,iproc-pcie";
300 reg = <0x18012000 0x1000>; 299 reg = <0x18012000 0x1000>;
301 300
302 #interrupt-cells = <1>; 301 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 0> 302 interrupt-map-mask = <0 0 0 0>;
304 interrupt-map = <0 0 0 0 &gic 303 interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
305 304
306 linux,pci-domain = <0>; 305 linux,pci-domain = <0>;
307 306
308 bus-range = <0x00 0xff>; 307 bus-range = <0x00 0xff>;
309 308
310 #address-cells = <3>; 309 #address-cells = <3>;
311 #size-cells = <2>; 310 #size-cells = <2>;
312 device_type = "pci"; 311 device_type = "pci";
313 312
314 /* Note: The HW does not suppo 313 /* Note: The HW does not support I/O resources. So,
315 * only the memory resource ra 314 * only the memory resource range is being specified.
316 */ 315 */
317 ranges = <0x82000000 0 0x08000 316 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
318 317
319 status = "disabled"; 318 status = "disabled";
320 319
321 msi-parent = <&msi0>; 320 msi-parent = <&msi0>;
322 msi0: msi { 321 msi0: msi {
323 compatible = "brcm,ipr 322 compatible = "brcm,iproc-msi";
324 msi-controller; 323 msi-controller;
325 interrupt-parent = <&g 324 interrupt-parent = <&gic>;
326 interrupts = <GIC_SPI 325 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 326 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 327 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 328 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
330 brcm,pcie-msi-inten; 329 brcm,pcie-msi-inten;
331 }; 330 };
332 }; 331 };
333 332
334 pcie1: pcie@18013000 { 333 pcie1: pcie@18013000 {
335 compatible = "brcm,iproc-pcie" 334 compatible = "brcm,iproc-pcie";
336 reg = <0x18013000 0x1000>; 335 reg = <0x18013000 0x1000>;
337 336
338 #interrupt-cells = <1>; 337 #interrupt-cells = <1>;
339 interrupt-map-mask = <0 0 0 0> 338 interrupt-map-mask = <0 0 0 0>;
340 interrupt-map = <0 0 0 0 &gic 339 interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
341 340
342 linux,pci-domain = <1>; 341 linux,pci-domain = <1>;
343 342
344 bus-range = <0x00 0xff>; 343 bus-range = <0x00 0xff>;
345 344
346 #address-cells = <3>; 345 #address-cells = <3>;
347 #size-cells = <2>; 346 #size-cells = <2>;
348 device_type = "pci"; 347 device_type = "pci";
349 348
350 /* Note: The HW does not suppo 349 /* Note: The HW does not support I/O resources. So,
351 * only the memory resource ra 350 * only the memory resource range is being specified.
352 */ 351 */
353 ranges = <0x82000000 0 0x40000 352 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
354 353
355 status = "disabled"; 354 status = "disabled";
356 355
357 msi-parent = <&msi1>; 356 msi-parent = <&msi1>;
358 msi1: msi { 357 msi1: msi {
359 compatible = "brcm,ipr 358 compatible = "brcm,iproc-msi";
360 msi-controller; 359 msi-controller;
361 interrupt-parent = <&g 360 interrupt-parent = <&gic>;
362 interrupts = <GIC_SPI 361 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 362 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 363 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 364 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
366 brcm,pcie-msi-inten; 365 brcm,pcie-msi-inten;
367 }; 366 };
368 }; 367 };
369 }; 368 };
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