1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@ha 3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
4 */ 4 */
5 5
6 #include <dt-bindings/clock/bcm-nsp.h> 6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 11
12 / { 12 / {
13 interrupt-parent = <&gic>; 13 interrupt-parent = <&gic>;
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 16
17 pmu { 17 pmu {
18 compatible = "arm,cortex-a9-pm 18 compatible = "arm,cortex-a9-pmu";
19 interrupts = 19 interrupts =
20 <GIC_SPI 8 IRQ_TYPE_LE 20 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
21 <GIC_SPI 9 IRQ_TYPE_LE 21 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
22 }; 22 };
23 23
24 chipcommon-a-bus@18000000 { 24 chipcommon-a-bus@18000000 {
25 compatible = "simple-bus"; 25 compatible = "simple-bus";
26 ranges = <0x00000000 0x1800000 26 ranges = <0x00000000 0x18000000 0x00001000>;
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <1>; 28 #size-cells = <1>;
29 29
30 uart0: serial@300 { 30 uart0: serial@300 {
31 compatible = "ns16550" 31 compatible = "ns16550";
32 reg = <0x0300 0x100>; 32 reg = <0x0300 0x100>;
33 interrupts = <GIC_SPI 33 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&iprocslow>; 34 clocks = <&iprocslow>;
35 status = "disabled"; 35 status = "disabled";
36 }; 36 };
37 37
38 uart1: serial@400 { 38 uart1: serial@400 {
39 compatible = "ns16550" 39 compatible = "ns16550";
40 reg = <0x0400 0x100>; 40 reg = <0x0400 0x100>;
41 interrupts = <GIC_SPI 41 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&iprocslow>; 42 clocks = <&iprocslow>;
43 pinctrl-names = "defau 43 pinctrl-names = "default";
44 pinctrl-0 = <&pinmux_u 44 pinctrl-0 = <&pinmux_uart1>;
45 status = "disabled"; 45 status = "disabled";
46 }; 46 };
47 }; 47 };
48 48
49 mpcore-bus@19000000 { 49 mpcore-bus@19000000 {
50 compatible = "simple-bus"; 50 compatible = "simple-bus";
51 ranges = <0x00000000 0x1900000 51 ranges = <0x00000000 0x19000000 0x00023000>;
52 #address-cells = <1>; 52 #address-cells = <1>;
53 #size-cells = <1>; 53 #size-cells = <1>;
54 54
55 scu@20000 { 55 scu@20000 {
56 compatible = "arm,cort 56 compatible = "arm,cortex-a9-scu";
57 reg = <0x20000 0x100>; 57 reg = <0x20000 0x100>;
58 }; 58 };
59 59
60 timer@20200 { 60 timer@20200 {
61 compatible = "arm,cort 61 compatible = "arm,cortex-a9-global-timer";
62 reg = <0x20200 0x100>; 62 reg = <0x20200 0x100>;
63 interrupts = <GIC_PPI 63 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
64 clocks = <&periph_clk> 64 clocks = <&periph_clk>;
65 }; 65 };
66 66
67 timer@20600 { 67 timer@20600 {
68 compatible = "arm,cort 68 compatible = "arm,cortex-a9-twd-timer";
69 reg = <0x20600 0x20>; 69 reg = <0x20600 0x20>;
70 interrupts = <GIC_PPI 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
71 71 IRQ_TYPE_EDGE_RISING)>;
72 clocks = <&periph_clk> 72 clocks = <&periph_clk>;
73 }; 73 };
74 74
75 gic: interrupt-controller@2100 75 gic: interrupt-controller@21000 {
76 compatible = "arm,cort 76 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3> 77 #interrupt-cells = <3>;
78 #address-cells = <0>; 78 #address-cells = <0>;
79 interrupt-controller; 79 interrupt-controller;
80 reg = <0x21000 0x1000> 80 reg = <0x21000 0x1000>,
81 <0x20100 0x100>; 81 <0x20100 0x100>;
82 }; 82 };
83 83
84 L2: cache-controller@22000 { 84 L2: cache-controller@22000 {
85 compatible = "arm,pl31 85 compatible = "arm,pl310-cache";
86 reg = <0x22000 0x1000> 86 reg = <0x22000 0x1000>;
87 cache-unified; 87 cache-unified;
88 arm,shared-override; 88 arm,shared-override;
89 prefetch-data = <1>; 89 prefetch-data = <1>;
90 prefetch-instr = <1>; 90 prefetch-instr = <1>;
91 cache-level = <2>; 91 cache-level = <2>;
92 }; 92 };
93 }; 93 };
94 94
95 axi@18000000 { 95 axi@18000000 {
96 compatible = "brcm,bus-axi"; 96 compatible = "brcm,bus-axi";
97 reg = <0x18000000 0x1000>; 97 reg = <0x18000000 0x1000>;
98 ranges = <0x00000000 0x1800000 98 ranges = <0x00000000 0x18000000 0x00100000>;
99 #address-cells = <1>; 99 #address-cells = <1>;
100 #size-cells = <1>; 100 #size-cells = <1>;
101 101
102 #interrupt-cells = <1>; 102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0x000fff 103 interrupt-map-mask = <0x000fffff 0xffff>;
104 interrupt-map = 104 interrupt-map =
105 /* ChipCommon */ 105 /* ChipCommon */
106 <0x00000000 0 &gic GIC 106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
107 107
108 /* Switch Register Acc 108 /* Switch Register Access Block */
109 <0x00007000 0 &gic GIC 109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC 110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC 111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC 112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC 113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
114 <0x00007000 5 &gic GIC 114 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
115 <0x00007000 6 &gic GIC 115 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
116 <0x00007000 7 &gic GIC 116 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
117 <0x00007000 8 &gic GIC 117 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
118 <0x00007000 9 &gic GIC 118 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
119 <0x00007000 10 &gic GI 119 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
120 <0x00007000 11 &gic GI 120 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
121 <0x00007000 12 &gic GI 121 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
122 122
123 /* PCIe Controller 0 * 123 /* PCIe Controller 0 */
124 <0x00012000 0 &gic GIC 124 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
125 <0x00012000 1 &gic GIC 125 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
126 <0x00012000 2 &gic GIC 126 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
127 <0x00012000 3 &gic GIC 127 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
128 <0x00012000 4 &gic GIC 128 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
129 <0x00012000 5 &gic GIC 129 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
130 130
131 /* PCIe Controller 1 * 131 /* PCIe Controller 1 */
132 <0x00013000 0 &gic GIC 132 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00013000 1 &gic GIC 133 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00013000 2 &gic GIC 134 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00013000 3 &gic GIC 135 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00013000 4 &gic GIC 136 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00013000 5 &gic GIC 137 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
138 138
139 /* PCIe Controller 2 * 139 /* PCIe Controller 2 */
140 <0x00014000 0 &gic GIC 140 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
141 <0x00014000 1 &gic GIC 141 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
142 <0x00014000 2 &gic GIC 142 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
143 <0x00014000 3 &gic GIC 143 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
144 <0x00014000 4 &gic GIC 144 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
145 <0x00014000 5 &gic GIC 145 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
146 146
147 /* USB 2.0 Controller 147 /* USB 2.0 Controller */
148 <0x00021000 0 &gic GIC 148 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
149 149
150 /* USB 3.0 Controller 150 /* USB 3.0 Controller */
151 <0x00023000 0 &gic GIC 151 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
152 152
153 /* Ethernet Controller 153 /* Ethernet Controller 0 */
154 <0x00024000 0 &gic GIC 154 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
155 155
156 /* Ethernet Controller 156 /* Ethernet Controller 1 */
157 <0x00025000 0 &gic GIC 157 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
158 158
159 /* Ethernet Controller 159 /* Ethernet Controller 2 */
160 <0x00026000 0 &gic GIC 160 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
161 161
162 /* Ethernet Controller 162 /* Ethernet Controller 3 */
163 <0x00027000 0 &gic GIC 163 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
164 164
165 /* NAND Controller */ 165 /* NAND Controller */
166 <0x00028000 0 &gic GIC 166 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00028000 1 &gic GIC 167 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00028000 2 &gic GIC 168 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00028000 3 &gic GIC 169 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00028000 4 &gic GIC 170 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00028000 5 &gic GIC 171 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00028000 6 &gic GIC 172 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00028000 7 &gic GIC 173 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
174 174
175 chipcommon: chipcommon@0 { 175 chipcommon: chipcommon@0 {
176 reg = <0x00000000 0x10 176 reg = <0x00000000 0x1000>;
177 177
178 gpio-controller; 178 gpio-controller;
179 #gpio-cells = <2>; 179 #gpio-cells = <2>;
180 interrupt-controller; 180 interrupt-controller;
181 #interrupt-cells = <2> 181 #interrupt-cells = <2>;
182 }; 182 };
183 183
184 pcie0: pcie@12000 { 184 pcie0: pcie@12000 {
185 reg = <0x00012000 0x10 185 reg = <0x00012000 0x1000>;
186 186
187 #address-cells = <3>; 187 #address-cells = <3>;
188 #size-cells = <2>; 188 #size-cells = <2>;
189 }; 189 };
190 190
191 pcie1: pcie@13000 { 191 pcie1: pcie@13000 {
192 reg = <0x00013000 0x10 192 reg = <0x00013000 0x1000>;
193 193
194 #address-cells = <3>; 194 #address-cells = <3>;
195 #size-cells = <2>; 195 #size-cells = <2>;
196 }; 196 };
197 197
198 pcie2: pcie@14000 { 198 pcie2: pcie@14000 {
199 reg = <0x00014000 0x10 199 reg = <0x00014000 0x1000>;
200 200
201 #address-cells = <3>; 201 #address-cells = <3>;
202 #size-cells = <2>; 202 #size-cells = <2>;
203 }; 203 };
204 204
205 usb2: usb2@21000 { 205 usb2: usb2@21000 {
206 reg = <0x00021000 0x10 206 reg = <0x00021000 0x1000>;
207 207
208 #address-cells = <1>; 208 #address-cells = <1>;
209 #size-cells = <1>; 209 #size-cells = <1>;
210 ranges; 210 ranges;
211 211
212 interrupt-parent = <&g 212 interrupt-parent = <&gic>;
213 213
214 ehci: usb@21000 { 214 ehci: usb@21000 {
215 compatible = " 215 compatible = "generic-ehci";
216 reg = <0x00021 216 reg = <0x00021000 0x1000>;
217 interrupts = < 217 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
218 phys = <&usb2_ 218 phys = <&usb2_phy>;
219 219
220 #address-cells 220 #address-cells = <1>;
221 #size-cells = 221 #size-cells = <0>;
222 222
223 ehci_port1: po 223 ehci_port1: port@1 {
224 reg = 224 reg = <1>;
225 #trigg 225 #trigger-source-cells = <0>;
226 }; 226 };
227 227
228 ehci_port2: po 228 ehci_port2: port@2 {
229 reg = 229 reg = <2>;
230 #trigg 230 #trigger-source-cells = <0>;
231 }; 231 };
232 }; 232 };
233 233
234 ohci: usb@22000 { 234 ohci: usb@22000 {
235 compatible = " 235 compatible = "generic-ohci";
236 reg = <0x00022 236 reg = <0x00022000 0x1000>;
237 interrupts = < 237 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
238 238
239 #address-cells 239 #address-cells = <1>;
240 #size-cells = 240 #size-cells = <0>;
241 241
242 ohci_port1: po 242 ohci_port1: port@1 {
243 reg = 243 reg = <1>;
244 #trigg 244 #trigger-source-cells = <0>;
245 }; 245 };
246 246
247 ohci_port2: po 247 ohci_port2: port@2 {
248 reg = 248 reg = <2>;
249 #trigg 249 #trigger-source-cells = <0>;
250 }; 250 };
251 }; 251 };
252 }; 252 };
253 253
254 usb3: usb3@23000 { 254 usb3: usb3@23000 {
255 reg = <0x00023000 0x10 255 reg = <0x00023000 0x1000>;
256 256
257 #address-cells = <1>; 257 #address-cells = <1>;
258 #size-cells = <1>; 258 #size-cells = <1>;
259 ranges; 259 ranges;
260 260
261 interrupt-parent = <&g 261 interrupt-parent = <&gic>;
262 262
263 xhci: usb@23000 { 263 xhci: usb@23000 {
264 compatible = " 264 compatible = "generic-xhci";
265 reg = <0x00023 265 reg = <0x00023000 0x1000>;
266 interrupts = < 266 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
267 phys = <&usb3_ 267 phys = <&usb3_phy>;
268 phy-names = "u 268 phy-names = "usb";
269 269
270 #address-cells 270 #address-cells = <1>;
271 #size-cells = 271 #size-cells = <0>;
272 272
273 xhci_port1: po 273 xhci_port1: port@1 {
274 reg = 274 reg = <1>;
275 #trigg 275 #trigger-source-cells = <0>;
276 }; 276 };
277 }; 277 };
278 }; 278 };
279 279
280 gmac0: ethernet@24000 { 280 gmac0: ethernet@24000 {
281 reg = <0x24000 0x800>; 281 reg = <0x24000 0x800>;
282 phy-mode = "internal"; 282 phy-mode = "internal";
283 283
284 fixed-link { 284 fixed-link {
285 speed = <1000> 285 speed = <1000>;
286 full-duplex; 286 full-duplex;
287 }; 287 };
288 }; 288 };
289 289
290 gmac1: ethernet@25000 { 290 gmac1: ethernet@25000 {
291 reg = <0x25000 0x800>; 291 reg = <0x25000 0x800>;
292 phy-mode = "internal"; 292 phy-mode = "internal";
293 293
294 fixed-link { 294 fixed-link {
295 speed = <1000> 295 speed = <1000>;
296 full-duplex; 296 full-duplex;
297 }; 297 };
298 }; 298 };
299 299
300 gmac2: ethernet@26000 { 300 gmac2: ethernet@26000 {
301 reg = <0x26000 0x800>; 301 reg = <0x26000 0x800>;
302 phy-mode = "internal"; 302 phy-mode = "internal";
303 303
304 fixed-link { 304 fixed-link {
305 speed = <1000> 305 speed = <1000>;
306 full-duplex; 306 full-duplex;
307 }; 307 };
308 }; 308 };
309 309
310 gmac3: ethernet@27000 { 310 gmac3: ethernet@27000 {
311 reg = <0x27000 0x800>; 311 reg = <0x27000 0x800>;
312 }; 312 };
313 }; 313 };
314 314
315 pwm: pwm@18002000 { 315 pwm: pwm@18002000 {
316 compatible = "brcm,iproc-pwm"; 316 compatible = "brcm,iproc-pwm";
317 reg = <0x18002000 0x28>; 317 reg = <0x18002000 0x28>;
318 clocks = <&osc>; 318 clocks = <&osc>;
319 #pwm-cells = <3>; 319 #pwm-cells = <3>;
320 status = "disabled"; 320 status = "disabled";
321 }; 321 };
322 322
323 mdio: mdio@18003000 { 323 mdio: mdio@18003000 {
324 compatible = "brcm,iproc-mdio" 324 compatible = "brcm,iproc-mdio";
325 reg = <0x18003000 0x8>; 325 reg = <0x18003000 0x8>;
326 #size-cells = <0>; 326 #size-cells = <0>;
327 #address-cells = <1>; 327 #address-cells = <1>;
328 }; 328 };
329 329
330 mdio-mux@18003000 { 330 mdio-mux@18003000 {
331 compatible = "mdio-mux-mmioreg 331 compatible = "mdio-mux-mmioreg", "mdio-mux";
332 mdio-parent-bus = <&mdio>; 332 mdio-parent-bus = <&mdio>;
333 #address-cells = <1>; 333 #address-cells = <1>;
334 #size-cells = <0>; 334 #size-cells = <0>;
335 reg = <0x18003000 0x4>; 335 reg = <0x18003000 0x4>;
336 mux-mask = <0x200>; 336 mux-mask = <0x200>;
337 337
338 mdio@0 { 338 mdio@0 {
339 reg = <0x0>; 339 reg = <0x0>;
340 #address-cells = <1>; 340 #address-cells = <1>;
341 #size-cells = <0>; 341 #size-cells = <0>;
342 342
343 usb3_phy: usb3-phy@10 343 usb3_phy: usb3-phy@10 {
344 compatible = " 344 compatible = "brcm,ns-ax-usb3-phy";
345 reg = <0x10>; 345 reg = <0x10>;
346 usb3-dmp-sysco 346 usb3-dmp-syscon = <&usb3_dmp>;
347 #phy-cells = < 347 #phy-cells = <0>;
348 status = "disa 348 status = "disabled";
349 }; 349 };
350 }; 350 };
351 }; 351 };
352 352
353 rng: rng@18004000 { 353 rng: rng@18004000 {
354 compatible = "brcm,bcm5301x-rn 354 compatible = "brcm,bcm5301x-rng";
355 reg = <0x18004000 0x14>; 355 reg = <0x18004000 0x14>;
356 }; 356 };
357 357
358 srab: ethernet-switch@18007000 { 358 srab: ethernet-switch@18007000 {
359 compatible = "brcm,bcm53011-sr 359 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
360 reg = <0x18007000 0x1000>; 360 reg = <0x18007000 0x1000>;
361 361
362 status = "disabled"; 362 status = "disabled";
363 363
364 ports { 364 ports {
365 #address-cells = <1>; 365 #address-cells = <1>;
366 #size-cells = <0>; 366 #size-cells = <0>;
367 367
368 port@0 { 368 port@0 {
369 reg = <0>; 369 reg = <0>;
370 }; 370 };
371 371
372 port@1 { 372 port@1 {
373 reg = <1>; 373 reg = <1>;
374 }; 374 };
375 375
376 port@2 { 376 port@2 {
377 reg = <2>; 377 reg = <2>;
378 }; 378 };
379 379
380 port@3 { 380 port@3 {
381 reg = <3>; 381 reg = <3>;
382 }; 382 };
383 383
384 port@4 { 384 port@4 {
385 reg = <4>; 385 reg = <4>;
386 }; 386 };
387 387
388 port@5 { 388 port@5 {
389 reg = <5>; 389 reg = <5>;
390 ethernet = <&g 390 ethernet = <&gmac0>;
391 }; 391 };
392 392
393 port@7 { 393 port@7 {
394 reg = <7>; 394 reg = <7>;
395 ethernet = <&g 395 ethernet = <&gmac1>;
396 }; 396 };
397 397
398 port@8 { 398 port@8 {
399 reg = <8>; 399 reg = <8>;
400 ethernet = <&g 400 ethernet = <&gmac2>;
401 401
402 fixed-link { 402 fixed-link {
403 speed 403 speed = <1000>;
404 full-d 404 full-duplex;
405 }; 405 };
406 }; 406 };
407 }; 407 };
408 }; 408 };
409 409
410 uart2: serial@18008000 { 410 uart2: serial@18008000 {
411 compatible = "ns16550a"; 411 compatible = "ns16550a";
412 reg = <0x18008000 0x20>; 412 reg = <0x18008000 0x20>;
413 clocks = <&iprocslow>; 413 clocks = <&iprocslow>;
414 interrupts = <GIC_SPI 86 IRQ_T 414 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
415 reg-shift = <2>; 415 reg-shift = <2>;
416 status = "disabled"; 416 status = "disabled";
417 }; 417 };
418 418
419 dmu-bus@1800c000 { 419 dmu-bus@1800c000 {
420 compatible = "simple-bus"; 420 compatible = "simple-bus";
421 ranges = <0 0x1800c000 0x1000> 421 ranges = <0 0x1800c000 0x1000>;
422 #address-cells = <1>; 422 #address-cells = <1>;
423 #size-cells = <1>; 423 #size-cells = <1>;
424 424
425 cru-bus@100 { 425 cru-bus@100 {
426 compatible = "brcm,ns- 426 compatible = "brcm,ns-cru", "simple-mfd";
427 reg = <0x100 0x1a4>; 427 reg = <0x100 0x1a4>;
428 ranges; 428 ranges;
429 #address-cells = <1>; 429 #address-cells = <1>;
430 #size-cells = <1>; 430 #size-cells = <1>;
431 431
432 usb2_phy: phy@164 { 432 usb2_phy: phy@164 {
433 compatible = " 433 compatible = "brcm,ns-usb2-phy";
434 reg = <0x164 0 434 reg = <0x164 0x4>;
435 brcm,syscon-cl 435 brcm,syscon-clkset = <&cru_clkset>;
436 clocks = <&gen 436 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
437 clock-names = 437 clock-names = "phy-ref-clk";
438 #phy-cells = < 438 #phy-cells = <0>;
439 }; 439 };
440 440
441 cru_clkset: syscon@180 441 cru_clkset: syscon@180 {
442 compatible = " 442 compatible = "brcm,cru-clkset", "syscon";
443 reg = <0x180 0 443 reg = <0x180 0x4>;
444 }; 444 };
445 445
446 pinctrl: pinctrl@1c0 { 446 pinctrl: pinctrl@1c0 {
447 compatible = " 447 compatible = "brcm,bcm4708-pinmux";
448 reg = <0x1c0 0 448 reg = <0x1c0 0x24>;
449 reg-names = "c 449 reg-names = "cru_gpio_control";
450 450
451 spi-pins { 451 spi-pins {
452 groups 452 groups = "spi_grp";
453 functi 453 function = "spi";
454 }; 454 };
455 455
456 pinmux_i2c: i2 456 pinmux_i2c: i2c-pins {
457 groups 457 groups = "i2c_grp";
458 functi 458 function = "i2c";
459 }; 459 };
460 460
461 pinmux_pwm: pw 461 pinmux_pwm: pwm-pins {
462 groups 462 groups = "pwm0_grp", "pwm1_grp",
463 463 "pwm2_grp", "pwm3_grp";
464 functi 464 function = "pwm";
465 }; 465 };
466 466
467 pinmux_uart1: 467 pinmux_uart1: uart1-pins {
468 groups 468 groups = "uart1_grp";
469 functi 469 function = "uart1";
470 }; 470 };
471 }; 471 };
472 472
473 thermal: thermal@2c0 { 473 thermal: thermal@2c0 {
474 compatible = " 474 compatible = "brcm,ns-thermal";
475 reg = <0x2c0 0 475 reg = <0x2c0 0x10>;
476 #thermal-senso 476 #thermal-sensor-cells = <0>;
477 }; 477 };
478 }; 478 };
479 }; 479 };
480 480
481 nand_controller: nand-controller@18028 481 nand_controller: nand-controller@18028000 {
482 compatible = "brcm,nand-iproc" 482 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
483 reg = <0x18028000 0x600>, <0x1 483 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
484 reg-names = "nand", "iproc-idm 484 reg-names = "nand", "iproc-idm", "iproc-ext";
485 interrupts = <GIC_SPI 68 IRQ_T 485 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
486 486
487 #address-cells = <1>; 487 #address-cells = <1>;
488 #size-cells = <0>; 488 #size-cells = <0>;
489 489
490 brcm,nand-has-wp; 490 brcm,nand-has-wp;
491 }; 491 };
492 492
493 usb3_dmp: syscon@18105000 { 493 usb3_dmp: syscon@18105000 {
494 reg = <0x18105000 0x1000>; 494 reg = <0x18105000 0x1000>;
495 }; 495 };
496 496
497 thermal-zones { 497 thermal-zones {
498 cpu_thermal: cpu-thermal { 498 cpu_thermal: cpu-thermal {
499 polling-delay-passive 499 polling-delay-passive = <0>;
500 polling-delay = <1000> 500 polling-delay = <1000>;
501 coefficients = <(-556) 501 coefficients = <(-556) 418000>;
502 thermal-sensors = <&th 502 thermal-sensors = <&thermal>;
503 503
504 trips { 504 trips {
505 cpu-crit { 505 cpu-crit {
506 temper 506 temperature = <125000>;
507 hyster 507 hysteresis = <0>;
508 type = 508 type = "critical";
509 }; 509 };
510 }; 510 };
511 511
512 cooling-maps { 512 cooling-maps {
513 }; 513 };
514 }; 514 };
515 }; 515 };
516 }; 516 };
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