1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@ha 3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
4 */ 4 */
5 5
6 #include <dt-bindings/clock/bcm-nsp.h> 6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 11
12 / { 12 / {
13 interrupt-parent = <&gic>; 13 interrupt-parent = <&gic>;
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 16
17 pmu { <<
18 compatible = "arm,cortex-a9-pm <<
19 interrupts = <<
20 <GIC_SPI 8 IRQ_TYPE_LE <<
21 <GIC_SPI 9 IRQ_TYPE_LE <<
22 }; <<
23 <<
24 chipcommon-a-bus@18000000 { 17 chipcommon-a-bus@18000000 {
25 compatible = "simple-bus"; 18 compatible = "simple-bus";
26 ranges = <0x00000000 0x1800000 19 ranges = <0x00000000 0x18000000 0x00001000>;
27 #address-cells = <1>; 20 #address-cells = <1>;
28 #size-cells = <1>; 21 #size-cells = <1>;
29 22
30 uart0: serial@300 { 23 uart0: serial@300 {
31 compatible = "ns16550" 24 compatible = "ns16550";
32 reg = <0x0300 0x100>; 25 reg = <0x0300 0x100>;
33 interrupts = <GIC_SPI 26 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&iprocslow>; 27 clocks = <&iprocslow>;
35 status = "disabled"; 28 status = "disabled";
36 }; 29 };
37 30
38 uart1: serial@400 { 31 uart1: serial@400 {
39 compatible = "ns16550" 32 compatible = "ns16550";
40 reg = <0x0400 0x100>; 33 reg = <0x0400 0x100>;
41 interrupts = <GIC_SPI 34 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&iprocslow>; 35 clocks = <&iprocslow>;
43 pinctrl-names = "defau 36 pinctrl-names = "default";
44 pinctrl-0 = <&pinmux_u 37 pinctrl-0 = <&pinmux_uart1>;
45 status = "disabled"; 38 status = "disabled";
46 }; 39 };
47 }; 40 };
48 41
49 mpcore-bus@19000000 { 42 mpcore-bus@19000000 {
50 compatible = "simple-bus"; 43 compatible = "simple-bus";
51 ranges = <0x00000000 0x1900000 44 ranges = <0x00000000 0x19000000 0x00023000>;
52 #address-cells = <1>; 45 #address-cells = <1>;
53 #size-cells = <1>; 46 #size-cells = <1>;
54 47
55 scu@20000 { 48 scu@20000 {
56 compatible = "arm,cort 49 compatible = "arm,cortex-a9-scu";
57 reg = <0x20000 0x100>; 50 reg = <0x20000 0x100>;
58 }; 51 };
59 52
60 timer@20200 { 53 timer@20200 {
61 compatible = "arm,cort 54 compatible = "arm,cortex-a9-global-timer";
62 reg = <0x20200 0x100>; 55 reg = <0x20200 0x100>;
63 interrupts = <GIC_PPI 56 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
64 clocks = <&periph_clk> 57 clocks = <&periph_clk>;
65 }; 58 };
66 59
67 timer@20600 { 60 timer@20600 {
68 compatible = "arm,cort 61 compatible = "arm,cortex-a9-twd-timer";
69 reg = <0x20600 0x20>; 62 reg = <0x20600 0x20>;
70 interrupts = <GIC_PPI 63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
71 64 IRQ_TYPE_EDGE_RISING)>;
72 clocks = <&periph_clk> 65 clocks = <&periph_clk>;
73 }; 66 };
74 67
75 gic: interrupt-controller@2100 68 gic: interrupt-controller@21000 {
76 compatible = "arm,cort 69 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3> 70 #interrupt-cells = <3>;
78 #address-cells = <0>; 71 #address-cells = <0>;
79 interrupt-controller; 72 interrupt-controller;
80 reg = <0x21000 0x1000> 73 reg = <0x21000 0x1000>,
81 <0x20100 0x100>; 74 <0x20100 0x100>;
82 }; 75 };
83 76
84 L2: cache-controller@22000 { 77 L2: cache-controller@22000 {
85 compatible = "arm,pl31 78 compatible = "arm,pl310-cache";
86 reg = <0x22000 0x1000> 79 reg = <0x22000 0x1000>;
87 cache-unified; 80 cache-unified;
88 arm,shared-override; 81 arm,shared-override;
89 prefetch-data = <1>; 82 prefetch-data = <1>;
90 prefetch-instr = <1>; 83 prefetch-instr = <1>;
91 cache-level = <2>; 84 cache-level = <2>;
92 }; 85 };
93 }; 86 };
94 87
95 axi@18000000 { 88 axi@18000000 {
96 compatible = "brcm,bus-axi"; 89 compatible = "brcm,bus-axi";
97 reg = <0x18000000 0x1000>; 90 reg = <0x18000000 0x1000>;
98 ranges = <0x00000000 0x1800000 91 ranges = <0x00000000 0x18000000 0x00100000>;
99 #address-cells = <1>; 92 #address-cells = <1>;
100 #size-cells = <1>; 93 #size-cells = <1>;
101 94
102 #interrupt-cells = <1>; 95 #interrupt-cells = <1>;
103 interrupt-map-mask = <0x000fff 96 interrupt-map-mask = <0x000fffff 0xffff>;
104 interrupt-map = 97 interrupt-map =
105 /* ChipCommon */ 98 /* ChipCommon */
106 <0x00000000 0 &gic GIC 99 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
107 100
108 /* Switch Register Acc 101 /* Switch Register Access Block */
109 <0x00007000 0 &gic GIC 102 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC 103 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC 104 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC 105 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC 106 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
114 <0x00007000 5 &gic GIC 107 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
115 <0x00007000 6 &gic GIC 108 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
116 <0x00007000 7 &gic GIC 109 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
117 <0x00007000 8 &gic GIC 110 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
118 <0x00007000 9 &gic GIC 111 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
119 <0x00007000 10 &gic GI 112 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
120 <0x00007000 11 &gic GI 113 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
121 <0x00007000 12 &gic GI 114 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
122 115
123 /* PCIe Controller 0 * 116 /* PCIe Controller 0 */
124 <0x00012000 0 &gic GIC 117 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
125 <0x00012000 1 &gic GIC 118 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
126 <0x00012000 2 &gic GIC 119 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
127 <0x00012000 3 &gic GIC 120 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
128 <0x00012000 4 &gic GIC 121 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
129 <0x00012000 5 &gic GIC 122 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
130 123
131 /* PCIe Controller 1 * 124 /* PCIe Controller 1 */
132 <0x00013000 0 &gic GIC 125 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00013000 1 &gic GIC 126 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00013000 2 &gic GIC 127 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00013000 3 &gic GIC 128 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00013000 4 &gic GIC 129 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00013000 5 &gic GIC 130 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
138 131
139 /* PCIe Controller 2 * 132 /* PCIe Controller 2 */
140 <0x00014000 0 &gic GIC 133 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
141 <0x00014000 1 &gic GIC 134 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
142 <0x00014000 2 &gic GIC 135 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
143 <0x00014000 3 &gic GIC 136 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
144 <0x00014000 4 &gic GIC 137 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
145 <0x00014000 5 &gic GIC 138 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
146 139
147 /* USB 2.0 Controller 140 /* USB 2.0 Controller */
148 <0x00021000 0 &gic GIC 141 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
149 142
150 /* USB 3.0 Controller 143 /* USB 3.0 Controller */
151 <0x00023000 0 &gic GIC 144 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
152 145
153 /* Ethernet Controller 146 /* Ethernet Controller 0 */
154 <0x00024000 0 &gic GIC 147 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
155 148
156 /* Ethernet Controller 149 /* Ethernet Controller 1 */
157 <0x00025000 0 &gic GIC 150 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
158 151
159 /* Ethernet Controller 152 /* Ethernet Controller 2 */
160 <0x00026000 0 &gic GIC 153 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
161 154
162 /* Ethernet Controller 155 /* Ethernet Controller 3 */
163 <0x00027000 0 &gic GIC 156 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
164 157
165 /* NAND Controller */ 158 /* NAND Controller */
166 <0x00028000 0 &gic GIC 159 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00028000 1 &gic GIC 160 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00028000 2 &gic GIC 161 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00028000 3 &gic GIC 162 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00028000 4 &gic GIC 163 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00028000 5 &gic GIC 164 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00028000 6 &gic GIC 165 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00028000 7 &gic GIC 166 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
174 167
175 chipcommon: chipcommon@0 { 168 chipcommon: chipcommon@0 {
176 reg = <0x00000000 0x10 169 reg = <0x00000000 0x1000>;
177 170
178 gpio-controller; 171 gpio-controller;
179 #gpio-cells = <2>; 172 #gpio-cells = <2>;
180 interrupt-controller; 173 interrupt-controller;
181 #interrupt-cells = <2> 174 #interrupt-cells = <2>;
182 }; 175 };
183 176
184 pcie0: pcie@12000 { 177 pcie0: pcie@12000 {
185 reg = <0x00012000 0x10 178 reg = <0x00012000 0x1000>;
186 179
187 #address-cells = <3>; 180 #address-cells = <3>;
188 #size-cells = <2>; 181 #size-cells = <2>;
189 }; 182 };
190 183
191 pcie1: pcie@13000 { 184 pcie1: pcie@13000 {
192 reg = <0x00013000 0x10 185 reg = <0x00013000 0x1000>;
193 186
194 #address-cells = <3>; 187 #address-cells = <3>;
195 #size-cells = <2>; 188 #size-cells = <2>;
196 }; 189 };
197 190
198 pcie2: pcie@14000 { 191 pcie2: pcie@14000 {
199 reg = <0x00014000 0x10 192 reg = <0x00014000 0x1000>;
200 193
201 #address-cells = <3>; 194 #address-cells = <3>;
202 #size-cells = <2>; 195 #size-cells = <2>;
203 }; 196 };
204 197
205 usb2: usb2@21000 { 198 usb2: usb2@21000 {
206 reg = <0x00021000 0x10 199 reg = <0x00021000 0x1000>;
207 200
208 #address-cells = <1>; 201 #address-cells = <1>;
209 #size-cells = <1>; 202 #size-cells = <1>;
210 ranges; 203 ranges;
211 204
212 interrupt-parent = <&g 205 interrupt-parent = <&gic>;
213 206
214 ehci: usb@21000 { 207 ehci: usb@21000 {
215 compatible = " 208 compatible = "generic-ehci";
216 reg = <0x00021 209 reg = <0x00021000 0x1000>;
217 interrupts = < 210 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
218 phys = <&usb2_ 211 phys = <&usb2_phy>;
219 212
220 #address-cells 213 #address-cells = <1>;
221 #size-cells = 214 #size-cells = <0>;
222 215
223 ehci_port1: po 216 ehci_port1: port@1 {
224 reg = 217 reg = <1>;
225 #trigg 218 #trigger-source-cells = <0>;
226 }; 219 };
227 220
228 ehci_port2: po 221 ehci_port2: port@2 {
229 reg = 222 reg = <2>;
230 #trigg 223 #trigger-source-cells = <0>;
231 }; 224 };
232 }; 225 };
233 226
234 ohci: usb@22000 { 227 ohci: usb@22000 {
235 compatible = " 228 compatible = "generic-ohci";
236 reg = <0x00022 229 reg = <0x00022000 0x1000>;
237 interrupts = < 230 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
238 231
239 #address-cells 232 #address-cells = <1>;
240 #size-cells = 233 #size-cells = <0>;
241 234
242 ohci_port1: po 235 ohci_port1: port@1 {
243 reg = 236 reg = <1>;
244 #trigg 237 #trigger-source-cells = <0>;
245 }; 238 };
246 239
247 ohci_port2: po 240 ohci_port2: port@2 {
248 reg = 241 reg = <2>;
249 #trigg 242 #trigger-source-cells = <0>;
250 }; 243 };
251 }; 244 };
252 }; 245 };
253 246
254 usb3: usb3@23000 { 247 usb3: usb3@23000 {
255 reg = <0x00023000 0x10 248 reg = <0x00023000 0x1000>;
256 249
257 #address-cells = <1>; 250 #address-cells = <1>;
258 #size-cells = <1>; 251 #size-cells = <1>;
259 ranges; 252 ranges;
260 253
261 interrupt-parent = <&g 254 interrupt-parent = <&gic>;
262 255
263 xhci: usb@23000 { 256 xhci: usb@23000 {
264 compatible = " 257 compatible = "generic-xhci";
265 reg = <0x00023 258 reg = <0x00023000 0x1000>;
266 interrupts = < 259 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
267 phys = <&usb3_ 260 phys = <&usb3_phy>;
268 phy-names = "u 261 phy-names = "usb";
269 262
270 #address-cells 263 #address-cells = <1>;
271 #size-cells = 264 #size-cells = <0>;
272 265
273 xhci_port1: po 266 xhci_port1: port@1 {
274 reg = 267 reg = <1>;
275 #trigg 268 #trigger-source-cells = <0>;
276 }; 269 };
277 }; 270 };
278 }; 271 };
279 272
280 gmac0: ethernet@24000 { 273 gmac0: ethernet@24000 {
281 reg = <0x24000 0x800>; 274 reg = <0x24000 0x800>;
282 phy-mode = "internal"; 275 phy-mode = "internal";
283 276
284 fixed-link { 277 fixed-link {
285 speed = <1000> 278 speed = <1000>;
286 full-duplex; 279 full-duplex;
287 }; 280 };
288 }; 281 };
289 282
290 gmac1: ethernet@25000 { 283 gmac1: ethernet@25000 {
291 reg = <0x25000 0x800>; 284 reg = <0x25000 0x800>;
292 phy-mode = "internal"; 285 phy-mode = "internal";
293 286
294 fixed-link { 287 fixed-link {
295 speed = <1000> 288 speed = <1000>;
296 full-duplex; 289 full-duplex;
297 }; 290 };
298 }; 291 };
299 292
300 gmac2: ethernet@26000 { 293 gmac2: ethernet@26000 {
301 reg = <0x26000 0x800>; 294 reg = <0x26000 0x800>;
302 phy-mode = "internal"; 295 phy-mode = "internal";
303 296
304 fixed-link { 297 fixed-link {
305 speed = <1000> 298 speed = <1000>;
306 full-duplex; 299 full-duplex;
307 }; 300 };
308 }; 301 };
309 302
310 gmac3: ethernet@27000 { 303 gmac3: ethernet@27000 {
311 reg = <0x27000 0x800>; 304 reg = <0x27000 0x800>;
312 }; 305 };
313 }; 306 };
314 307
315 pwm: pwm@18002000 { 308 pwm: pwm@18002000 {
316 compatible = "brcm,iproc-pwm"; 309 compatible = "brcm,iproc-pwm";
317 reg = <0x18002000 0x28>; 310 reg = <0x18002000 0x28>;
318 clocks = <&osc>; 311 clocks = <&osc>;
319 #pwm-cells = <3>; 312 #pwm-cells = <3>;
320 status = "disabled"; 313 status = "disabled";
321 }; 314 };
322 315
323 mdio: mdio@18003000 { 316 mdio: mdio@18003000 {
324 compatible = "brcm,iproc-mdio" 317 compatible = "brcm,iproc-mdio";
325 reg = <0x18003000 0x8>; 318 reg = <0x18003000 0x8>;
326 #size-cells = <0>; 319 #size-cells = <0>;
327 #address-cells = <1>; 320 #address-cells = <1>;
328 }; 321 };
329 322
330 mdio-mux@18003000 { <<
331 compatible = "mdio-mux-mmioreg <<
332 mdio-parent-bus = <&mdio>; <<
333 #address-cells = <1>; <<
334 #size-cells = <0>; <<
335 reg = <0x18003000 0x4>; <<
336 mux-mask = <0x200>; <<
337 <<
338 mdio@0 { <<
339 reg = <0x0>; <<
340 #address-cells = <1>; <<
341 #size-cells = <0>; <<
342 <<
343 usb3_phy: usb3-phy@10 <<
344 compatible = " <<
345 reg = <0x10>; <<
346 usb3-dmp-sysco <<
347 #phy-cells = < <<
348 status = "disa <<
349 }; <<
350 }; <<
351 }; <<
352 <<
353 rng: rng@18004000 { 323 rng: rng@18004000 {
354 compatible = "brcm,bcm5301x-rn 324 compatible = "brcm,bcm5301x-rng";
355 reg = <0x18004000 0x14>; 325 reg = <0x18004000 0x14>;
356 }; 326 };
357 327
358 srab: ethernet-switch@18007000 { 328 srab: ethernet-switch@18007000 {
359 compatible = "brcm,bcm53011-sr 329 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
360 reg = <0x18007000 0x1000>; 330 reg = <0x18007000 0x1000>;
361 331
362 status = "disabled"; 332 status = "disabled";
363 333
364 ports { 334 ports {
365 #address-cells = <1>; 335 #address-cells = <1>;
366 #size-cells = <0>; 336 #size-cells = <0>;
367 337
368 port@0 { 338 port@0 {
369 reg = <0>; 339 reg = <0>;
370 }; 340 };
371 341
372 port@1 { 342 port@1 {
373 reg = <1>; 343 reg = <1>;
374 }; 344 };
375 345
376 port@2 { 346 port@2 {
377 reg = <2>; 347 reg = <2>;
378 }; 348 };
379 349
380 port@3 { 350 port@3 {
381 reg = <3>; 351 reg = <3>;
382 }; 352 };
383 353
384 port@4 { 354 port@4 {
385 reg = <4>; 355 reg = <4>;
386 }; 356 };
387 357
388 port@5 { 358 port@5 {
389 reg = <5>; 359 reg = <5>;
390 ethernet = <&g 360 ethernet = <&gmac0>;
391 }; 361 };
392 362
393 port@7 { 363 port@7 {
394 reg = <7>; 364 reg = <7>;
395 ethernet = <&g 365 ethernet = <&gmac1>;
396 }; 366 };
397 367
398 port@8 { 368 port@8 {
399 reg = <8>; 369 reg = <8>;
400 ethernet = <&g 370 ethernet = <&gmac2>;
401 371
402 fixed-link { 372 fixed-link {
403 speed 373 speed = <1000>;
404 full-d 374 full-duplex;
405 }; 375 };
406 }; 376 };
407 }; 377 };
408 }; 378 };
409 379
410 uart2: serial@18008000 { 380 uart2: serial@18008000 {
411 compatible = "ns16550a"; 381 compatible = "ns16550a";
412 reg = <0x18008000 0x20>; 382 reg = <0x18008000 0x20>;
413 clocks = <&iprocslow>; 383 clocks = <&iprocslow>;
414 interrupts = <GIC_SPI 86 IRQ_T 384 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
415 reg-shift = <2>; 385 reg-shift = <2>;
416 status = "disabled"; 386 status = "disabled";
417 }; 387 };
418 388
419 dmu-bus@1800c000 { 389 dmu-bus@1800c000 {
420 compatible = "simple-bus"; 390 compatible = "simple-bus";
421 ranges = <0 0x1800c000 0x1000> 391 ranges = <0 0x1800c000 0x1000>;
422 #address-cells = <1>; 392 #address-cells = <1>;
423 #size-cells = <1>; 393 #size-cells = <1>;
424 394
425 cru-bus@100 { 395 cru-bus@100 {
426 compatible = "brcm,ns- 396 compatible = "brcm,ns-cru", "simple-mfd";
427 reg = <0x100 0x1a4>; 397 reg = <0x100 0x1a4>;
428 ranges; 398 ranges;
429 #address-cells = <1>; 399 #address-cells = <1>;
430 #size-cells = <1>; 400 #size-cells = <1>;
431 401
432 usb2_phy: phy@164 { 402 usb2_phy: phy@164 {
433 compatible = " 403 compatible = "brcm,ns-usb2-phy";
434 reg = <0x164 0 404 reg = <0x164 0x4>;
435 brcm,syscon-cl 405 brcm,syscon-clkset = <&cru_clkset>;
436 clocks = <&gen 406 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
437 clock-names = 407 clock-names = "phy-ref-clk";
438 #phy-cells = < 408 #phy-cells = <0>;
439 }; 409 };
440 410
441 cru_clkset: syscon@180 411 cru_clkset: syscon@180 {
442 compatible = " 412 compatible = "brcm,cru-clkset", "syscon";
443 reg = <0x180 0 413 reg = <0x180 0x4>;
444 }; 414 };
445 415
446 pinctrl: pinctrl@1c0 { 416 pinctrl: pinctrl@1c0 {
447 compatible = " 417 compatible = "brcm,bcm4708-pinmux";
448 reg = <0x1c0 0 418 reg = <0x1c0 0x24>;
449 reg-names = "c 419 reg-names = "cru_gpio_control";
450 420
451 spi-pins { 421 spi-pins {
452 groups 422 groups = "spi_grp";
453 functi 423 function = "spi";
454 }; 424 };
455 425
456 pinmux_i2c: i2 426 pinmux_i2c: i2c-pins {
457 groups 427 groups = "i2c_grp";
458 functi 428 function = "i2c";
459 }; 429 };
460 430
461 pinmux_pwm: pw 431 pinmux_pwm: pwm-pins {
462 groups 432 groups = "pwm0_grp", "pwm1_grp",
463 433 "pwm2_grp", "pwm3_grp";
464 functi 434 function = "pwm";
465 }; 435 };
466 436
467 pinmux_uart1: 437 pinmux_uart1: uart1-pins {
468 groups 438 groups = "uart1_grp";
469 functi 439 function = "uart1";
470 }; 440 };
471 }; 441 };
472 442
473 thermal: thermal@2c0 { 443 thermal: thermal@2c0 {
474 compatible = " 444 compatible = "brcm,ns-thermal";
475 reg = <0x2c0 0 445 reg = <0x2c0 0x10>;
476 #thermal-senso 446 #thermal-sensor-cells = <0>;
477 }; 447 };
478 }; 448 };
479 }; 449 };
480 450
481 nand_controller: nand-controller@18028 451 nand_controller: nand-controller@18028000 {
482 compatible = "brcm,nand-iproc" 452 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
483 reg = <0x18028000 0x600>, <0x1 453 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
484 reg-names = "nand", "iproc-idm 454 reg-names = "nand", "iproc-idm", "iproc-ext";
485 interrupts = <GIC_SPI 68 IRQ_T 455 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
486 456
487 #address-cells = <1>; 457 #address-cells = <1>;
488 #size-cells = <0>; 458 #size-cells = <0>;
489 459
490 brcm,nand-has-wp; 460 brcm,nand-has-wp;
491 }; <<
492 <<
493 usb3_dmp: syscon@18105000 { <<
494 reg = <0x18105000 0x1000>; <<
495 }; 461 };
496 462
497 thermal-zones { 463 thermal-zones {
498 cpu_thermal: cpu-thermal { 464 cpu_thermal: cpu-thermal {
499 polling-delay-passive 465 polling-delay-passive = <0>;
500 polling-delay = <1000> 466 polling-delay = <1000>;
501 coefficients = <(-556) 467 coefficients = <(-556) 418000>;
502 thermal-sensors = <&th 468 thermal-sensors = <&thermal>;
503 469
504 trips { 470 trips {
505 cpu-crit { 471 cpu-crit {
506 temper 472 temperature = <125000>;
507 hyster 473 hysteresis = <0>;
508 type = 474 type = "critical";
509 }; 475 };
510 }; 476 };
511 477
512 cooling-maps { 478 cooling-maps {
513 }; 479 };
514 }; 480 };
515 }; 481 };
516 }; 482 };
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