1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Broadcom Ltd. 3 * Copyright 2022 Broadcom Ltd.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
8 8
9 / { 9 / {
10 compatible = "brcm,bcm63148", "brcm,bc 10 compatible = "brcm,bcm63148", "brcm,bcmbca";
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 13
14 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 B15_0: cpu@0 { 20 B15_0: cpu@0 {
21 device_type = "cpu"; 21 device_type = "cpu";
22 compatible = "brcm,bra 22 compatible = "brcm,brahma-b15";
23 reg = <0x0>; 23 reg = <0x0>;
24 next-level-cache = <&L 24 next-level-cache = <&L2_0>;
25 enable-method = "psci" 25 enable-method = "psci";
26 }; 26 };
27 27
28 B15_1: cpu@1 { 28 B15_1: cpu@1 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 compatible = "brcm,bra 30 compatible = "brcm,brahma-b15";
31 reg = <0x1>; 31 reg = <0x1>;
32 next-level-cache = <&L 32 next-level-cache = <&L2_0>;
33 enable-method = "psci" 33 enable-method = "psci";
34 }; 34 };
35 35
36 L2_0: l2-cache0 { 36 L2_0: l2-cache0 {
37 compatible = "cache"; 37 compatible = "cache";
38 cache-level = <2>; 38 cache-level = <2>;
39 cache-unified; 39 cache-unified;
40 }; 40 };
41 }; 41 };
42 42
43 timer { 43 timer {
44 compatible = "arm,armv7-timer" 44 compatible = "arm,armv7-timer";
45 interrupts = <GIC_PPI 13 (GIC_ 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 14 (GIC_CPU_M 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 11 (GIC_CPU_M 47 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 10 (GIC_CPU_M 48 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
49 }; 49 };
50 50
51 pmu: pmu { 51 pmu: pmu {
52 compatible = "arm,cortex-a15-p 52 compatible = "arm,cortex-a15-pmu";
53 interrupts = <GIC_SPI 8 IRQ_TY 53 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 9 IRQ_TYPE_LE 54 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-affinity = <&B15_0>, 55 interrupt-affinity = <&B15_0>, <&B15_1>;
56 }; 56 };
57 57
58 clocks: clocks { 58 clocks: clocks {
59 periph_clk: periph-clk { 59 periph_clk: periph-clk {
60 compatible = "fixed-cl 60 compatible = "fixed-clock";
61 #clock-cells = <0>; 61 #clock-cells = <0>;
62 clock-frequency = <500 62 clock-frequency = <50000000>;
63 }; 63 };
64 64
65 hsspi_pll: hsspi-pll { 65 hsspi_pll: hsspi-pll {
66 compatible = "fixed-cl 66 compatible = "fixed-clock";
67 #clock-cells = <0>; 67 #clock-cells = <0>;
68 clock-frequency = <400 68 clock-frequency = <400000000>;
69 }; 69 };
70 }; 70 };
71 71
72 psci { 72 psci {
73 compatible = "arm,psci-0.2"; 73 compatible = "arm,psci-0.2";
74 method = "smc"; 74 method = "smc";
75 }; 75 };
76 76
77 axi@80030000 { 77 axi@80030000 {
78 compatible = "simple-bus"; 78 compatible = "simple-bus";
79 #address-cells = <1>; 79 #address-cells = <1>;
80 #size-cells = <1>; 80 #size-cells = <1>;
81 ranges = <0 0x80030000 0x8000> 81 ranges = <0 0x80030000 0x8000>;
82 82
83 gic: interrupt-controller@1000 83 gic: interrupt-controller@1000 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a15-gic";
85 #interrupt-cells = <3> 85 #interrupt-cells = <3>;
86 interrupt-controller; 86 interrupt-controller;
87 reg = <0x1000 0x1000>, 87 reg = <0x1000 0x1000>,
88 <0x2000 0x2000 88 <0x2000 0x2000>,
89 <0x4000 0x2000 89 <0x4000 0x2000>,
90 <0x6000 0x2000 90 <0x6000 0x2000>;
91 interrupts = <GIC_PPI 91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
92 IRQ_TY 92 IRQ_TYPE_LEVEL_HIGH)>;
93 }; 93 };
94 }; 94 };
95 95
96 bus@ff800000 { 96 bus@ff800000 {
97 compatible = "simple-bus"; 97 compatible = "simple-bus";
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <1>; 99 #size-cells = <1>;
100 ranges = <0 0xfffe8000 0x8000> 100 ranges = <0 0xfffe8000 0x8000>;
101 101
102 uart0: serial@600 { 102 uart0: serial@600 {
103 compatible = "brcm,bcm 103 compatible = "brcm,bcm6345-uart";
104 reg = <0x600 0x20>; 104 reg = <0x600 0x20>;
105 interrupts = <GIC_SPI 105 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&periph_clk> 106 clocks = <&periph_clk>;
107 clock-names = "refclk" 107 clock-names = "refclk";
108 status = "disabled"; 108 status = "disabled";
109 }; 109 };
110 110
111 hsspi: spi@1000 { 111 hsspi: spi@1000 {
112 #address-cells = <1>; 112 #address-cells = <1>;
113 #size-cells = <0>; 113 #size-cells = <0>;
114 compatible = "brcm,bcm 114 compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
115 reg = <0x1000 0x600>; 115 reg = <0x1000 0x600>;
116 interrupts = <GIC_SPI 116 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&hsspi_pll & 117 clocks = <&hsspi_pll &hsspi_pll>;
118 clock-names = "hsspi", 118 clock-names = "hsspi", "pll";
119 num-cs = <8>; 119 num-cs = <8>;
120 status = "disabled"; 120 status = "disabled";
121 }; 121 };
122 <<
123 nand_controller: nand-controll <<
124 #address-cells = <1>; <<
125 #size-cells = <0>; <<
126 compatible = "brcm,nan <<
127 reg = <0x2000 0x600>, <<
128 reg-names = "nand", "n <<
129 status = "disabled"; <<
130 <<
131 nandcs: nand@0 { <<
132 compatible = " <<
133 reg = <0>; <<
134 }; <<
135 }; <<
136 }; 122 };
137 }; 123 };
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