1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright 2011-2012 Calxeda, Inc.
4 */ 4 */
5 5
6 / { 6 / {
7 chosen { 7 chosen {
8 bootargs = "console=ttyAMA0"; 8 bootargs = "console=ttyAMA0";
9 }; 9 };
10 10
11 psci { 11 psci {
12 compatible = "arm,psci"; 12 compatible = "arm,psci";
13 method = "smc"; 13 method = "smc";
14 cpu_suspend = <0x84000002>; 14 cpu_suspend = <0x84000002>;
15 cpu_off = <0x84000004>; 15 cpu_off = <0x84000004>;
16 cpu_on = <0x84000006>; 16 cpu_on = <0x84000006>;
17 }; 17 };
18 18
19 soc { 19 soc {
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 compatible = "simple-bus"; 22 compatible = "simple-bus";
23 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
24 24
25 sata@ffe08000 { 25 sata@ffe08000 {
26 compatible = "calxeda, 26 compatible = "calxeda,hb-ahci";
27 reg = <0xffe08000 0x10 27 reg = <0xffe08000 0x10000>;
28 interrupts = <0 83 4>; 28 interrupts = <0 83 4>;
29 dma-coherent; 29 dma-coherent;
30 calxeda,port-phys = < 30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
31 < 31 <&combophy0 1>, <&combophy0 2>,
32 < 32 <&combophy0 3>;
33 calxeda,sgpio-gpio =<& 33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
34 <& 34 <&gpioh 7 1>;
35 calxeda,led-order = <4 35 calxeda,led-order = <4 0 1 2 3>;
36 }; 36 };
37 37
38 sdhci@ffe0e000 { 38 sdhci@ffe0e000 {
39 compatible = "calxeda, 39 compatible = "calxeda,hb-sdhci";
40 reg = <0xffe0e000 0x10 40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>; 41 interrupts = <0 90 4>;
42 clocks = <&eclk>; 42 clocks = <&eclk>;
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 ipc@fff20000 { 46 ipc@fff20000 {
47 compatible = "arm,pl32 47 compatible = "arm,pl320", "arm,primecell";
48 reg = <0xfff20000 0x10 48 reg = <0xfff20000 0x1000>;
49 interrupts = <0 7 4>; 49 interrupts = <0 7 4>;
50 clocks = <&pclk>; 50 clocks = <&pclk>;
51 clock-names = "apb_pcl 51 clock-names = "apb_pclk";
52 }; 52 };
53 53
54 gpioe: gpio@fff30000 { 54 gpioe: gpio@fff30000 {
55 #gpio-cells = <2>; 55 #gpio-cells = <2>;
56 compatible = "arm,pl06 56 compatible = "arm,pl061", "arm,primecell";
57 gpio-controller; 57 gpio-controller;
58 reg = <0xfff30000 0x10 58 reg = <0xfff30000 0x1000>;
59 interrupts = <0 14 4>; 59 interrupts = <0 14 4>;
60 clocks = <&pclk>; 60 clocks = <&pclk>;
61 clock-names = "apb_pcl 61 clock-names = "apb_pclk";
62 status = "disabled"; 62 status = "disabled";
63 }; 63 };
64 64
65 gpiof: gpio@fff31000 { 65 gpiof: gpio@fff31000 {
66 #gpio-cells = <2>; 66 #gpio-cells = <2>;
67 compatible = "arm,pl06 67 compatible = "arm,pl061", "arm,primecell";
68 gpio-controller; 68 gpio-controller;
69 reg = <0xfff31000 0x10 69 reg = <0xfff31000 0x1000>;
70 interrupts = <0 15 4>; 70 interrupts = <0 15 4>;
71 clocks = <&pclk>; 71 clocks = <&pclk>;
72 clock-names = "apb_pcl 72 clock-names = "apb_pclk";
73 status = "disabled"; 73 status = "disabled";
74 }; 74 };
75 75
76 gpiog: gpio@fff32000 { 76 gpiog: gpio@fff32000 {
77 #gpio-cells = <2>; 77 #gpio-cells = <2>;
78 compatible = "arm,pl06 78 compatible = "arm,pl061", "arm,primecell";
79 gpio-controller; 79 gpio-controller;
80 reg = <0xfff32000 0x10 80 reg = <0xfff32000 0x1000>;
81 interrupts = <0 16 4>; 81 interrupts = <0 16 4>;
82 clocks = <&pclk>; 82 clocks = <&pclk>;
83 clock-names = "apb_pcl 83 clock-names = "apb_pclk";
84 status = "disabled"; 84 status = "disabled";
85 }; 85 };
86 86
87 gpioh: gpio@fff33000 { 87 gpioh: gpio@fff33000 {
88 #gpio-cells = <2>; 88 #gpio-cells = <2>;
89 compatible = "arm,pl06 89 compatible = "arm,pl061", "arm,primecell";
90 gpio-controller; 90 gpio-controller;
91 reg = <0xfff33000 0x10 91 reg = <0xfff33000 0x1000>;
92 interrupts = <0 17 4>; 92 interrupts = <0 17 4>;
93 clocks = <&pclk>; 93 clocks = <&pclk>;
94 clock-names = "apb_pcl 94 clock-names = "apb_pclk";
95 status = "disabled"; 95 status = "disabled";
96 }; 96 };
97 97
98 timer@fff34000 { 98 timer@fff34000 {
99 compatible = "arm,sp80 99 compatible = "arm,sp804", "arm,primecell";
100 reg = <0xfff34000 0x10 100 reg = <0xfff34000 0x1000>;
101 interrupts = <0 18 4>; 101 interrupts = <0 18 4>;
102 clocks = <&pclk>; 102 clocks = <&pclk>;
103 clock-names = "apb_pcl 103 clock-names = "apb_pclk";
104 }; 104 };
105 105
106 rtc@fff35000 { 106 rtc@fff35000 {
107 compatible = "arm,pl03 107 compatible = "arm,pl031", "arm,primecell";
108 reg = <0xfff35000 0x10 108 reg = <0xfff35000 0x1000>;
109 interrupts = <0 19 4>; 109 interrupts = <0 19 4>;
110 clocks = <&pclk>; 110 clocks = <&pclk>;
111 clock-names = "apb_pcl 111 clock-names = "apb_pclk";
112 }; 112 };
113 113
114 serial@fff36000 { 114 serial@fff36000 {
115 compatible = "arm,pl01 115 compatible = "arm,pl011", "arm,primecell";
116 reg = <0xfff36000 0x10 116 reg = <0xfff36000 0x1000>;
117 interrupts = <0 20 4>; 117 interrupts = <0 20 4>;
118 clocks = <&pclk>, <&pc 118 clocks = <&pclk>, <&pclk>;
119 clock-names = "uartclk 119 clock-names = "uartclk", "apb_pclk";
120 }; 120 };
121 121
122 smic@fff3a000 { 122 smic@fff3a000 {
123 compatible = "ipmi-smi 123 compatible = "ipmi-smic";
124 device_type = "ipmi"; 124 device_type = "ipmi";
125 reg = <0xfff3a000 0x10 125 reg = <0xfff3a000 0x1000>;
126 interrupts = <0 24 4>; 126 interrupts = <0 24 4>;
127 reg-size = <4>; 127 reg-size = <4>;
128 reg-spacing = <4>; 128 reg-spacing = <4>;
129 }; 129 };
130 130
131 sregs@fff3c000 { 131 sregs@fff3c000 {
132 compatible = "calxeda, 132 compatible = "calxeda,hb-sregs";
133 reg = <0xfff3c000 0x10 133 reg = <0xfff3c000 0x1000>;
134 134
135 clocks { 135 clocks {
136 #address-cells 136 #address-cells = <1>;
137 #size-cells = 137 #size-cells = <0>;
138 138
139 osc: oscillato 139 osc: oscillator {
140 #clock 140 #clock-cells = <0>;
141 compat 141 compatible = "fixed-clock";
142 clock- 142 clock-frequency = <33333000>;
143 }; 143 };
144 144
145 ddrpll: ddrpll 145 ddrpll: ddrpll {
146 #clock 146 #clock-cells = <0>;
147 compat 147 compatible = "calxeda,hb-pll-clock";
148 clocks 148 clocks = <&osc>;
149 reg = 149 reg = <0x108>;
150 }; 150 };
151 151
152 a9pll: a9pll { 152 a9pll: a9pll {
153 #clock 153 #clock-cells = <0>;
154 compat 154 compatible = "calxeda,hb-pll-clock";
155 clocks 155 clocks = <&osc>;
156 reg = 156 reg = <0x100>;
157 }; 157 };
158 158
159 a9periphclk: a 159 a9periphclk: a9periphclk {
160 #clock 160 #clock-cells = <0>;
161 compat 161 compatible = "calxeda,hb-a9periph-clock";
162 clocks 162 clocks = <&a9pll>;
163 reg = 163 reg = <0x104>;
164 }; 164 };
165 165
166 a9bclk: a9bclk 166 a9bclk: a9bclk {
167 #clock 167 #clock-cells = <0>;
168 compat 168 compatible = "calxeda,hb-a9bus-clock";
169 clocks 169 clocks = <&a9pll>;
170 reg = 170 reg = <0x104>;
171 }; 171 };
172 172
173 emmcpll: emmcp 173 emmcpll: emmcpll {
174 #clock 174 #clock-cells = <0>;
175 compat 175 compatible = "calxeda,hb-pll-clock";
176 clocks 176 clocks = <&osc>;
177 reg = 177 reg = <0x10C>;
178 }; 178 };
179 179
180 eclk: eclk { 180 eclk: eclk {
181 #clock 181 #clock-cells = <0>;
182 compat 182 compatible = "calxeda,hb-emmc-clock";
183 clocks 183 clocks = <&emmcpll>;
184 reg = 184 reg = <0x114>;
185 }; 185 };
186 186
187 pclk: pclk { 187 pclk: pclk {
188 #clock 188 #clock-cells = <0>;
189 compat 189 compatible = "fixed-clock";
190 clock- 190 clock-frequency = <150000000>;
191 }; 191 };
192 }; 192 };
193 }; 193 };
194 194
195 dma@fff3d000 { 195 dma@fff3d000 {
196 compatible = "arm,pl33 196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0xfff3d000 0x10 197 reg = <0xfff3d000 0x1000>;
198 interrupts = <0 92 4>; 198 interrupts = <0 92 4>;
199 clocks = <&pclk>; 199 clocks = <&pclk>;
200 clock-names = "apb_pcl 200 clock-names = "apb_pclk";
201 }; 201 };
202 202
203 ethernet@fff50000 { 203 ethernet@fff50000 {
204 compatible = "calxeda, 204 compatible = "calxeda,hb-xgmac";
205 reg = <0xfff50000 0x10 205 reg = <0xfff50000 0x1000>;
206 interrupts = <0 77 4>, 206 interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
207 dma-coherent; 207 dma-coherent;
208 }; 208 };
209 209
210 ethernet@fff51000 { 210 ethernet@fff51000 {
211 compatible = "calxeda, 211 compatible = "calxeda,hb-xgmac";
212 reg = <0xfff51000 0x10 212 reg = <0xfff51000 0x1000>;
213 interrupts = <0 80 4>, 213 interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
214 dma-coherent; 214 dma-coherent;
215 }; 215 };
216 216
217 combophy0: combo-phy@fff58000 217 combophy0: combo-phy@fff58000 {
218 compatible = "calxeda, 218 compatible = "calxeda,hb-combophy";
219 #phy-cells = <1>; 219 #phy-cells = <1>;
220 reg = <0xfff58000 0x10 220 reg = <0xfff58000 0x1000>;
221 phydev = <5>; 221 phydev = <5>;
222 }; 222 };
223 223
224 combophy5: combo-phy@fff5d000 224 combophy5: combo-phy@fff5d000 {
225 compatible = "calxeda, 225 compatible = "calxeda,hb-combophy";
226 #phy-cells = <1>; 226 #phy-cells = <1>;
227 reg = <0xfff5d000 0x10 227 reg = <0xfff5d000 0x1000>;
228 phydev = <31>; 228 phydev = <31>;
229 }; 229 };
230 }; 230 };
231 }; 231 };
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